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git.proxmox.com Git - mirror_edk2.git/blob - MdePkg/Library/BaseCacheMaintenanceLib/X86Cache.c
2 Cache Maintenance Functions.
4 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
11 #include <Library/BaseLib.h>
12 #include <Library/DebugLib.h>
15 Invalidates the entire instruction cache in cache coherency domain of the
21 InvalidateInstructionCache (
28 Invalidates a range of instruction cache lines in the cache coherency domain
31 Invalidates the instruction cache lines specified by Address and Length. If
32 Address is not aligned on a cache line boundary, then entire instruction
33 cache line containing Address is invalidated. If Address + Length is not
34 aligned on a cache line boundary, then the entire instruction cache line
35 containing Address + Length -1 is invalidated. This function may choose to
36 invalidate the entire instruction cache if that is more efficient than
37 invalidating the specified range. If Length is 0, then no instruction cache
38 lines are invalidated. Address is returned.
40 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
42 @param Address The base address of the instruction cache lines to
43 invalidate. If the CPU is in a physical addressing mode, then
44 Address is a physical address. If the CPU is in a virtual
45 addressing mode, then Address is a virtual address.
47 @param Length The number of bytes to invalidate from the instruction cache.
54 InvalidateInstructionCacheRange (
63 ASSERT ((Length
- 1) <= (MAX_ADDRESS
- (UINTN
)Address
));
68 Writes back and invalidates the entire data cache in cache coherency domain
71 Writes back and invalidates the entire data cache in cache coherency domain
72 of the calling CPU. This function guarantees that all dirty cache lines are
73 written back to system memory, and also invalidates all the data cache lines
74 in the cache coherency domain of the calling CPU.
79 WriteBackInvalidateDataCache (
87 Writes back and invalidates a range of data cache lines in the cache
88 coherency domain of the calling CPU.
90 Writes back and invalidates the data cache lines specified by Address and
91 Length. If Address is not aligned on a cache line boundary, then entire data
92 cache line containing Address is written back and invalidated. If Address +
93 Length is not aligned on a cache line boundary, then the entire data cache
94 line containing Address + Length -1 is written back and invalidated. This
95 function may choose to write back and invalidate the entire data cache if
96 that is more efficient than writing back and invalidating the specified
97 range. If Length is 0, then no data cache lines are written back and
98 invalidated. Address is returned.
100 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
102 @param Address The base address of the data cache lines to write back and
103 invalidate. If the CPU is in a physical addressing mode, then
104 Address is a physical address. If the CPU is in a virtual
105 addressing mode, then Address is a virtual address.
106 @param Length The number of bytes to write back and invalidate from the
109 @return Address of cache invalidation.
114 WriteBackInvalidateDataCacheRange (
129 ASSERT ((Length
- 1) <= (MAX_ADDRESS
- (UINTN
)Address
));
132 // If the CPU does not support CLFLUSH instruction,
133 // then promote flush range to flush entire cache.
135 AsmCpuid (0x01, NULL
, &RegEbx
, NULL
, &RegEdx
);
136 if ((RegEdx
& BIT19
) == 0) {
142 // Cache line size is 8 * Bits 15-08 of EBX returned from CPUID 01H
144 CacheLineSize
= (RegEbx
& 0xff00) >> 5;
146 Start
= (UINTN
)Address
;
148 // Calculate the cache line alignment
150 End
= (Start
+ Length
+ (CacheLineSize
- 1)) & ~(CacheLineSize
- 1);
151 Start
&= ~((UINTN
)CacheLineSize
- 1);
154 Start
= (UINTN
)AsmFlushCacheLine ((VOID
*)Start
) + CacheLineSize
;
155 } while (Start
!= End
);
160 Writes back the entire data cache in cache coherency domain of the calling
163 Writes back the entire data cache in cache coherency domain of the calling
164 CPU. This function guarantees that all dirty cache lines are written back to
165 system memory. This function may also invalidate all the data cache lines in
166 the cache coherency domain of the calling CPU.
175 WriteBackInvalidateDataCache ();
179 Writes back a range of data cache lines in the cache coherency domain of the
182 Writes back the data cache lines specified by Address and Length. If Address
183 is not aligned on a cache line boundary, then entire data cache line
184 containing Address is written back. If Address + Length is not aligned on a
185 cache line boundary, then the entire data cache line containing Address +
186 Length -1 is written back. This function may choose to write back the entire
187 data cache if that is more efficient than writing back the specified range.
188 If Length is 0, then no data cache lines are written back. This function may
189 also invalidate all the data cache lines in the specified range of the cache
190 coherency domain of the calling CPU. Address is returned.
192 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
194 @param Address The base address of the data cache lines to write back. If
195 the CPU is in a physical addressing mode, then Address is a
196 physical address. If the CPU is in a virtual addressing
197 mode, then Address is a virtual address.
198 @param Length The number of bytes to write back from the data cache.
200 @return Address of cache written in main memory.
205 WriteBackDataCacheRange (
210 return WriteBackInvalidateDataCacheRange (Address
, Length
);
214 Invalidates the entire data cache in cache coherency domain of the calling
217 Invalidates the entire data cache in cache coherency domain of the calling
218 CPU. This function must be used with care because dirty cache lines are not
219 written back to system memory. It is typically used for cache diagnostics. If
220 the CPU does not support invalidation of the entire data cache, then a write
221 back and invalidate operation should be performed on the entire data cache.
226 InvalidateDataCache (
234 Invalidates a range of data cache lines in the cache coherency domain of the
237 Invalidates the data cache lines specified by Address and Length. If Address
238 is not aligned on a cache line boundary, then entire data cache line
239 containing Address is invalidated. If Address + Length is not aligned on a
240 cache line boundary, then the entire data cache line containing Address +
241 Length -1 is invalidated. This function must never invalidate any cache lines
242 outside the specified range. If Length is 0, then no data cache lines are
243 invalidated. Address is returned. This function must be used with care
244 because dirty cache lines are not written back to system memory. It is
245 typically used for cache diagnostics. If the CPU does not support
246 invalidation of a data cache range, then a write back and invalidate
247 operation should be performed on the data cache range.
249 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
251 @param Address The base address of the data cache lines to invalidate. If
252 the CPU is in a physical addressing mode, then Address is a
253 physical address. If the CPU is in a virtual addressing mode,
254 then Address is a virtual address.
255 @param Length The number of bytes to invalidate from the data cache.
262 InvalidateDataCacheRange (
268 // Invalidation of a data cache range without writing back is not supported on
269 // x86 architecture, so write back and invalidate operation is performed.
271 return WriteBackInvalidateDataCacheRange (Address
, Length
);