MdePkg/Library/BaseCacheMaintenanceLib/X86Cache.c

   1 /** @file
   2   Cache Maintenance Functions.
   3
   4   Copyright (c) 2006 - 2008, Intel Corporation<BR>
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13
  14 **/
  15
  16 #include <Base.h>
  17 #include <Library/BaseLib.h>
  18 #include <Library/DebugLib.h>
  19
  20 //
  21 // This size must be at or below the smallest cache size possible among all
  22 // supported processors
  23 //
  24 #define CACHE_LINE_SIZE             0x20
  25
  26 /**
  27   Invalidates the entire instruction cache in cache coherency domain of the
  28   calling CPU.
  29
  30 **/
  31 VOID
  32 EFIAPI
  33 InvalidateInstructionCache (
  34   VOID
  35   )
  36 {
  37 }
  38
  39 /**
  40   Invalidates a range of instruction cache lines in the cache coherency domain
  41   of the calling CPU.
  42
  43   Invalidates the instruction cache lines specified by Address and Length. If
  44   Address is not aligned on a cache line boundary, then entire instruction
  45   cache line containing Address is invalidated. If Address + Length is not
  46   aligned on a cache line boundary, then the entire instruction cache line
  47   containing Address + Length -1 is invalidated. This function may choose to
  48   invalidate the entire instruction cache if that is more efficient than
  49   invalidating the specified range. If Length is 0, the no instruction cache
  50   lines are invalidated. Address is returned.
  51
  52   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
  53
  54   @param  Address The base address of the instruction cache lines to
  55                   invalidate. If the CPU is in a physical addressing mode, then
  56                   Address is a physical address. If the CPU is in a virtual
  57                   addressing mode, then Address is a virtual address.
  58
  59   @param  Length  The number of bytes to invalidate from the instruction cache.
  60
  61   @return Address of cache invalidation.
  62
  63 **/
  64 VOID *
  65 EFIAPI
  66 InvalidateInstructionCacheRange (
  67   IN      VOID                      *Address,
  68   IN      UINTN                     Length
  69   )
  70 {
  71   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
  72   return Address;
  73 }
  74
  75 /**
  76   Writes Back and Invalidates the entire data cache in cache coherency domain
  77   of the calling CPU.
  78
  79   Writes Back and Invalidates the entire data cache in cache coherency domain
  80   of the calling CPU. This function guarantees that all dirty cache lines are
  81   written back to system memory, and also invalidates all the data cache lines
  82   in the cache coherency domain of the calling CPU.
  83
  84 **/
  85 VOID
  86 EFIAPI
  87 WriteBackInvalidateDataCache (
  88   VOID
  89   )
  90 {
  91   AsmWbinvd ();
  92 }
  93
  94 /**
  95   Writes Back and Invalidates a range of data cache lines in the cache
  96   coherency domain of the calling CPU.
  97
  98   Writes Back and Invalidate the data cache lines specified by Address and
  99   Length. If Address is not aligned on a cache line boundary, then entire data
 100   cache line containing Address is written back and invalidated. If Address +
 101   Length is not aligned on a cache line boundary, then the entire data cache
 102   line containing Address + Length -1 is written back and invalidated. This
 103   function may choose to write back and invalidate the entire data cache if
 104   that is more efficient than writing back and invalidating the specified
 105   range. If Length is 0, the no data cache lines are written back and
 106   invalidated. Address is returned.
 107
 108   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 109
 110   @param  Address The base address of the data cache lines to write back and
 111                   invalidate. If the CPU is in a physical addressing mode, then
 112                   Address is a physical address. If the CPU is in a virtual
 113                   addressing mode, then Address is a virtual address.
 114   @param  Length  The number of bytes to write back and invalidate from the
 115                   data cache.
 116
 117   @return Address of cache invalidation.
 118
 119 **/
 120 VOID *
 121 EFIAPI
 122 WriteBackInvalidateDataCacheRange (
 123   IN      VOID                      *Address,
 124   IN      UINTN                     Length
 125   )
 126 {
 127   UINTN                             Start;
 128   UINTN                             End;
 129
 130   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
 131
 132   if (Length == 0) {
 133     return Address;
 134   }
 135
 136   Start = (UINTN)Address;
 137   //
 138   // Calculate the cache line alignment
 139   //
 140   End = (Start + Length + (CACHE_LINE_SIZE - 1)) & ~(CACHE_LINE_SIZE - 1);
 141   Start &= ~(CACHE_LINE_SIZE - 1);
 142
 143   do {
 144     Start = (UINTN)AsmFlushCacheLine ((VOID*)Start) + CACHE_LINE_SIZE;
 145   } while (Start != End);
 146   return Address;
 147 }
 148
 149 /**
 150   Writes Back the entire data cache in cache coherency domain of the calling
 151   CPU.
 152
 153   Writes Back the entire data cache in cache coherency domain of the calling
 154   CPU. This function guarantees that all dirty cache lines are written back to
 155   system memory. This function may also invalidate all the data cache lines in
 156   the cache coherency domain of the calling CPU.
 157
 158 **/
 159 VOID
 160 EFIAPI
 161 WriteBackDataCache (
 162   VOID
 163   )
 164 {
 165   WriteBackInvalidateDataCache ();
 166 }
 167
 168 /**
 169   Writes Back a range of data cache lines in the cache coherency domain of the
 170   calling CPU.
 171
 172   Writes Back the data cache lines specified by Address and Length. If Address
 173   is not aligned on a cache line boundary, then entire data cache line
 174   containing Address is written back. If Address + Length is not aligned on a
 175   cache line boundary, then the entire data cache line containing Address +
 176   Length -1 is written back. This function may choose to write back the entire
 177   data cache if that is more efficient than writing back the specified range.
 178   If Length is 0, the no data cache lines are written back. This function may
 179   also invalidate all the data cache lines in the specified range of the cache
 180   coherency domain of the calling CPU. Address is returned.
 181
 182   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 183
 184   @param  Address The base address of the data cache lines to write back. If
 185                   the CPU is in a physical addressing mode, then Address is a
 186                   physical address. If the CPU is in a virtual addressing
 187                   mode, then Address is a virtual address.
 188   @param  Length  The number of bytes to write back from the data cache.
 189
 190   @return Address of cache written in main memory.
 191
 192 **/
 193 VOID *
 194 EFIAPI
 195 WriteBackDataCacheRange (
 196   IN      VOID                      *Address,
 197   IN      UINTN                     Length
 198   )
 199 {
 200   return WriteBackInvalidateDataCacheRange (Address, Length);
 201 }
 202
 203 /**
 204   Invalidates the entire data cache in cache coherency domain of the calling
 205   CPU.
 206
 207   Invalidates the entire data cache in cache coherency domain of the calling
 208   CPU. This function must be used with care because dirty cache lines are not
 209   written back to system memory. It is typically used for cache diagnostics. If
 210   the CPU does not support invalidation of the entire data cache, then a write
 211   back and invalidate operation should be performed on the entire data cache.
 212
 213 **/
 214 VOID
 215 EFIAPI
 216 InvalidateDataCache (
 217   VOID
 218   )
 219 {
 220   AsmInvd ();
 221 }
 222
 223 /**
 224   Invalidates a range of data cache lines in the cache coherency domain of the
 225   calling CPU.
 226
 227   Invalidates the data cache lines specified by Address and Length. If Address
 228   is not aligned on a cache line boundary, then entire data cache line
 229   containing Address is invalidated. If Address + Length is not aligned on a
 230   cache line boundary, then the entire data cache line containing Address +
 231   Length -1 is invalidated. This function must never invalidate any cache lines
 232   outside the specified range. If Length is 0, the no data cache lines are
 233   invalidated. Address is returned. This function must be used with care
 234   because dirty cache lines are not written back to system memory. It is
 235   typically used for cache diagnostics. If the CPU does not support
 236   invalidation of a data cache range, then a write back and invalidate
 237   operation should be performed on the data cache range.
 238
 239   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 240
 241   @param  Address The base address of the data cache lines to invalidate. If
 242                   the CPU is in a physical addressing mode, then Address is a
 243                   physical address. If the CPU is in a virtual addressing mode,
 244                   then Address is a virtual address.
 245   @param  Length  The number of bytes to invalidate from the data cache.
 246
 247   @return Address of cache invalidation.
 248
 249 **/
 250 VOID *
 251 EFIAPI
 252 InvalidateDataCacheRange (
 253   IN      VOID                      *Address,
 254   IN      UINTN                     Length
 255   )
 256 {
 257   //
 258   // Invalidation of a data cache range without writing back is not supported on
 259   // x86 architecture, so write back and invalidate operation is performed.
 260   //
 261   return WriteBackInvalidateDataCacheRange (Address, Length);
 262 }