4 Copyright (c) 2006, Intel Corporation<BR>
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 // Declare I/O Ports used to perform PCI Confguration Cycles
20 #define PCI_CONFIGURATION_ADDRESS_PORT 0xCF8
21 #define PCI_CONFIGURATION_DATA_PORT 0xCFC
24 // Declare macro to convert PCI Library formatted address to CF8 formatted address
26 // PCI Library formatted address CF8 Formatted Address
27 // ============================= ======================
28 // Bits 00..11 Register Bits 00..07 Register
29 // Bits 12..14 Function Bits 08..10 Function
30 // Bits 15..19 Device Bits 11..15 Device
31 // Bits 20..27 Bus Bits 16..23 Bus
32 // Bits 28..31 Reserved(MBZ) Bits 24..30 Reserved(MBZ)
33 // Bits 31..31 Must be 1
37 Assert the validity of a PCI address. A valid PCI address should contain 1's
38 only in the low 28 bits.
40 @param A The address to validate.
41 @param M Additional bits to assert to be zero.
44 #define ASSERT_INVALID_PCI_ADDRESS(A,M) \
45 ASSERT (((A) & (~0xffff0ff | (M))) == 0)
48 Convert a PCI Express address to PCI CF8 address.
50 @param A The address to convert.
52 @retval The coverted address.
55 #define PCI_TO_CF8_ADDRESS(A) \
56 ((UINT32) ((((A) >> 4) & 0x00ffff00) | ((A) & 0xfc) | 0x80000000))
59 Reads an 8-bit PCI configuration register.
61 Reads and returns the 8-bit PCI configuration register specified by Address.
62 This function must guarantee that all PCI read and write operations are
65 If Address > 0x0FFFFFFF, then ASSERT().
66 If the register specified by Address >= 0x100, then ASSERT().
68 @param Address Address that encodes the PCI Bus, Device, Function and
71 @return The read value from the PCI configuration register.
80 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
81 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
82 return IoRead8 (PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 3));
86 Writes an 8-bit PCI configuration register.
88 Writes the 8-bit PCI configuration register specified by Address with the
89 value specified by Value. Value is returned. This function must guarantee
90 that all PCI read and write operations are serialized.
92 If Address > 0x0FFFFFFF, then ASSERT().
93 If the register specified by Address >= 0x100, then ASSERT().
95 @param Address Address that encodes the PCI Bus, Device, Function and
97 @param Value The value to write.
99 @return The value written to the PCI configuration register.
109 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
110 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
112 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 3),
118 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
121 Reads the 8-bit PCI configuration register specified by Address, performs a
122 bitwise inclusive OR between the read result and the value specified by
123 OrData, and writes the result to the 8-bit PCI configuration register
124 specified by Address. The value written to the PCI configuration register is
125 returned. This function must guarantee that all PCI read and write operations
128 If Address > 0x0FFFFFFF, then ASSERT().
129 If the register specified by Address >= 0x100, then ASSERT().
131 @param Address Address that encodes the PCI Bus, Device, Function and
133 @param OrData The value to OR with the PCI configuration register.
135 @return The value written back to the PCI configuration register.
145 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
146 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
148 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 3),
154 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
157 Reads the 8-bit PCI configuration register specified by Address, performs a
158 bitwise AND between the read result and the value specified by AndData, and
159 writes the result to the 8-bit PCI configuration register specified by
160 Address. The value written to the PCI configuration register is returned.
161 This function must guarantee that all PCI read and write operations are
164 If Address > 0x0FFFFFFF, then ASSERT().
165 If the register specified by Address >= 0x100, then ASSERT().
167 @param Address Address that encodes the PCI Bus, Device, Function and
169 @param AndData The value to AND with the PCI configuration register.
171 @return The value written back to the PCI configuration register.
181 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
182 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
184 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 3),
190 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
191 value, followed a bitwise inclusive OR with another 8-bit value.
193 Reads the 8-bit PCI configuration register specified by Address, performs a
194 bitwise AND between the read result and the value specified by AndData,
195 performs a bitwise inclusive OR between the result of the AND operation and
196 the value specified by OrData, and writes the result to the 8-bit PCI
197 configuration register specified by Address. The value written to the PCI
198 configuration register is returned. This function must guarantee that all PCI
199 read and write operations are serialized.
201 If Address > 0x0FFFFFFF, then ASSERT().
202 If the register specified by Address >= 0x100, then ASSERT().
204 @param Address Address that encodes the PCI Bus, Device, Function and
206 @param AndData The value to AND with the PCI configuration register.
207 @param OrData The value to OR with the result of the AND operation.
209 @return The value written back to the PCI configuration register.
220 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
221 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
222 return IoAndThenOr8 (
223 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 3),
230 Reads a bit field of a PCI configuration register.
232 Reads the bit field in an 8-bit PCI configuration register. The bit field is
233 specified by the StartBit and the EndBit. The value of the bit field is
236 If Address > 0x0FFFFFFF, then ASSERT().
237 If the register specified by Address >= 0x100, then ASSERT().
238 If StartBit is greater than 7, then ASSERT().
239 If EndBit is greater than 7, then ASSERT().
240 If EndBit is less than StartBit, then ASSERT().
242 @param Address PCI configuration register to read.
243 @param StartBit The ordinal of the least significant bit in the bit field.
245 @param EndBit The ordinal of the most significant bit in the bit field.
248 @return The value of the bit field read from the PCI configuration register.
253 PciCf8BitFieldRead8 (
259 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
260 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
261 return IoBitFieldRead8 (
262 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 3),
269 Writes a bit field to a PCI configuration register.
271 Writes Value to the bit field of the PCI configuration register. The bit
272 field is specified by the StartBit and the EndBit. All other bits in the
273 destination PCI configuration register are preserved. The new value of the
274 8-bit register is returned.
276 If Address > 0x0FFFFFFF, then ASSERT().
277 If the register specified by Address >= 0x100, then ASSERT().
278 If StartBit is greater than 7, then ASSERT().
279 If EndBit is greater than 7, then ASSERT().
280 If EndBit is less than StartBit, then ASSERT().
282 @param Address PCI configuration register to write.
283 @param StartBit The ordinal of the least significant bit in the bit field.
285 @param EndBit The ordinal of the most significant bit in the bit field.
287 @param Value New value of the bit field.
289 @return The value written back to the PCI configuration register.
294 PciCf8BitFieldWrite8 (
301 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
302 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
303 return IoBitFieldWrite8 (
304 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 3),
312 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
313 writes the result back to the bit field in the 8-bit port.
315 Reads the 8-bit PCI configuration register specified by Address, performs a
316 bitwise inclusive OR between the read result and the value specified by
317 OrData, and writes the result to the 8-bit PCI configuration register
318 specified by Address. The value written to the PCI configuration register is
319 returned. This function must guarantee that all PCI read and write operations
320 are serialized. Extra left bits in OrData are stripped.
322 If Address > 0x0FFFFFFF, then ASSERT().
323 If the register specified by Address >= 0x100, then ASSERT().
324 If StartBit is greater than 7, then ASSERT().
325 If EndBit is greater than 7, then ASSERT().
326 If EndBit is less than StartBit, then ASSERT().
328 @param Address PCI configuration register to write.
329 @param StartBit The ordinal of the least significant bit in the bit field.
331 @param EndBit The ordinal of the most significant bit in the bit field.
333 @param OrData The value to OR with the PCI configuration register.
335 @return The value written back to the PCI configuration register.
347 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
348 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
349 return IoBitFieldOr8 (
350 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 3),
358 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
359 AND, and writes the result back to the bit field in the 8-bit register.
361 Reads the 8-bit PCI configuration register specified by Address, performs a
362 bitwise AND between the read result and the value specified by AndData, and
363 writes the result to the 8-bit PCI configuration register specified by
364 Address. The value written to the PCI configuration register is returned.
365 This function must guarantee that all PCI read and write operations are
366 serialized. Extra left bits in AndData are stripped.
368 If Address > 0x0FFFFFFF, then ASSERT().
369 If the register specified by Address >= 0x100, then ASSERT().
370 If StartBit is greater than 7, then ASSERT().
371 If EndBit is greater than 7, then ASSERT().
372 If EndBit is less than StartBit, then ASSERT().
374 @param Address PCI configuration register to write.
375 @param StartBit The ordinal of the least significant bit in the bit field.
377 @param EndBit The ordinal of the most significant bit in the bit field.
379 @param AndData The value to AND with the PCI configuration register.
381 @return The value written back to the PCI configuration register.
393 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
394 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
395 return IoBitFieldAnd8 (
396 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 3),
404 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
405 bitwise inclusive OR, and writes the result back to the bit field in the
408 Reads the 8-bit PCI configuration register specified by Address, performs a
409 bitwise AND followed by a bitwise inclusive OR between the read result and
410 the value specified by AndData, and writes the result to the 8-bit PCI
411 configuration register specified by Address. The value written to the PCI
412 configuration register is returned. This function must guarantee that all PCI
413 read and write operations are serialized. Extra left bits in both AndData and
416 If Address > 0x0FFFFFFF, then ASSERT().
417 If the register specified by Address >= 0x100, then ASSERT().
418 If StartBit is greater than 7, then ASSERT().
419 If EndBit is greater than 7, then ASSERT().
420 If EndBit is less than StartBit, then ASSERT().
422 @param Address PCI configuration register to write.
423 @param StartBit The ordinal of the least significant bit in the bit field.
425 @param EndBit The ordinal of the most significant bit in the bit field.
427 @param AndData The value to AND with the PCI configuration register.
428 @param OrData The value to OR with the result of the AND operation.
430 @return The value written back to the PCI configuration register.
435 PciCf8BitFieldAndThenOr8(
443 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
444 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
445 return IoBitFieldAndThenOr8 (
446 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 3),
455 Reads a 16-bit PCI configuration register.
457 Reads and returns the 16-bit PCI configuration register specified by Address.
458 This function must guarantee that all PCI read and write operations are
461 If Address > 0x0FFFFFFF, then ASSERT().
462 If Address is not aligned on a 16-bit boundary, then ASSERT().
463 If the register specified by Address >= 0x100, then ASSERT().
465 @param Address Address that encodes the PCI Bus, Device, Function and
468 @return The read value from the PCI configuration register.
477 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
478 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
479 return IoRead16 (PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 2));
483 Writes a 16-bit PCI configuration register.
485 Writes the 16-bit PCI configuration register specified by Address with the
486 value specified by Value. Value is returned. This function must guarantee
487 that all PCI read and write operations are serialized.
489 If Address > 0x0FFFFFFF, then ASSERT().
490 If Address is not aligned on a 16-bit boundary, then ASSERT().
491 If the register specified by Address >= 0x100, then ASSERT().
493 @param Address Address that encodes the PCI Bus, Device, Function and
495 @param Value The value to write.
497 @return The value written to the PCI configuration register.
507 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
508 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
510 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 2),
516 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
519 Reads the 16-bit PCI configuration register specified by Address, performs a
520 bitwise inclusive OR between the read result and the value specified by
521 OrData, and writes the result to the 16-bit PCI configuration register
522 specified by Address. The value written to the PCI configuration register is
523 returned. This function must guarantee that all PCI read and write operations
526 If Address > 0x0FFFFFFF, then ASSERT().
527 If Address is not aligned on a 16-bit boundary, then ASSERT().
528 If the register specified by Address >= 0x100, then ASSERT().
530 @param Address Address that encodes the PCI Bus, Device, Function and
532 @param OrData The value to OR with the PCI configuration register.
534 @return The value written back to the PCI configuration register.
544 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
545 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
547 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 2),
553 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
556 Reads the 16-bit PCI configuration register specified by Address, performs a
557 bitwise AND between the read result and the value specified by AndData, and
558 writes the result to the 16-bit PCI configuration register specified by
559 Address. The value written to the PCI configuration register is returned.
560 This function must guarantee that all PCI read and write operations are
563 If Address > 0x0FFFFFFF, then ASSERT().
564 If Address is not aligned on a 16-bit boundary, then ASSERT().
565 If the register specified by Address >= 0x100, then ASSERT().
567 @param Address Address that encodes the PCI Bus, Device, Function and
569 @param AndData The value to AND with the PCI configuration register.
571 @return The value written back to the PCI configuration register.
581 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
582 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
584 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 2),
590 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
591 value, followed a bitwise inclusive OR with another 16-bit value.
593 Reads the 16-bit PCI configuration register specified by Address, performs a
594 bitwise AND between the read result and the value specified by AndData,
595 performs a bitwise inclusive OR between the result of the AND operation and
596 the value specified by OrData, and writes the result to the 16-bit PCI
597 configuration register specified by Address. The value written to the PCI
598 configuration register is returned. This function must guarantee that all PCI
599 read and write operations are serialized.
601 If Address > 0x0FFFFFFF, then ASSERT().
602 If Address is not aligned on a 16-bit boundary, then ASSERT().
603 If the register specified by Address >= 0x100, then ASSERT().
605 @param Address Address that encodes the PCI Bus, Device, Function and
607 @param AndData The value to AND with the PCI configuration register.
608 @param OrData The value to OR with the result of the AND operation.
610 @return The value written back to the PCI configuration register.
621 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
622 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
623 return IoAndThenOr16 (
624 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 2),
631 Reads a bit field of a PCI configuration register.
633 Reads the bit field in a 16-bit PCI configuration register. The bit field is
634 specified by the StartBit and the EndBit. The value of the bit field is
637 If Address > 0x0FFFFFFF, then ASSERT().
638 If Address is not aligned on a 16-bit boundary, then ASSERT().
639 If the register specified by Address >= 0x100, then ASSERT().
640 If StartBit is greater than 15, then ASSERT().
641 If EndBit is greater than 15, then ASSERT().
642 If EndBit is less than StartBit, then ASSERT().
644 @param Address PCI configuration register to read.
645 @param StartBit The ordinal of the least significant bit in the bit field.
647 @param EndBit The ordinal of the most significant bit in the bit field.
650 @return The value of the bit field read from the PCI configuration register.
655 PciCf8BitFieldRead16 (
661 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
662 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
663 return IoBitFieldRead16 (
664 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 2),
671 Writes a bit field to a PCI configuration register.
673 Writes Value to the bit field of the PCI configuration register. The bit
674 field is specified by the StartBit and the EndBit. All other bits in the
675 destination PCI configuration register are preserved. The new value of the
676 16-bit register is returned.
678 If Address > 0x0FFFFFFF, then ASSERT().
679 If Address is not aligned on a 16-bit boundary, then ASSERT().
680 If the register specified by Address >= 0x100, then ASSERT().
681 If StartBit is greater than 15, then ASSERT().
682 If EndBit is greater than 15, then ASSERT().
683 If EndBit is less than StartBit, then ASSERT().
685 @param Address PCI configuration register to write.
686 @param StartBit The ordinal of the least significant bit in the bit field.
688 @param EndBit The ordinal of the most significant bit in the bit field.
690 @param Value New value of the bit field.
692 @return The value written back to the PCI configuration register.
697 PciCf8BitFieldWrite16 (
704 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
705 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
706 return IoBitFieldWrite16 (
707 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 2),
715 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
716 writes the result back to the bit field in the 16-bit port.
718 Reads the 16-bit PCI configuration register specified by Address, performs a
719 bitwise inclusive OR between the read result and the value specified by
720 OrData, and writes the result to the 16-bit PCI configuration register
721 specified by Address. The value written to the PCI configuration register is
722 returned. This function must guarantee that all PCI read and write operations
723 are serialized. Extra left bits in OrData are stripped.
725 If Address > 0x0FFFFFFF, then ASSERT().
726 If Address is not aligned on a 16-bit boundary, then ASSERT().
727 If the register specified by Address >= 0x100, then ASSERT().
728 If StartBit is greater than 15, then ASSERT().
729 If EndBit is greater than 15, then ASSERT().
730 If EndBit is less than StartBit, then ASSERT().
732 @param Address PCI configuration register to write.
733 @param StartBit The ordinal of the least significant bit in the bit field.
735 @param EndBit The ordinal of the most significant bit in the bit field.
737 @param OrData The value to OR with the PCI configuration register.
739 @return The value written back to the PCI configuration register.
751 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
752 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
753 return IoBitFieldOr16 (
754 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 2),
762 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
763 AND, and writes the result back to the bit field in the 16-bit register.
765 Reads the 16-bit PCI configuration register specified by Address, performs a
766 bitwise AND between the read result and the value specified by AndData, and
767 writes the result to the 16-bit PCI configuration register specified by
768 Address. The value written to the PCI configuration register is returned.
769 This function must guarantee that all PCI read and write operations are
770 serialized. Extra left bits in AndData are stripped.
772 If Address > 0x0FFFFFFF, then ASSERT().
773 If Address is not aligned on a 16-bit boundary, then ASSERT().
774 If the register specified by Address >= 0x100, then ASSERT().
775 If StartBit is greater than 15, then ASSERT().
776 If EndBit is greater than 15, then ASSERT().
777 If EndBit is less than StartBit, then ASSERT().
779 @param Address PCI configuration register to write.
780 @param StartBit The ordinal of the least significant bit in the bit field.
782 @param EndBit The ordinal of the most significant bit in the bit field.
784 @param AndData The value to AND with the PCI configuration register.
786 @return The value written back to the PCI configuration register.
791 PciCf8BitFieldAnd16 (
798 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
799 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
800 return IoBitFieldAnd16 (
801 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 2),
809 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
810 bitwise inclusive OR, and writes the result back to the bit field in the
813 Reads the 16-bit PCI configuration register specified by Address, performs a
814 bitwise AND followed by a bitwise inclusive OR between the read result and
815 the value specified by AndData, and writes the result to the 16-bit PCI
816 configuration register specified by Address. The value written to the PCI
817 configuration register is returned. This function must guarantee that all PCI
818 read and write operations are serialized. Extra left bits in both AndData and
821 If Address > 0x0FFFFFFF, then ASSERT().
822 If Address is not aligned on a 16-bit boundary, then ASSERT().
823 If the register specified by Address >= 0x100, then ASSERT().
824 If StartBit is greater than 15, then ASSERT().
825 If EndBit is greater than 15, then ASSERT().
826 If EndBit is less than StartBit, then ASSERT().
828 @param Address PCI configuration register to write.
829 @param StartBit The ordinal of the least significant bit in the bit field.
831 @param EndBit The ordinal of the most significant bit in the bit field.
833 @param AndData The value to AND with the PCI configuration register.
834 @param OrData The value to OR with the result of the AND operation.
836 @return The value written back to the PCI configuration register.
841 PciCf8BitFieldAndThenOr16(
849 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
850 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
851 return IoBitFieldAndThenOr16 (
852 PCI_CONFIGURATION_DATA_PORT
+ (UINT16
)(Address
& 2),
861 Reads a 32-bit PCI configuration register.
863 Reads and returns the 32-bit PCI configuration register specified by Address.
864 This function must guarantee that all PCI read and write operations are
867 If Address > 0x0FFFFFFF, then ASSERT().
868 If Address is not aligned on a 32-bit boundary, then ASSERT().
869 If the register specified by Address >= 0x100, then ASSERT().
871 @param Address Address that encodes the PCI Bus, Device, Function and
874 @return The read value from the PCI configuration register.
883 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
884 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
885 return IoRead32 (PCI_CONFIGURATION_DATA_PORT
);
889 Writes a 32-bit PCI configuration register.
891 Writes the 32-bit PCI configuration register specified by Address with the
892 value specified by Value. Value is returned. This function must guarantee
893 that all PCI read and write operations are serialized.
895 If Address > 0x0FFFFFFF, then ASSERT().
896 If Address is not aligned on a 32-bit boundary, then ASSERT().
897 If the register specified by Address >= 0x100, then ASSERT().
899 @param Address Address that encodes the PCI Bus, Device, Function and
901 @param Value The value to write.
903 @return The value written to the PCI configuration register.
913 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
914 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
916 PCI_CONFIGURATION_DATA_PORT
,
922 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
925 Reads the 32-bit PCI configuration register specified by Address, performs a
926 bitwise inclusive OR between the read result and the value specified by
927 OrData, and writes the result to the 32-bit PCI configuration register
928 specified by Address. The value written to the PCI configuration register is
929 returned. This function must guarantee that all PCI read and write operations
932 If Address > 0x0FFFFFFF, then ASSERT().
933 If Address is not aligned on a 32-bit boundary, then ASSERT().
934 If the register specified by Address >= 0x100, then ASSERT().
936 @param Address Address that encodes the PCI Bus, Device, Function and
938 @param OrData The value to OR with the PCI configuration register.
940 @return The value written back to the PCI configuration register.
950 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
951 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
953 PCI_CONFIGURATION_DATA_PORT
,
959 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
962 Reads the 32-bit PCI configuration register specified by Address, performs a
963 bitwise AND between the read result and the value specified by AndData, and
964 writes the result to the 32-bit PCI configuration register specified by
965 Address. The value written to the PCI configuration register is returned.
966 This function must guarantee that all PCI read and write operations are
969 If Address > 0x0FFFFFFF, then ASSERT().
970 If Address is not aligned on a 32-bit boundary, then ASSERT().
971 If the register specified by Address >= 0x100, then ASSERT().
973 @param Address Address that encodes the PCI Bus, Device, Function and
975 @param AndData The value to AND with the PCI configuration register.
977 @return The value written back to the PCI configuration register.
987 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
988 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
990 PCI_CONFIGURATION_DATA_PORT
,
996 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
997 value, followed a bitwise inclusive OR with another 32-bit value.
999 Reads the 32-bit PCI configuration register specified by Address, performs a
1000 bitwise AND between the read result and the value specified by AndData,
1001 performs a bitwise inclusive OR between the result of the AND operation and
1002 the value specified by OrData, and writes the result to the 32-bit PCI
1003 configuration register specified by Address. The value written to the PCI
1004 configuration register is returned. This function must guarantee that all PCI
1005 read and write operations are serialized.
1007 If Address > 0x0FFFFFFF, then ASSERT().
1008 If Address is not aligned on a 32-bit boundary, then ASSERT().
1009 If the register specified by Address >= 0x100, then ASSERT().
1011 @param Address Address that encodes the PCI Bus, Device, Function and
1013 @param AndData The value to AND with the PCI configuration register.
1014 @param OrData The value to OR with the result of the AND operation.
1016 @return The value written back to the PCI configuration register.
1027 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
1028 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
1029 return IoAndThenOr32 (
1030 PCI_CONFIGURATION_DATA_PORT
,
1037 Reads a bit field of a PCI configuration register.
1039 Reads the bit field in a 32-bit PCI configuration register. The bit field is
1040 specified by the StartBit and the EndBit. The value of the bit field is
1043 If Address > 0x0FFFFFFF, then ASSERT().
1044 If Address is not aligned on a 32-bit boundary, then ASSERT().
1045 If the register specified by Address >= 0x100, then ASSERT().
1046 If StartBit is greater than 31, then ASSERT().
1047 If EndBit is greater than 31, then ASSERT().
1048 If EndBit is less than StartBit, then ASSERT().
1050 @param Address PCI configuration register to read.
1051 @param StartBit The ordinal of the least significant bit in the bit field.
1053 @param EndBit The ordinal of the most significant bit in the bit field.
1056 @return The value of the bit field read from the PCI configuration register.
1061 PciCf8BitFieldRead32 (
1067 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
1068 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
1069 return IoBitFieldRead32 (
1070 PCI_CONFIGURATION_DATA_PORT
,
1077 Writes a bit field to a PCI configuration register.
1079 Writes Value to the bit field of the PCI configuration register. The bit
1080 field is specified by the StartBit and the EndBit. All other bits in the
1081 destination PCI configuration register are preserved. The new value of the
1082 32-bit register is returned.
1084 If Address > 0x0FFFFFFF, then ASSERT().
1085 If Address is not aligned on a 32-bit boundary, then ASSERT().
1086 If the register specified by Address >= 0x100, then ASSERT().
1087 If StartBit is greater than 31, then ASSERT().
1088 If EndBit is greater than 31, then ASSERT().
1089 If EndBit is less than StartBit, then ASSERT().
1091 @param Address PCI configuration register to write.
1092 @param StartBit The ordinal of the least significant bit in the bit field.
1094 @param EndBit The ordinal of the most significant bit in the bit field.
1096 @param Value New value of the bit field.
1098 @return The value written back to the PCI configuration register.
1103 PciCf8BitFieldWrite32 (
1110 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
1111 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
1112 return IoBitFieldWrite32 (
1113 PCI_CONFIGURATION_DATA_PORT
,
1121 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1122 writes the result back to the bit field in the 32-bit port.
1124 Reads the 32-bit PCI configuration register specified by Address, performs a
1125 bitwise inclusive OR between the read result and the value specified by
1126 OrData, and writes the result to the 32-bit PCI configuration register
1127 specified by Address. The value written to the PCI configuration register is
1128 returned. This function must guarantee that all PCI read and write operations
1129 are serialized. Extra left bits in OrData are stripped.
1131 If Address > 0x0FFFFFFF, then ASSERT().
1132 If Address is not aligned on a 32-bit boundary, then ASSERT().
1133 If the register specified by Address >= 0x100, then ASSERT().
1134 If StartBit is greater than 31, then ASSERT().
1135 If EndBit is greater than 31, then ASSERT().
1136 If EndBit is less than StartBit, then ASSERT().
1138 @param Address PCI configuration register to write.
1139 @param StartBit The ordinal of the least significant bit in the bit field.
1141 @param EndBit The ordinal of the most significant bit in the bit field.
1143 @param OrData The value to OR with the PCI configuration register.
1145 @return The value written back to the PCI configuration register.
1150 PciCf8BitFieldOr32 (
1157 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
1158 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
1159 return IoBitFieldOr32 (
1160 PCI_CONFIGURATION_DATA_PORT
,
1168 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1169 AND, and writes the result back to the bit field in the 32-bit register.
1171 Reads the 32-bit PCI configuration register specified by Address, performs a
1172 bitwise AND between the read result and the value specified by AndData, and
1173 writes the result to the 32-bit PCI configuration register specified by
1174 Address. The value written to the PCI configuration register is returned.
1175 This function must guarantee that all PCI read and write operations are
1176 serialized. Extra left bits in AndData are stripped.
1178 If Address > 0x0FFFFFFF, then ASSERT().
1179 If Address is not aligned on a 32-bit boundary, then ASSERT().
1180 If the register specified by Address >= 0x100, then ASSERT().
1181 If StartBit is greater than 31, then ASSERT().
1182 If EndBit is greater than 31, then ASSERT().
1183 If EndBit is less than StartBit, then ASSERT().
1185 @param Address PCI configuration register to write.
1186 @param StartBit The ordinal of the least significant bit in the bit field.
1188 @param EndBit The ordinal of the most significant bit in the bit field.
1190 @param AndData The value to AND with the PCI configuration register.
1192 @return The value written back to the PCI configuration register.
1197 PciCf8BitFieldAnd32 (
1204 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
1205 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
1206 return IoBitFieldAnd32 (
1207 PCI_CONFIGURATION_DATA_PORT
,
1215 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1216 bitwise inclusive OR, and writes the result back to the bit field in the
1219 Reads the 32-bit PCI configuration register specified by Address, performs a
1220 bitwise AND followed by a bitwise inclusive OR between the read result and
1221 the value specified by AndData, and writes the result to the 32-bit PCI
1222 configuration register specified by Address. The value written to the PCI
1223 configuration register is returned. This function must guarantee that all PCI
1224 read and write operations are serialized. Extra left bits in both AndData and
1225 OrData are stripped.
1227 If Address > 0x0FFFFFFF, then ASSERT().
1228 If Address is not aligned on a 32-bit boundary, then ASSERT().
1229 If the register specified by Address >= 0x100, then ASSERT().
1230 If StartBit is greater than 31, then ASSERT().
1231 If EndBit is greater than 31, then ASSERT().
1232 If EndBit is less than StartBit, then ASSERT().
1234 @param Address PCI configuration register to write.
1235 @param StartBit The ordinal of the least significant bit in the bit field.
1237 @param EndBit The ordinal of the most significant bit in the bit field.
1239 @param AndData The value to AND with the PCI configuration register.
1240 @param OrData The value to OR with the result of the AND operation.
1242 @return The value written back to the PCI configuration register.
1247 PciCf8BitFieldAndThenOr32(
1255 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
1256 IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT
, PCI_TO_CF8_ADDRESS (Address
));
1257 return IoBitFieldAndThenOr32 (
1258 PCI_CONFIGURATION_DATA_PORT
,
1267 Reads a range of PCI configuration registers into a caller supplied buffer.
1269 Reads the range of PCI configuration registers specified by StartAddress and
1270 Size into the buffer specified by Buffer. This function only allows the PCI
1271 configuration registers from a single PCI function to be read. Size is
1272 returned. When possible 32-bit PCI configuration read cycles are used to read
1273 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1274 and 16-bit PCI configuration read cycles may be used at the beginning and the
1277 If StartAddress > 0x0FFFFFFF, then ASSERT().
1278 If the register specified by StartAddress >= 0x100, then ASSERT().
1279 If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1280 If (StartAddress + Size - 1) > 0x0FFFFFFF, then ASSERT().
1281 If Buffer is NULL, then ASSERT().
1283 @param StartAddress Starting address that encodes the PCI Bus, Device,
1284 Function and Register.
1285 @param Size Size in bytes of the transfer.
1286 @param Buffer Pointer to a buffer receiving the data read.
1294 IN UINTN StartAddress
,
1301 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1302 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x100);
1303 ASSERT (Buffer
!= NULL
);
1305 EndAddress
= StartAddress
+ Size
;
1307 if (StartAddress
< EndAddress
&& (StartAddress
& 1)) {
1309 // Read a byte if StartAddress is byte aligned
1311 *(UINT8
*)Buffer
= PciCf8Read8 (StartAddress
);
1312 StartAddress
+= sizeof (UINT8
);
1313 Buffer
= (UINT8
*)Buffer
+ 1;
1316 if (StartAddress
< EndAddress
&& (StartAddress
& 2)) {
1318 // Read a word if StartAddress is word aligned
1320 *(UINT16
*)Buffer
= PciCf8Read16 (StartAddress
);
1321 StartAddress
+= sizeof (UINT16
);
1322 Buffer
= (UINT16
*)Buffer
+ 1;
1325 while (EndAddress
- StartAddress
>= 4) {
1327 // Read as many double words as possible
1329 *(UINT32
*)Buffer
= PciCf8Read32 (StartAddress
);
1330 StartAddress
+= sizeof (UINT32
);
1331 Buffer
= (UINT32
*)Buffer
+ 1;
1334 if ((EndAddress
& 2) != 0) {
1336 // Read the last remaining word if exist
1338 *(UINT16
*)Buffer
= PciCf8Read16 (StartAddress
);
1339 StartAddress
+= sizeof (UINT16
);
1340 Buffer
= (UINT16
*)Buffer
+ 1;
1343 if (EndAddress
& 1) {
1345 // Read the last remaining byte if exist
1347 *(UINT8
*)Buffer
= PciCf8Read8 (StartAddress
);
1354 Copies the data in a caller supplied buffer to a specified range of PCI
1355 configuration space.
1357 Writes the range of PCI configuration registers specified by StartAddress and
1358 Size from the buffer specified by Buffer. This function only allows the PCI
1359 configuration registers from a single PCI function to be written. Size is
1360 returned. When possible 32-bit PCI configuration write cycles are used to
1361 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1362 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1363 and the end of the range.
1365 If StartAddress > 0x0FFFFFFF, then ASSERT().
1366 If the register specified by StartAddress >= 0x100, then ASSERT().
1367 If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1368 If (StartAddress + Size - 1) > 0x0FFFFFFF, then ASSERT().
1369 If Buffer is NULL, then ASSERT().
1371 @param StartAddress Starting address that encodes the PCI Bus, Device,
1372 Function and Register.
1373 @param Size Size in bytes of the transfer.
1374 @param Buffer Pointer to a buffer containing the data to write.
1382 IN UINTN StartAddress
,
1389 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1390 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x100);
1391 ASSERT (Buffer
!= NULL
);
1393 EndAddress
= StartAddress
+ Size
;
1395 if ((StartAddress
< EndAddress
) && ((StartAddress
& 1)!= 0)) {
1397 // Write a byte if StartAddress is byte aligned
1399 PciCf8Write8 (StartAddress
, *(UINT8
*)Buffer
);
1400 StartAddress
+= sizeof (UINT8
);
1401 Buffer
= (UINT8
*)Buffer
+ 1;
1404 if (StartAddress
< EndAddress
&& (StartAddress
& 2)) {
1406 // Write a word if StartAddress is word aligned
1408 PciCf8Write16 (StartAddress
, *(UINT16
*)Buffer
);
1409 StartAddress
+= sizeof (UINT16
);
1410 Buffer
= (UINT16
*)Buffer
+ 1;
1413 while (EndAddress
- StartAddress
>= 4) {
1415 // Write as many double words as possible
1417 PciCf8Write32 (StartAddress
, *(UINT32
*)Buffer
);
1418 StartAddress
+= sizeof (UINT32
);
1419 Buffer
= (UINT32
*)Buffer
+ 1;
1422 if (EndAddress
& 2) {
1424 // Write the last remaining word if exist
1426 PciCf8Write16 (StartAddress
, *(UINT16
*)Buffer
);
1427 StartAddress
+= sizeof (UINT16
);
1428 Buffer
= (UINT16
*)Buffer
+ 1;
1431 if (EndAddress
& 1) {
1433 // Write the last remaining byte if exist
1435 PciCf8Write8 (StartAddress
, *(UINT8
*)Buffer
);