]>
git.proxmox.com Git - mirror_edk2.git/blob - MdePkg/Library/BasePciExpressLib/PciExpressLib.c
2 Functions in this library instance make use of MMIO functions in IoLib to
3 access memory mapped PCI configuration space.
5 All assertions for I/O operations are handled in MMIO functions in the IoLib
8 Copyright (c) 2006 - 2009, Intel Corporation<BR>
9 All rights reserved. This program and the accompanying materials
10 are licensed and made available under the terms and conditions of the BSD License
11 which accompanies this distribution. The full text of the license may be found at
12 http://opensource.org/licenses/bsd-license.php
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
22 #include <Library/BaseLib.h>
23 #include <Library/PciExpressLib.h>
24 #include <Library/IoLib.h>
25 #include <Library/DebugLib.h>
26 #include <Library/PcdLib.h>
30 Assert the validity of a PCI address. A valid PCI address should contain 1's
31 only in the low 28 bits.
33 @param A The address to validate.
36 #define ASSERT_INVALID_PCI_ADDRESS(A) \
37 ASSERT (((A) & ~0xfffffff) == 0)
40 Registers a PCI device so PCI configuration registers may be accessed after
41 SetVirtualAddressMap().
43 Registers the PCI device specified by Address so all the PCI configuration
44 registers associated with that PCI device may be accessed after SetVirtualAddressMap()
47 If Address > 0x0FFFFFFF, then ASSERT().
49 @param Address Address that encodes the PCI Bus, Device, Function and
52 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
53 @retval RETURN_UNSUPPORTED An attempt was made to call this function
54 after ExitBootServices().
55 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
56 at runtime could not be mapped.
57 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
58 complete the registration.
63 PciExpressRegisterForRuntimeAccess (
67 ASSERT_INVALID_PCI_ADDRESS (Address
);
68 return RETURN_UNSUPPORTED
;
72 Gets the base address of PCI Express.
74 This internal functions retrieves PCI Express Base Address via a PCD entry
75 PcdPciExpressBaseAddress.
77 @return The base address of PCI Express.
81 GetPciExpressBaseAddress (
85 return (VOID
*)(UINTN
) PcdGet64 (PcdPciExpressBaseAddress
);
89 Reads an 8-bit PCI configuration register.
91 Reads and returns the 8-bit PCI configuration register specified by Address.
92 This function must guarantee that all PCI read and write operations are
95 If Address > 0x0FFFFFFF, then ASSERT().
97 @param Address Address that encodes the PCI Bus, Device, Function and
100 @return The read value from the PCI configuration register.
109 ASSERT_INVALID_PCI_ADDRESS (Address
);
110 return MmioRead8 ((UINTN
) GetPciExpressBaseAddress () + Address
);
114 Writes an 8-bit PCI configuration register.
116 Writes the 8-bit PCI configuration register specified by Address with the
117 value specified by Value. Value is returned. This function must guarantee
118 that all PCI read and write operations are serialized.
120 If Address > 0x0FFFFFFF, then ASSERT().
122 @param Address Address that encodes the PCI Bus, Device, Function and
124 @param Value The value to write.
126 @return The value written to the PCI configuration register.
136 ASSERT_INVALID_PCI_ADDRESS (Address
);
137 return MmioWrite8 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
141 Performs a bitwise OR of an 8-bit PCI configuration register with
144 Reads the 8-bit PCI configuration register specified by Address, performs a
145 bitwise OR between the read result and the value specified by
146 OrData, and writes the result to the 8-bit PCI configuration register
147 specified by Address. The value written to the PCI configuration register is
148 returned. This function must guarantee that all PCI read and write operations
151 If Address > 0x0FFFFFFF, then ASSERT().
153 @param Address Address that encodes the PCI Bus, Device, Function and
155 @param OrData The value to OR with the PCI configuration register.
157 @return The value written back to the PCI configuration register.
167 ASSERT_INVALID_PCI_ADDRESS (Address
);
168 return MmioOr8 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
172 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
175 Reads the 8-bit PCI configuration register specified by Address, performs a
176 bitwise AND between the read result and the value specified by AndData, and
177 writes the result to the 8-bit PCI configuration register specified by
178 Address. The value written to the PCI configuration register is returned.
179 This function must guarantee that all PCI read and write operations are
182 If Address > 0x0FFFFFFF, then ASSERT().
184 @param Address Address that encodes the PCI Bus, Device, Function and
186 @param AndData The value to AND with the PCI configuration register.
188 @return The value written back to the PCI configuration register.
198 ASSERT_INVALID_PCI_ADDRESS (Address
);
199 return MmioAnd8 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
203 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
204 value, followed a bitwise OR with another 8-bit value.
206 Reads the 8-bit PCI configuration register specified by Address, performs a
207 bitwise AND between the read result and the value specified by AndData,
208 performs a bitwise OR between the result of the AND operation and
209 the value specified by OrData, and writes the result to the 8-bit PCI
210 configuration register specified by Address. The value written to the PCI
211 configuration register is returned. This function must guarantee that all PCI
212 read and write operations are serialized.
214 If Address > 0x0FFFFFFF, then ASSERT().
216 @param Address Address that encodes the PCI Bus, Device, Function and
218 @param AndData The value to AND with the PCI configuration register.
219 @param OrData The value to OR with the result of the AND operation.
221 @return The value written back to the PCI configuration register.
226 PciExpressAndThenOr8 (
232 ASSERT_INVALID_PCI_ADDRESS (Address
);
233 return MmioAndThenOr8 (
234 (UINTN
) GetPciExpressBaseAddress () + Address
,
241 Reads a bit field of a PCI configuration register.
243 Reads the bit field in an 8-bit PCI configuration register. The bit field is
244 specified by the StartBit and the EndBit. The value of the bit field is
247 If Address > 0x0FFFFFFF, then ASSERT().
248 If StartBit is greater than 7, then ASSERT().
249 If EndBit is greater than 7, then ASSERT().
250 If EndBit is less than StartBit, then ASSERT().
252 @param Address PCI configuration register to read.
253 @param StartBit The ordinal of the least significant bit in the bit field.
255 @param EndBit The ordinal of the most significant bit in the bit field.
258 @return The value of the bit field read from the PCI configuration register.
263 PciExpressBitFieldRead8 (
269 ASSERT_INVALID_PCI_ADDRESS (Address
);
270 return MmioBitFieldRead8 (
271 (UINTN
) GetPciExpressBaseAddress () + Address
,
278 Writes a bit field to a PCI configuration register.
280 Writes Value to the bit field of the PCI configuration register. The bit
281 field is specified by the StartBit and the EndBit. All other bits in the
282 destination PCI configuration register are preserved. The new value of the
283 8-bit register is returned.
285 If Address > 0x0FFFFFFF, then ASSERT().
286 If StartBit is greater than 7, then ASSERT().
287 If EndBit is greater than 7, then ASSERT().
288 If EndBit is less than StartBit, then ASSERT().
290 @param Address PCI configuration register to write.
291 @param StartBit The ordinal of the least significant bit in the bit field.
293 @param EndBit The ordinal of the most significant bit in the bit field.
295 @param Value New value of the bit field.
297 @return The value written back to the PCI configuration register.
302 PciExpressBitFieldWrite8 (
309 ASSERT_INVALID_PCI_ADDRESS (Address
);
310 return MmioBitFieldWrite8 (
311 (UINTN
) GetPciExpressBaseAddress () + Address
,
319 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
320 writes the result back to the bit field in the 8-bit port.
322 Reads the 8-bit PCI configuration register specified by Address, performs a
323 bitwise OR between the read result and the value specified by
324 OrData, and writes the result to the 8-bit PCI configuration register
325 specified by Address. The value written to the PCI configuration register is
326 returned. This function must guarantee that all PCI read and write operations
327 are serialized. Extra left bits in OrData are stripped.
329 If Address > 0x0FFFFFFF, then ASSERT().
330 If StartBit is greater than 7, then ASSERT().
331 If EndBit is greater than 7, then ASSERT().
332 If EndBit is less than StartBit, then ASSERT().
334 @param Address PCI configuration register to write.
335 @param StartBit The ordinal of the least significant bit in the bit field.
337 @param EndBit The ordinal of the most significant bit in the bit field.
339 @param OrData The value to OR with the PCI configuration register.
341 @return The value written back to the PCI configuration register.
346 PciExpressBitFieldOr8 (
353 ASSERT_INVALID_PCI_ADDRESS (Address
);
354 return MmioBitFieldOr8 (
355 (UINTN
) GetPciExpressBaseAddress () + Address
,
363 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
364 AND, and writes the result back to the bit field in the 8-bit register.
366 Reads the 8-bit PCI configuration register specified by Address, performs a
367 bitwise AND between the read result and the value specified by AndData, and
368 writes the result to the 8-bit PCI configuration register specified by
369 Address. The value written to the PCI configuration register is returned.
370 This function must guarantee that all PCI read and write operations are
371 serialized. Extra left bits in AndData are stripped.
373 If Address > 0x0FFFFFFF, then ASSERT().
374 If StartBit is greater than 7, then ASSERT().
375 If EndBit is greater than 7, then ASSERT().
376 If EndBit is less than StartBit, then ASSERT().
378 @param Address PCI configuration register to write.
379 @param StartBit The ordinal of the least significant bit in the bit field.
381 @param EndBit The ordinal of the most significant bit in the bit field.
383 @param AndData The value to AND with the PCI configuration register.
385 @return The value written back to the PCI configuration register.
390 PciExpressBitFieldAnd8 (
397 ASSERT_INVALID_PCI_ADDRESS (Address
);
398 return MmioBitFieldAnd8 (
399 (UINTN
) GetPciExpressBaseAddress () + Address
,
407 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
408 bitwise OR, and writes the result back to the bit field in the
411 Reads the 8-bit PCI configuration register specified by Address, performs a
412 bitwise AND followed by a bitwise OR between the read result and
413 the value specified by AndData, and writes the result to the 8-bit PCI
414 configuration register specified by Address. The value written to the PCI
415 configuration register is returned. This function must guarantee that all PCI
416 read and write operations are serialized. Extra left bits in both AndData and
419 If Address > 0x0FFFFFFF, then ASSERT().
420 If StartBit is greater than 7, then ASSERT().
421 If EndBit is greater than 7, then ASSERT().
422 If EndBit is less than StartBit, then ASSERT().
424 @param Address PCI configuration register to write.
425 @param StartBit The ordinal of the least significant bit in the bit field.
427 @param EndBit The ordinal of the most significant bit in the bit field.
429 @param AndData The value to AND with the PCI configuration register.
430 @param OrData The value to OR with the result of the AND operation.
432 @return The value written back to the PCI configuration register.
437 PciExpressBitFieldAndThenOr8 (
445 ASSERT_INVALID_PCI_ADDRESS (Address
);
446 return MmioBitFieldAndThenOr8 (
447 (UINTN
) GetPciExpressBaseAddress () + Address
,
456 Reads a 16-bit PCI configuration register.
458 Reads and returns the 16-bit PCI configuration register specified by Address.
459 This function must guarantee that all PCI read and write operations are
462 If Address > 0x0FFFFFFF, then ASSERT().
463 If Address is not aligned on a 16-bit boundary, then ASSERT().
465 @param Address Address that encodes the PCI Bus, Device, Function and
468 @return The read value from the PCI configuration register.
477 ASSERT_INVALID_PCI_ADDRESS (Address
);
478 return MmioRead16 ((UINTN
) GetPciExpressBaseAddress () + Address
);
482 Writes a 16-bit PCI configuration register.
484 Writes the 16-bit PCI configuration register specified by Address with the
485 value specified by Value. Value is returned. This function must guarantee
486 that all PCI read and write operations are serialized.
488 If Address > 0x0FFFFFFF, then ASSERT().
489 If Address is not aligned on a 16-bit boundary, then ASSERT().
491 @param Address Address that encodes the PCI Bus, Device, Function and
493 @param Value The value to write.
495 @return The value written to the PCI configuration register.
505 ASSERT_INVALID_PCI_ADDRESS (Address
);
506 return MmioWrite16 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
510 Performs a bitwise OR of a 16-bit PCI configuration register with
513 Reads the 16-bit PCI configuration register specified by Address, performs a
514 bitwise OR between the read result and the value specified by
515 OrData, and writes the result to the 16-bit PCI configuration register
516 specified by Address. The value written to the PCI configuration register is
517 returned. This function must guarantee that all PCI read and write operations
520 If Address > 0x0FFFFFFF, then ASSERT().
521 If Address is not aligned on a 16-bit boundary, then ASSERT().
523 @param Address Address that encodes the PCI Bus, Device, Function and
525 @param OrData The value to OR with the PCI configuration register.
527 @return The value written back to the PCI configuration register.
537 ASSERT_INVALID_PCI_ADDRESS (Address
);
538 return MmioOr16 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
542 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
545 Reads the 16-bit PCI configuration register specified by Address, performs a
546 bitwise AND between the read result and the value specified by AndData, and
547 writes the result to the 16-bit PCI configuration register specified by
548 Address. The value written to the PCI configuration register is returned.
549 This function must guarantee that all PCI read and write operations are
552 If Address > 0x0FFFFFFF, then ASSERT().
553 If Address is not aligned on a 16-bit boundary, then ASSERT().
555 @param Address Address that encodes the PCI Bus, Device, Function and
557 @param AndData The value to AND with the PCI configuration register.
559 @return The value written back to the PCI configuration register.
569 ASSERT_INVALID_PCI_ADDRESS (Address
);
570 return MmioAnd16 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
574 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
575 value, followed a bitwise OR with another 16-bit value.
577 Reads the 16-bit PCI configuration register specified by Address, performs a
578 bitwise AND between the read result and the value specified by AndData,
579 performs a bitwise OR between the result of the AND operation and
580 the value specified by OrData, and writes the result to the 16-bit PCI
581 configuration register specified by Address. The value written to the PCI
582 configuration register is returned. This function must guarantee that all PCI
583 read and write operations are serialized.
585 If Address > 0x0FFFFFFF, then ASSERT().
586 If Address is not aligned on a 16-bit boundary, then ASSERT().
588 @param Address Address that encodes the PCI Bus, Device, Function and
590 @param AndData The value to AND with the PCI configuration register.
591 @param OrData The value to OR with the result of the AND operation.
593 @return The value written back to the PCI configuration register.
598 PciExpressAndThenOr16 (
604 ASSERT_INVALID_PCI_ADDRESS (Address
);
605 return MmioAndThenOr16 (
606 (UINTN
) GetPciExpressBaseAddress () + Address
,
613 Reads a bit field of a PCI configuration register.
615 Reads the bit field in a 16-bit PCI configuration register. The bit field is
616 specified by the StartBit and the EndBit. The value of the bit field is
619 If Address > 0x0FFFFFFF, then ASSERT().
620 If Address is not aligned on a 16-bit boundary, then ASSERT().
621 If StartBit is greater than 15, then ASSERT().
622 If EndBit is greater than 15, then ASSERT().
623 If EndBit is less than StartBit, then ASSERT().
625 @param Address PCI configuration register to read.
626 @param StartBit The ordinal of the least significant bit in the bit field.
628 @param EndBit The ordinal of the most significant bit in the bit field.
631 @return The value of the bit field read from the PCI configuration register.
636 PciExpressBitFieldRead16 (
642 ASSERT_INVALID_PCI_ADDRESS (Address
);
643 return MmioBitFieldRead16 (
644 (UINTN
) GetPciExpressBaseAddress () + Address
,
651 Writes a bit field to a PCI configuration register.
653 Writes Value to the bit field of the PCI configuration register. The bit
654 field is specified by the StartBit and the EndBit. All other bits in the
655 destination PCI configuration register are preserved. The new value of the
656 16-bit register is returned.
658 If Address > 0x0FFFFFFF, then ASSERT().
659 If Address is not aligned on a 16-bit boundary, then ASSERT().
660 If StartBit is greater than 15, then ASSERT().
661 If EndBit is greater than 15, then ASSERT().
662 If EndBit is less than StartBit, then ASSERT().
664 @param Address PCI configuration register to write.
665 @param StartBit The ordinal of the least significant bit in the bit field.
667 @param EndBit The ordinal of the most significant bit in the bit field.
669 @param Value New value of the bit field.
671 @return The value written back to the PCI configuration register.
676 PciExpressBitFieldWrite16 (
683 ASSERT_INVALID_PCI_ADDRESS (Address
);
684 return MmioBitFieldWrite16 (
685 (UINTN
) GetPciExpressBaseAddress () + Address
,
693 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
694 writes the result back to the bit field in the 16-bit port.
696 Reads the 16-bit PCI configuration register specified by Address, performs a
697 bitwise OR between the read result and the value specified by
698 OrData, and writes the result to the 16-bit PCI configuration register
699 specified by Address. The value written to the PCI configuration register is
700 returned. This function must guarantee that all PCI read and write operations
701 are serialized. Extra left bits in OrData are stripped.
703 If Address > 0x0FFFFFFF, then ASSERT().
704 If Address is not aligned on a 16-bit boundary, then ASSERT().
705 If StartBit is greater than 15, then ASSERT().
706 If EndBit is greater than 15, then ASSERT().
707 If EndBit is less than StartBit, then ASSERT().
709 @param Address PCI configuration register to write.
710 @param StartBit The ordinal of the least significant bit in the bit field.
712 @param EndBit The ordinal of the most significant bit in the bit field.
714 @param OrData The value to OR with the PCI configuration register.
716 @return The value written back to the PCI configuration register.
721 PciExpressBitFieldOr16 (
728 ASSERT_INVALID_PCI_ADDRESS (Address
);
729 return MmioBitFieldOr16 (
730 (UINTN
) GetPciExpressBaseAddress () + Address
,
738 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
739 AND, and writes the result back to the bit field in the 16-bit register.
741 Reads the 16-bit PCI configuration register specified by Address, performs a
742 bitwise AND between the read result and the value specified by AndData, and
743 writes the result to the 16-bit PCI configuration register specified by
744 Address. The value written to the PCI configuration register is returned.
745 This function must guarantee that all PCI read and write operations are
746 serialized. Extra left bits in AndData are stripped.
748 If Address > 0x0FFFFFFF, then ASSERT().
749 If Address is not aligned on a 16-bit boundary, then ASSERT().
750 If StartBit is greater than 15, then ASSERT().
751 If EndBit is greater than 15, then ASSERT().
752 If EndBit is less than StartBit, then ASSERT().
754 @param Address PCI configuration register to write.
755 @param StartBit The ordinal of the least significant bit in the bit field.
757 @param EndBit The ordinal of the most significant bit in the bit field.
759 @param AndData The value to AND with the PCI configuration register.
761 @return The value written back to the PCI configuration register.
766 PciExpressBitFieldAnd16 (
773 ASSERT_INVALID_PCI_ADDRESS (Address
);
774 return MmioBitFieldAnd16 (
775 (UINTN
) GetPciExpressBaseAddress () + Address
,
783 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
784 bitwise OR, and writes the result back to the bit field in the
787 Reads the 16-bit PCI configuration register specified by Address, performs a
788 bitwise AND followed by a bitwise OR between the read result and
789 the value specified by AndData, and writes the result to the 16-bit PCI
790 configuration register specified by Address. The value written to the PCI
791 configuration register is returned. This function must guarantee that all PCI
792 read and write operations are serialized. Extra left bits in both AndData and
795 If Address > 0x0FFFFFFF, then ASSERT().
796 If Address is not aligned on a 16-bit boundary, then ASSERT().
797 If StartBit is greater than 15, then ASSERT().
798 If EndBit is greater than 15, then ASSERT().
799 If EndBit is less than StartBit, then ASSERT().
801 @param Address PCI configuration register to write.
802 @param StartBit The ordinal of the least significant bit in the bit field.
804 @param EndBit The ordinal of the most significant bit in the bit field.
806 @param AndData The value to AND with the PCI configuration register.
807 @param OrData The value to OR with the result of the AND operation.
809 @return The value written back to the PCI configuration register.
814 PciExpressBitFieldAndThenOr16 (
822 ASSERT_INVALID_PCI_ADDRESS (Address
);
823 return MmioBitFieldAndThenOr16 (
824 (UINTN
) GetPciExpressBaseAddress () + Address
,
833 Reads a 32-bit PCI configuration register.
835 Reads and returns the 32-bit PCI configuration register specified by Address.
836 This function must guarantee that all PCI read and write operations are
839 If Address > 0x0FFFFFFF, then ASSERT().
840 If Address is not aligned on a 32-bit boundary, then ASSERT().
842 @param Address Address that encodes the PCI Bus, Device, Function and
845 @return The read value from the PCI configuration register.
854 ASSERT_INVALID_PCI_ADDRESS (Address
);
855 return MmioRead32 ((UINTN
) GetPciExpressBaseAddress () + Address
);
859 Writes a 32-bit PCI configuration register.
861 Writes the 32-bit PCI configuration register specified by Address with the
862 value specified by Value. Value is returned. This function must guarantee
863 that all PCI read and write operations are serialized.
865 If Address > 0x0FFFFFFF, then ASSERT().
866 If Address is not aligned on a 32-bit boundary, then ASSERT().
868 @param Address Address that encodes the PCI Bus, Device, Function and
870 @param Value The value to write.
872 @return The value written to the PCI configuration register.
882 ASSERT_INVALID_PCI_ADDRESS (Address
);
883 return MmioWrite32 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
887 Performs a bitwise OR of a 32-bit PCI configuration register with
890 Reads the 32-bit PCI configuration register specified by Address, performs a
891 bitwise OR between the read result and the value specified by
892 OrData, and writes the result to the 32-bit PCI configuration register
893 specified by Address. The value written to the PCI configuration register is
894 returned. This function must guarantee that all PCI read and write operations
897 If Address > 0x0FFFFFFF, then ASSERT().
898 If Address is not aligned on a 32-bit boundary, then ASSERT().
900 @param Address Address that encodes the PCI Bus, Device, Function and
902 @param OrData The value to OR with the PCI configuration register.
904 @return The value written back to the PCI configuration register.
914 ASSERT_INVALID_PCI_ADDRESS (Address
);
915 return MmioOr32 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
919 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
922 Reads the 32-bit PCI configuration register specified by Address, performs a
923 bitwise AND between the read result and the value specified by AndData, and
924 writes the result to the 32-bit PCI configuration register specified by
925 Address. The value written to the PCI configuration register is returned.
926 This function must guarantee that all PCI read and write operations are
929 If Address > 0x0FFFFFFF, then ASSERT().
930 If Address is not aligned on a 32-bit boundary, then ASSERT().
932 @param Address Address that encodes the PCI Bus, Device, Function and
934 @param AndData The value to AND with the PCI configuration register.
936 @return The value written back to the PCI configuration register.
946 ASSERT_INVALID_PCI_ADDRESS (Address
);
947 return MmioAnd32 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
951 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
952 value, followed a bitwise OR with another 32-bit value.
954 Reads the 32-bit PCI configuration register specified by Address, performs a
955 bitwise AND between the read result and the value specified by AndData,
956 performs a bitwise OR between the result of the AND operation and
957 the value specified by OrData, and writes the result to the 32-bit PCI
958 configuration register specified by Address. The value written to the PCI
959 configuration register is returned. This function must guarantee that all PCI
960 read and write operations are serialized.
962 If Address > 0x0FFFFFFF, then ASSERT().
963 If Address is not aligned on a 32-bit boundary, then ASSERT().
965 @param Address Address that encodes the PCI Bus, Device, Function and
967 @param AndData The value to AND with the PCI configuration register.
968 @param OrData The value to OR with the result of the AND operation.
970 @return The value written back to the PCI configuration register.
975 PciExpressAndThenOr32 (
981 ASSERT_INVALID_PCI_ADDRESS (Address
);
982 return MmioAndThenOr32 (
983 (UINTN
) GetPciExpressBaseAddress () + Address
,
990 Reads a bit field of a PCI configuration register.
992 Reads the bit field in a 32-bit PCI configuration register. The bit field is
993 specified by the StartBit and the EndBit. The value of the bit field is
996 If Address > 0x0FFFFFFF, then ASSERT().
997 If Address is not aligned on a 32-bit boundary, then ASSERT().
998 If StartBit is greater than 31, then ASSERT().
999 If EndBit is greater than 31, then ASSERT().
1000 If EndBit is less than StartBit, then ASSERT().
1002 @param Address PCI configuration register to read.
1003 @param StartBit The ordinal of the least significant bit in the bit field.
1005 @param EndBit The ordinal of the most significant bit in the bit field.
1008 @return The value of the bit field read from the PCI configuration register.
1013 PciExpressBitFieldRead32 (
1019 ASSERT_INVALID_PCI_ADDRESS (Address
);
1020 return MmioBitFieldRead32 (
1021 (UINTN
) GetPciExpressBaseAddress () + Address
,
1028 Writes a bit field to a PCI configuration register.
1030 Writes Value to the bit field of the PCI configuration register. The bit
1031 field is specified by the StartBit and the EndBit. All other bits in the
1032 destination PCI configuration register are preserved. The new value of the
1033 32-bit register is returned.
1035 If Address > 0x0FFFFFFF, then ASSERT().
1036 If Address is not aligned on a 32-bit boundary, then ASSERT().
1037 If StartBit is greater than 31, then ASSERT().
1038 If EndBit is greater than 31, then ASSERT().
1039 If EndBit is less than StartBit, then ASSERT().
1041 @param Address PCI configuration register to write.
1042 @param StartBit The ordinal of the least significant bit in the bit field.
1044 @param EndBit The ordinal of the most significant bit in the bit field.
1046 @param Value New value of the bit field.
1048 @return The value written back to the PCI configuration register.
1053 PciExpressBitFieldWrite32 (
1060 ASSERT_INVALID_PCI_ADDRESS (Address
);
1061 return MmioBitFieldWrite32 (
1062 (UINTN
) GetPciExpressBaseAddress () + Address
,
1070 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1071 writes the result back to the bit field in the 32-bit port.
1073 Reads the 32-bit PCI configuration register specified by Address, performs a
1074 bitwise OR between the read result and the value specified by
1075 OrData, and writes the result to the 32-bit PCI configuration register
1076 specified by Address. The value written to the PCI configuration register is
1077 returned. This function must guarantee that all PCI read and write operations
1078 are serialized. Extra left bits in OrData are stripped.
1080 If Address > 0x0FFFFFFF, then ASSERT().
1081 If Address is not aligned on a 32-bit boundary, then ASSERT().
1082 If StartBit is greater than 31, then ASSERT().
1083 If EndBit is greater than 31, then ASSERT().
1084 If EndBit is less than StartBit, then ASSERT().
1086 @param Address PCI configuration register to write.
1087 @param StartBit The ordinal of the least significant bit in the bit field.
1089 @param EndBit The ordinal of the most significant bit in the bit field.
1091 @param OrData The value to OR with the PCI configuration register.
1093 @return The value written back to the PCI configuration register.
1098 PciExpressBitFieldOr32 (
1105 ASSERT_INVALID_PCI_ADDRESS (Address
);
1106 return MmioBitFieldOr32 (
1107 (UINTN
) GetPciExpressBaseAddress () + Address
,
1115 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1116 AND, and writes the result back to the bit field in the 32-bit register.
1118 Reads the 32-bit PCI configuration register specified by Address, performs a
1119 bitwise AND between the read result and the value specified by AndData, and
1120 writes the result to the 32-bit PCI configuration register specified by
1121 Address. The value written to the PCI configuration register is returned.
1122 This function must guarantee that all PCI read and write operations are
1123 serialized. Extra left bits in AndData are stripped.
1125 If Address > 0x0FFFFFFF, then ASSERT().
1126 If Address is not aligned on a 32-bit boundary, then ASSERT().
1127 If StartBit is greater than 31, then ASSERT().
1128 If EndBit is greater than 31, then ASSERT().
1129 If EndBit is less than StartBit, then ASSERT().
1131 @param Address PCI configuration register to write.
1132 @param StartBit The ordinal of the least significant bit in the bit field.
1134 @param EndBit The ordinal of the most significant bit in the bit field.
1136 @param AndData The value to AND with the PCI configuration register.
1138 @return The value written back to the PCI configuration register.
1143 PciExpressBitFieldAnd32 (
1150 ASSERT_INVALID_PCI_ADDRESS (Address
);
1151 return MmioBitFieldAnd32 (
1152 (UINTN
) GetPciExpressBaseAddress () + Address
,
1160 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1161 bitwise OR, and writes the result back to the bit field in the
1164 Reads the 32-bit PCI configuration register specified by Address, performs a
1165 bitwise AND followed by a bitwise OR between the read result and
1166 the value specified by AndData, and writes the result to the 32-bit PCI
1167 configuration register specified by Address. The value written to the PCI
1168 configuration register is returned. This function must guarantee that all PCI
1169 read and write operations are serialized. Extra left bits in both AndData and
1170 OrData are stripped.
1172 If Address > 0x0FFFFFFF, then ASSERT().
1173 If Address is not aligned on a 32-bit boundary, then ASSERT().
1174 If StartBit is greater than 31, then ASSERT().
1175 If EndBit is greater than 31, then ASSERT().
1176 If EndBit is less than StartBit, then ASSERT().
1178 @param Address PCI configuration register to write.
1179 @param StartBit The ordinal of the least significant bit in the bit field.
1181 @param EndBit The ordinal of the most significant bit in the bit field.
1183 @param AndData The value to AND with the PCI configuration register.
1184 @param OrData The value to OR with the result of the AND operation.
1186 @return The value written back to the PCI configuration register.
1191 PciExpressBitFieldAndThenOr32 (
1199 ASSERT_INVALID_PCI_ADDRESS (Address
);
1200 return MmioBitFieldAndThenOr32 (
1201 (UINTN
) GetPciExpressBaseAddress () + Address
,
1210 Reads a range of PCI configuration registers into a caller supplied buffer.
1212 Reads the range of PCI configuration registers specified by StartAddress and
1213 Size into the buffer specified by Buffer. This function only allows the PCI
1214 configuration registers from a single PCI function to be read. Size is
1215 returned. When possible 32-bit PCI configuration read cycles are used to read
1216 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1217 and 16-bit PCI configuration read cycles may be used at the beginning and the
1220 If StartAddress > 0x0FFFFFFF, then ASSERT().
1221 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1222 If Size > 0 and Buffer is NULL, then ASSERT().
1224 @param StartAddress Starting address that encodes the PCI Bus, Device,
1225 Function and Register.
1226 @param Size Size in bytes of the transfer.
1227 @param Buffer Pointer to a buffer receiving the data read.
1229 @return Size read data from StartAddress.
1234 PciExpressReadBuffer (
1235 IN UINTN StartAddress
,
1242 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1243 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1249 ASSERT (Buffer
!= NULL
);
1252 // Save Size for return
1256 if ((StartAddress
& 1) != 0) {
1258 // Read a byte if StartAddress is byte aligned
1260 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1261 StartAddress
+= sizeof (UINT8
);
1262 Size
-= sizeof (UINT8
);
1263 Buffer
= (UINT8
*)Buffer
+ 1;
1266 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1268 // Read a word if StartAddress is word aligned
1270 WriteUnaligned16 ((UINT16
*) Buffer
, (UINT16
) PciExpressRead16 (StartAddress
));
1272 StartAddress
+= sizeof (UINT16
);
1273 Size
-= sizeof (UINT16
);
1274 Buffer
= (UINT16
*)Buffer
+ 1;
1277 while (Size
>= sizeof (UINT32
)) {
1279 // Read as many double words as possible
1281 WriteUnaligned32 ((UINT32
*) Buffer
, (UINT32
) PciExpressRead32 (StartAddress
));
1283 StartAddress
+= sizeof (UINT32
);
1284 Size
-= sizeof (UINT32
);
1285 Buffer
= (UINT32
*)Buffer
+ 1;
1288 if (Size
>= sizeof (UINT16
)) {
1290 // Read the last remaining word if exist
1292 WriteUnaligned16 ((UINT16
*) Buffer
, (UINT16
) PciExpressRead16 (StartAddress
));
1293 StartAddress
+= sizeof (UINT16
);
1294 Size
-= sizeof (UINT16
);
1295 Buffer
= (UINT16
*)Buffer
+ 1;
1298 if (Size
>= sizeof (UINT8
)) {
1300 // Read the last remaining byte if exist
1302 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1309 Copies the data in a caller supplied buffer to a specified range of PCI
1310 configuration space.
1312 Writes the range of PCI configuration registers specified by StartAddress and
1313 Size from the buffer specified by Buffer. This function only allows the PCI
1314 configuration registers from a single PCI function to be written. Size is
1315 returned. When possible 32-bit PCI configuration write cycles are used to
1316 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1317 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1318 and the end of the range.
1320 If StartAddress > 0x0FFFFFFF, then ASSERT().
1321 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1322 If Size > 0 and Buffer is NULL, then ASSERT().
1324 @param StartAddress Starting address that encodes the PCI Bus, Device,
1325 Function and Register.
1326 @param Size Size in bytes of the transfer.
1327 @param Buffer Pointer to a buffer containing the data to write.
1329 @return Size written to StartAddress.
1334 PciExpressWriteBuffer (
1335 IN UINTN StartAddress
,
1342 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1343 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1349 ASSERT (Buffer
!= NULL
);
1352 // Save Size for return
1356 if ((StartAddress
& 1) != 0) {
1358 // Write a byte if StartAddress is byte aligned
1360 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1361 StartAddress
+= sizeof (UINT8
);
1362 Size
-= sizeof (UINT8
);
1363 Buffer
= (UINT8
*)Buffer
+ 1;
1366 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1368 // Write a word if StartAddress is word aligned
1370 PciExpressWrite16 (StartAddress
, ReadUnaligned16 ((UINT16
*)Buffer
));
1371 StartAddress
+= sizeof (UINT16
);
1372 Size
-= sizeof (UINT16
);
1373 Buffer
= (UINT16
*)Buffer
+ 1;
1376 while (Size
>= sizeof (UINT32
)) {
1378 // Write as many double words as possible
1380 PciExpressWrite32 (StartAddress
, ReadUnaligned32 ((UINT32
*)Buffer
));
1381 StartAddress
+= sizeof (UINT32
);
1382 Size
-= sizeof (UINT32
);
1383 Buffer
= (UINT32
*)Buffer
+ 1;
1386 if (Size
>= sizeof (UINT16
)) {
1388 // Write the last remaining word if exist
1390 PciExpressWrite16 (StartAddress
, ReadUnaligned16 ((UINT16
*)Buffer
));
1391 StartAddress
+= sizeof (UINT16
);
1392 Size
-= sizeof (UINT16
);
1393 Buffer
= (UINT16
*)Buffer
+ 1;
1396 if (Size
>= sizeof (UINT8
)) {
1398 // Write the last remaining byte if exist
1400 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);