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git.proxmox.com Git - mirror_edk2.git/blob - MdePkg/Library/BasePciExpressLib/PciExpressLib.c
61be0098a68ba4706001c1172998cb15100a0bf1
2 Functions in this library instance make use of MMIO functions in IoLib to
3 access memory mapped PCI configuration space.
5 All assertions for I/O operations are handled in MMIO functions in the IoLib
8 Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
9 This program and the accompanying materials
10 are licensed and made available under the terms and conditions of the BSD License
11 which accompanies this distribution. The full text of the license may be found at
12 http://opensource.org/licenses/bsd-license.php.
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
22 #include <Library/BaseLib.h>
23 #include <Library/PciExpressLib.h>
24 #include <Library/IoLib.h>
25 #include <Library/DebugLib.h>
26 #include <Library/PcdLib.h>
30 Assert the validity of a PCI address. A valid PCI address should contain 1's
31 only in the low 28 bits.
33 @param A The address to validate.
36 #define ASSERT_INVALID_PCI_ADDRESS(A) \
37 ASSERT (((A) & ~0xfffffff) == 0)
40 Registers a PCI device so PCI configuration registers may be accessed after
41 SetVirtualAddressMap().
43 Registers the PCI device specified by Address so all the PCI configuration
44 registers associated with that PCI device may be accessed after SetVirtualAddressMap()
47 If Address > 0x0FFFFFFF, then ASSERT().
49 @param Address The address that encodes the PCI Bus, Device, Function and
52 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
53 @retval RETURN_UNSUPPORTED An attempt was made to call this function
54 after ExitBootServices().
55 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
56 at runtime could not be mapped.
57 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
58 complete the registration.
63 PciExpressRegisterForRuntimeAccess (
67 ASSERT_INVALID_PCI_ADDRESS (Address
);
68 return RETURN_UNSUPPORTED
;
72 Gets the base address of PCI Express.
74 This internal functions retrieves PCI Express Base Address via a PCD entry
75 PcdPciExpressBaseAddress.
77 @return The base address of PCI Express.
81 GetPciExpressBaseAddress (
85 return (VOID
*)(UINTN
) PcdGet64 (PcdPciExpressBaseAddress
);
89 Reads an 8-bit PCI configuration register.
91 Reads and returns the 8-bit PCI configuration register specified by Address.
92 This function must guarantee that all PCI read and write operations are
95 If Address > 0x0FFFFFFF, then ASSERT().
97 @param Address The address that encodes the PCI Bus, Device, Function and
100 @return The read value from the PCI configuration register.
109 ASSERT_INVALID_PCI_ADDRESS (Address
);
110 return MmioRead8 ((UINTN
) GetPciExpressBaseAddress () + Address
);
114 Writes an 8-bit PCI configuration register.
116 Writes the 8-bit PCI configuration register specified by Address with the
117 value specified by Value. Value is returned. This function must guarantee
118 that all PCI read and write operations are serialized.
120 If Address > 0x0FFFFFFF, then ASSERT().
122 @param Address The address that encodes the PCI Bus, Device, Function and
124 @param Value The value to write.
126 @return The value written to the PCI configuration register.
136 ASSERT_INVALID_PCI_ADDRESS (Address
);
137 return MmioWrite8 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
141 Performs a bitwise OR of an 8-bit PCI configuration register with
144 Reads the 8-bit PCI configuration register specified by Address, performs a
145 bitwise OR between the read result and the value specified by
146 OrData, and writes the result to the 8-bit PCI configuration register
147 specified by Address. The value written to the PCI configuration register is
148 returned. This function must guarantee that all PCI read and write operations
151 If Address > 0x0FFFFFFF, then ASSERT().
153 @param Address The address that encodes the PCI Bus, Device, Function and
155 @param OrData The value to OR with the PCI configuration register.
157 @return The value written back to the PCI configuration register.
167 ASSERT_INVALID_PCI_ADDRESS (Address
);
168 return MmioOr8 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
172 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
175 Reads the 8-bit PCI configuration register specified by Address, performs a
176 bitwise AND between the read result and the value specified by AndData, and
177 writes the result to the 8-bit PCI configuration register specified by
178 Address. The value written to the PCI configuration register is returned.
179 This function must guarantee that all PCI read and write operations are
182 If Address > 0x0FFFFFFF, then ASSERT().
184 @param Address The address that encodes the PCI Bus, Device, Function and
186 @param AndData The value to AND with the PCI configuration register.
188 @return The value written back to the PCI configuration register.
198 ASSERT_INVALID_PCI_ADDRESS (Address
);
199 return MmioAnd8 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
203 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
204 value, followed a bitwise OR with another 8-bit value.
206 Reads the 8-bit PCI configuration register specified by Address, performs a
207 bitwise AND between the read result and the value specified by AndData,
208 performs a bitwise OR between the result of the AND operation and
209 the value specified by OrData, and writes the result to the 8-bit PCI
210 configuration register specified by Address. The value written to the PCI
211 configuration register is returned. This function must guarantee that all PCI
212 read and write operations are serialized.
214 If Address > 0x0FFFFFFF, then ASSERT().
216 @param Address The address that encodes the PCI Bus, Device, Function and
218 @param AndData The value to AND with the PCI configuration register.
219 @param OrData The value to OR with the result of the AND operation.
221 @return The value written back to the PCI configuration register.
226 PciExpressAndThenOr8 (
232 ASSERT_INVALID_PCI_ADDRESS (Address
);
233 return MmioAndThenOr8 (
234 (UINTN
) GetPciExpressBaseAddress () + Address
,
241 Reads a bit field of a PCI configuration register.
243 Reads the bit field in an 8-bit PCI configuration register. The bit field is
244 specified by the StartBit and the EndBit. The value of the bit field is
247 If Address > 0x0FFFFFFF, then ASSERT().
248 If StartBit is greater than 7, then ASSERT().
249 If EndBit is greater than 7, then ASSERT().
250 If EndBit is less than StartBit, then ASSERT().
252 @param Address The PCI configuration register to read.
253 @param StartBit The ordinal of the least significant bit in the bit field.
255 @param EndBit The ordinal of the most significant bit in the bit field.
258 @return The value of the bit field read from the PCI configuration register.
263 PciExpressBitFieldRead8 (
269 ASSERT_INVALID_PCI_ADDRESS (Address
);
270 return MmioBitFieldRead8 (
271 (UINTN
) GetPciExpressBaseAddress () + Address
,
278 Writes a bit field to a PCI configuration register.
280 Writes Value to the bit field of the PCI configuration register. The bit
281 field is specified by the StartBit and the EndBit. All other bits in the
282 destination PCI configuration register are preserved. The new value of the
283 8-bit register is returned.
285 If Address > 0x0FFFFFFF, then ASSERT().
286 If StartBit is greater than 7, then ASSERT().
287 If EndBit is greater than 7, then ASSERT().
288 If EndBit is less than StartBit, then ASSERT().
289 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
291 @param Address The PCI configuration register to write.
292 @param StartBit The ordinal of the least significant bit in the bit field.
294 @param EndBit The ordinal of the most significant bit in the bit field.
296 @param Value The new value of the bit field.
298 @return The value written back to the PCI configuration register.
303 PciExpressBitFieldWrite8 (
310 ASSERT_INVALID_PCI_ADDRESS (Address
);
311 return MmioBitFieldWrite8 (
312 (UINTN
) GetPciExpressBaseAddress () + Address
,
320 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
321 writes the result back to the bit field in the 8-bit port.
323 Reads the 8-bit PCI configuration register specified by Address, performs a
324 bitwise OR between the read result and the value specified by
325 OrData, and writes the result to the 8-bit PCI configuration register
326 specified by Address. The value written to the PCI configuration register is
327 returned. This function must guarantee that all PCI read and write operations
328 are serialized. Extra left bits in OrData are stripped.
330 If Address > 0x0FFFFFFF, then ASSERT().
331 If StartBit is greater than 7, then ASSERT().
332 If EndBit is greater than 7, then ASSERT().
333 If EndBit is less than StartBit, then ASSERT().
334 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
336 @param Address The PCI configuration register to write.
337 @param StartBit The ordinal of the least significant bit in the bit field.
339 @param EndBit The ordinal of the most significant bit in the bit field.
341 @param OrData The value to OR with the PCI configuration register.
343 @return The value written back to the PCI configuration register.
348 PciExpressBitFieldOr8 (
355 ASSERT_INVALID_PCI_ADDRESS (Address
);
356 return MmioBitFieldOr8 (
357 (UINTN
) GetPciExpressBaseAddress () + Address
,
365 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
366 AND, and writes the result back to the bit field in the 8-bit register.
368 Reads the 8-bit PCI configuration register specified by Address, performs a
369 bitwise AND between the read result and the value specified by AndData, and
370 writes the result to the 8-bit PCI configuration register specified by
371 Address. The value written to the PCI configuration register is returned.
372 This function must guarantee that all PCI read and write operations are
373 serialized. Extra left bits in AndData are stripped.
375 If Address > 0x0FFFFFFF, then ASSERT().
376 If StartBit is greater than 7, then ASSERT().
377 If EndBit is greater than 7, then ASSERT().
378 If EndBit is less than StartBit, then ASSERT().
379 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
381 @param Address The PCI configuration register to write.
382 @param StartBit The ordinal of the least significant bit in the bit field.
384 @param EndBit The ordinal of the most significant bit in the bit field.
386 @param AndData The value to AND with the PCI configuration register.
388 @return The value written back to the PCI configuration register.
393 PciExpressBitFieldAnd8 (
400 ASSERT_INVALID_PCI_ADDRESS (Address
);
401 return MmioBitFieldAnd8 (
402 (UINTN
) GetPciExpressBaseAddress () + Address
,
410 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
411 bitwise OR, and writes the result back to the bit field in the
414 Reads the 8-bit PCI configuration register specified by Address, performs a
415 bitwise AND followed by a bitwise OR between the read result and
416 the value specified by AndData, and writes the result to the 8-bit PCI
417 configuration register specified by Address. The value written to the PCI
418 configuration register is returned. This function must guarantee that all PCI
419 read and write operations are serialized. Extra left bits in both AndData and
422 If Address > 0x0FFFFFFF, then ASSERT().
423 If StartBit is greater than 7, then ASSERT().
424 If EndBit is greater than 7, then ASSERT().
425 If EndBit is less than StartBit, then ASSERT().
426 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
427 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
429 @param Address The PCI configuration register to write.
430 @param StartBit The ordinal of the least significant bit in the bit field.
432 @param EndBit The ordinal of the most significant bit in the bit field.
434 @param AndData The value to AND with the PCI configuration register.
435 @param OrData The value to OR with the result of the AND operation.
437 @return The value written back to the PCI configuration register.
442 PciExpressBitFieldAndThenOr8 (
450 ASSERT_INVALID_PCI_ADDRESS (Address
);
451 return MmioBitFieldAndThenOr8 (
452 (UINTN
) GetPciExpressBaseAddress () + Address
,
461 Reads a 16-bit PCI configuration register.
463 Reads and returns the 16-bit PCI configuration register specified by Address.
464 This function must guarantee that all PCI read and write operations are
467 If Address > 0x0FFFFFFF, then ASSERT().
468 If Address is not aligned on a 16-bit boundary, then ASSERT().
470 @param Address The address that encodes the PCI Bus, Device, Function and
473 @return The read value from the PCI configuration register.
482 ASSERT_INVALID_PCI_ADDRESS (Address
);
483 return MmioRead16 ((UINTN
) GetPciExpressBaseAddress () + Address
);
487 Writes a 16-bit PCI configuration register.
489 Writes the 16-bit PCI configuration register specified by Address with the
490 value specified by Value. Value is returned. This function must guarantee
491 that all PCI read and write operations are serialized.
493 If Address > 0x0FFFFFFF, then ASSERT().
494 If Address is not aligned on a 16-bit boundary, then ASSERT().
496 @param Address The address that encodes the PCI Bus, Device, Function and
498 @param Value The value to write.
500 @return The value written to the PCI configuration register.
510 ASSERT_INVALID_PCI_ADDRESS (Address
);
511 return MmioWrite16 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
515 Performs a bitwise OR of a 16-bit PCI configuration register with
518 Reads the 16-bit PCI configuration register specified by Address, performs a
519 bitwise OR between the read result and the value specified by
520 OrData, and writes the result to the 16-bit PCI configuration register
521 specified by Address. The value written to the PCI configuration register is
522 returned. This function must guarantee that all PCI read and write operations
525 If Address > 0x0FFFFFFF, then ASSERT().
526 If Address is not aligned on a 16-bit boundary, then ASSERT().
528 @param Address The address that encodes the PCI Bus, Device, Function and
530 @param OrData The value to OR with the PCI configuration register.
532 @return The value written back to the PCI configuration register.
542 ASSERT_INVALID_PCI_ADDRESS (Address
);
543 return MmioOr16 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
547 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
550 Reads the 16-bit PCI configuration register specified by Address, performs a
551 bitwise AND between the read result and the value specified by AndData, and
552 writes the result to the 16-bit PCI configuration register specified by
553 Address. The value written to the PCI configuration register is returned.
554 This function must guarantee that all PCI read and write operations are
557 If Address > 0x0FFFFFFF, then ASSERT().
558 If Address is not aligned on a 16-bit boundary, then ASSERT().
560 @param Address The address that encodes the PCI Bus, Device, Function and
562 @param AndData The value to AND with the PCI configuration register.
564 @return The value written back to the PCI configuration register.
574 ASSERT_INVALID_PCI_ADDRESS (Address
);
575 return MmioAnd16 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
579 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
580 value, followed a bitwise OR with another 16-bit value.
582 Reads the 16-bit PCI configuration register specified by Address, performs a
583 bitwise AND between the read result and the value specified by AndData,
584 performs a bitwise OR between the result of the AND operation and
585 the value specified by OrData, and writes the result to the 16-bit PCI
586 configuration register specified by Address. The value written to the PCI
587 configuration register is returned. This function must guarantee that all PCI
588 read and write operations are serialized.
590 If Address > 0x0FFFFFFF, then ASSERT().
591 If Address is not aligned on a 16-bit boundary, then ASSERT().
593 @param Address The address that encodes the PCI Bus, Device, Function and
595 @param AndData The value to AND with the PCI configuration register.
596 @param OrData The value to OR with the result of the AND operation.
598 @return The value written back to the PCI configuration register.
603 PciExpressAndThenOr16 (
609 ASSERT_INVALID_PCI_ADDRESS (Address
);
610 return MmioAndThenOr16 (
611 (UINTN
) GetPciExpressBaseAddress () + Address
,
618 Reads a bit field of a PCI configuration register.
620 Reads the bit field in a 16-bit PCI configuration register. The bit field is
621 specified by the StartBit and the EndBit. The value of the bit field is
624 If Address > 0x0FFFFFFF, then ASSERT().
625 If Address is not aligned on a 16-bit boundary, then ASSERT().
626 If StartBit is greater than 15, then ASSERT().
627 If EndBit is greater than 15, then ASSERT().
628 If EndBit is less than StartBit, then ASSERT().
630 @param Address The PCI configuration register to read.
631 @param StartBit The ordinal of the least significant bit in the bit field.
633 @param EndBit The ordinal of the most significant bit in the bit field.
636 @return The value of the bit field read from the PCI configuration register.
641 PciExpressBitFieldRead16 (
647 ASSERT_INVALID_PCI_ADDRESS (Address
);
648 return MmioBitFieldRead16 (
649 (UINTN
) GetPciExpressBaseAddress () + Address
,
656 Writes a bit field to a PCI configuration register.
658 Writes Value to the bit field of the PCI configuration register. The bit
659 field is specified by the StartBit and the EndBit. All other bits in the
660 destination PCI configuration register are preserved. The new value of the
661 16-bit register is returned.
663 If Address > 0x0FFFFFFF, then ASSERT().
664 If Address is not aligned on a 16-bit boundary, then ASSERT().
665 If StartBit is greater than 15, then ASSERT().
666 If EndBit is greater than 15, then ASSERT().
667 If EndBit is less than StartBit, then ASSERT().
668 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
670 @param Address The PCI configuration register to write.
671 @param StartBit The ordinal of the least significant bit in the bit field.
673 @param EndBit The ordinal of the most significant bit in the bit field.
675 @param Value The new value of the bit field.
677 @return The value written back to the PCI configuration register.
682 PciExpressBitFieldWrite16 (
689 ASSERT_INVALID_PCI_ADDRESS (Address
);
690 return MmioBitFieldWrite16 (
691 (UINTN
) GetPciExpressBaseAddress () + Address
,
699 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
700 writes the result back to the bit field in the 16-bit port.
702 Reads the 16-bit PCI configuration register specified by Address, performs a
703 bitwise OR between the read result and the value specified by
704 OrData, and writes the result to the 16-bit PCI configuration register
705 specified by Address. The value written to the PCI configuration register is
706 returned. This function must guarantee that all PCI read and write operations
707 are serialized. Extra left bits in OrData are stripped.
709 If Address > 0x0FFFFFFF, then ASSERT().
710 If Address is not aligned on a 16-bit boundary, then ASSERT().
711 If StartBit is greater than 15, then ASSERT().
712 If EndBit is greater than 15, then ASSERT().
713 If EndBit is less than StartBit, then ASSERT().
714 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
716 @param Address The PCI configuration register to write.
717 @param StartBit The ordinal of the least significant bit in the bit field.
719 @param EndBit The ordinal of the most significant bit in the bit field.
721 @param OrData The value to OR with the PCI configuration register.
723 @return The value written back to the PCI configuration register.
728 PciExpressBitFieldOr16 (
735 ASSERT_INVALID_PCI_ADDRESS (Address
);
736 return MmioBitFieldOr16 (
737 (UINTN
) GetPciExpressBaseAddress () + Address
,
745 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
746 AND, and writes the result back to the bit field in the 16-bit register.
748 Reads the 16-bit PCI configuration register specified by Address, performs a
749 bitwise AND between the read result and the value specified by AndData, and
750 writes the result to the 16-bit PCI configuration register specified by
751 Address. The value written to the PCI configuration register is returned.
752 This function must guarantee that all PCI read and write operations are
753 serialized. Extra left bits in AndData are stripped.
755 If Address > 0x0FFFFFFF, then ASSERT().
756 If Address is not aligned on a 16-bit boundary, then ASSERT().
757 If StartBit is greater than 15, then ASSERT().
758 If EndBit is greater than 15, then ASSERT().
759 If EndBit is less than StartBit, then ASSERT().
760 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
762 @param Address The PCI configuration register to write.
763 @param StartBit The ordinal of the least significant bit in the bit field.
765 @param EndBit The ordinal of the most significant bit in the bit field.
767 @param AndData The value to AND with the PCI configuration register.
769 @return The value written back to the PCI configuration register.
774 PciExpressBitFieldAnd16 (
781 ASSERT_INVALID_PCI_ADDRESS (Address
);
782 return MmioBitFieldAnd16 (
783 (UINTN
) GetPciExpressBaseAddress () + Address
,
791 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
792 bitwise OR, and writes the result back to the bit field in the
795 Reads the 16-bit PCI configuration register specified by Address, performs a
796 bitwise AND followed by a bitwise OR between the read result and
797 the value specified by AndData, and writes the result to the 16-bit PCI
798 configuration register specified by Address. The value written to the PCI
799 configuration register is returned. This function must guarantee that all PCI
800 read and write operations are serialized. Extra left bits in both AndData and
803 If Address > 0x0FFFFFFF, then ASSERT().
804 If Address is not aligned on a 16-bit boundary, then ASSERT().
805 If StartBit is greater than 15, then ASSERT().
806 If EndBit is greater than 15, then ASSERT().
807 If EndBit is less than StartBit, then ASSERT().
808 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
809 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
811 @param Address The PCI configuration register to write.
812 @param StartBit The ordinal of the least significant bit in the bit field.
814 @param EndBit The ordinal of the most significant bit in the bit field.
816 @param AndData The value to AND with the PCI configuration register.
817 @param OrData The value to OR with the result of the AND operation.
819 @return The value written back to the PCI configuration register.
824 PciExpressBitFieldAndThenOr16 (
832 ASSERT_INVALID_PCI_ADDRESS (Address
);
833 return MmioBitFieldAndThenOr16 (
834 (UINTN
) GetPciExpressBaseAddress () + Address
,
843 Reads a 32-bit PCI configuration register.
845 Reads and returns the 32-bit PCI configuration register specified by Address.
846 This function must guarantee that all PCI read and write operations are
849 If Address > 0x0FFFFFFF, then ASSERT().
850 If Address is not aligned on a 32-bit boundary, then ASSERT().
852 @param Address The address that encodes the PCI Bus, Device, Function and
855 @return The read value from the PCI configuration register.
864 ASSERT_INVALID_PCI_ADDRESS (Address
);
865 return MmioRead32 ((UINTN
) GetPciExpressBaseAddress () + Address
);
869 Writes a 32-bit PCI configuration register.
871 Writes the 32-bit PCI configuration register specified by Address with the
872 value specified by Value. Value is returned. This function must guarantee
873 that all PCI read and write operations are serialized.
875 If Address > 0x0FFFFFFF, then ASSERT().
876 If Address is not aligned on a 32-bit boundary, then ASSERT().
878 @param Address The address that encodes the PCI Bus, Device, Function and
880 @param Value The value to write.
882 @return The value written to the PCI configuration register.
892 ASSERT_INVALID_PCI_ADDRESS (Address
);
893 return MmioWrite32 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
897 Performs a bitwise OR of a 32-bit PCI configuration register with
900 Reads the 32-bit PCI configuration register specified by Address, performs a
901 bitwise OR between the read result and the value specified by
902 OrData, and writes the result to the 32-bit PCI configuration register
903 specified by Address. The value written to the PCI configuration register is
904 returned. This function must guarantee that all PCI read and write operations
907 If Address > 0x0FFFFFFF, then ASSERT().
908 If Address is not aligned on a 32-bit boundary, then ASSERT().
910 @param Address The address that encodes the PCI Bus, Device, Function and
912 @param OrData The value to OR with the PCI configuration register.
914 @return The value written back to the PCI configuration register.
924 ASSERT_INVALID_PCI_ADDRESS (Address
);
925 return MmioOr32 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
929 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
932 Reads the 32-bit PCI configuration register specified by Address, performs a
933 bitwise AND between the read result and the value specified by AndData, and
934 writes the result to the 32-bit PCI configuration register specified by
935 Address. The value written to the PCI configuration register is returned.
936 This function must guarantee that all PCI read and write operations are
939 If Address > 0x0FFFFFFF, then ASSERT().
940 If Address is not aligned on a 32-bit boundary, then ASSERT().
942 @param Address The address that encodes the PCI Bus, Device, Function and
944 @param AndData The value to AND with the PCI configuration register.
946 @return The value written back to the PCI configuration register.
956 ASSERT_INVALID_PCI_ADDRESS (Address
);
957 return MmioAnd32 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
961 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
962 value, followed a bitwise OR with another 32-bit value.
964 Reads the 32-bit PCI configuration register specified by Address, performs a
965 bitwise AND between the read result and the value specified by AndData,
966 performs a bitwise OR between the result of the AND operation and
967 the value specified by OrData, and writes the result to the 32-bit PCI
968 configuration register specified by Address. The value written to the PCI
969 configuration register is returned. This function must guarantee that all PCI
970 read and write operations are serialized.
972 If Address > 0x0FFFFFFF, then ASSERT().
973 If Address is not aligned on a 32-bit boundary, then ASSERT().
975 @param Address The address that encodes the PCI Bus, Device, Function and
977 @param AndData The value to AND with the PCI configuration register.
978 @param OrData The value to OR with the result of the AND operation.
980 @return The value written back to the PCI configuration register.
985 PciExpressAndThenOr32 (
991 ASSERT_INVALID_PCI_ADDRESS (Address
);
992 return MmioAndThenOr32 (
993 (UINTN
) GetPciExpressBaseAddress () + Address
,
1000 Reads a bit field of a PCI configuration register.
1002 Reads the bit field in a 32-bit PCI configuration register. The bit field is
1003 specified by the StartBit and the EndBit. The value of the bit field is
1006 If Address > 0x0FFFFFFF, then ASSERT().
1007 If Address is not aligned on a 32-bit boundary, then ASSERT().
1008 If StartBit is greater than 31, then ASSERT().
1009 If EndBit is greater than 31, then ASSERT().
1010 If EndBit is less than StartBit, then ASSERT().
1012 @param Address The PCI configuration register to read.
1013 @param StartBit The ordinal of the least significant bit in the bit field.
1015 @param EndBit The ordinal of the most significant bit in the bit field.
1018 @return The value of the bit field read from the PCI configuration register.
1023 PciExpressBitFieldRead32 (
1029 ASSERT_INVALID_PCI_ADDRESS (Address
);
1030 return MmioBitFieldRead32 (
1031 (UINTN
) GetPciExpressBaseAddress () + Address
,
1038 Writes a bit field to a PCI configuration register.
1040 Writes Value to the bit field of the PCI configuration register. The bit
1041 field is specified by the StartBit and the EndBit. All other bits in the
1042 destination PCI configuration register are preserved. The new value of the
1043 32-bit register is returned.
1045 If Address > 0x0FFFFFFF, then ASSERT().
1046 If Address is not aligned on a 32-bit boundary, then ASSERT().
1047 If StartBit is greater than 31, then ASSERT().
1048 If EndBit is greater than 31, then ASSERT().
1049 If EndBit is less than StartBit, then ASSERT().
1050 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1052 @param Address The PCI configuration register to write.
1053 @param StartBit The ordinal of the least significant bit in the bit field.
1055 @param EndBit The ordinal of the most significant bit in the bit field.
1057 @param Value The new value of the bit field.
1059 @return The value written back to the PCI configuration register.
1064 PciExpressBitFieldWrite32 (
1071 ASSERT_INVALID_PCI_ADDRESS (Address
);
1072 return MmioBitFieldWrite32 (
1073 (UINTN
) GetPciExpressBaseAddress () + Address
,
1081 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1082 writes the result back to the bit field in the 32-bit port.
1084 Reads the 32-bit PCI configuration register specified by Address, performs a
1085 bitwise OR between the read result and the value specified by
1086 OrData, and writes the result to the 32-bit PCI configuration register
1087 specified by Address. The value written to the PCI configuration register is
1088 returned. This function must guarantee that all PCI read and write operations
1089 are serialized. Extra left bits in OrData are stripped.
1091 If Address > 0x0FFFFFFF, then ASSERT().
1092 If Address is not aligned on a 32-bit boundary, then ASSERT().
1093 If StartBit is greater than 31, then ASSERT().
1094 If EndBit is greater than 31, then ASSERT().
1095 If EndBit is less than StartBit, then ASSERT().
1096 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1098 @param Address The PCI configuration register to write.
1099 @param StartBit The ordinal of the least significant bit in the bit field.
1101 @param EndBit The ordinal of the most significant bit in the bit field.
1103 @param OrData The value to OR with the PCI configuration register.
1105 @return The value written back to the PCI configuration register.
1110 PciExpressBitFieldOr32 (
1117 ASSERT_INVALID_PCI_ADDRESS (Address
);
1118 return MmioBitFieldOr32 (
1119 (UINTN
) GetPciExpressBaseAddress () + Address
,
1127 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1128 AND, and writes the result back to the bit field in the 32-bit register.
1130 Reads the 32-bit PCI configuration register specified by Address, performs a
1131 bitwise AND between the read result and the value specified by AndData, and
1132 writes the result to the 32-bit PCI configuration register specified by
1133 Address. The value written to the PCI configuration register is returned.
1134 This function must guarantee that all PCI read and write operations are
1135 serialized. Extra left bits in AndData are stripped.
1137 If Address > 0x0FFFFFFF, then ASSERT().
1138 If Address is not aligned on a 32-bit boundary, then ASSERT().
1139 If StartBit is greater than 31, then ASSERT().
1140 If EndBit is greater than 31, then ASSERT().
1141 If EndBit is less than StartBit, then ASSERT().
1142 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1144 @param Address The PCI configuration register to write.
1145 @param StartBit The ordinal of the least significant bit in the bit field.
1147 @param EndBit The ordinal of the most significant bit in the bit field.
1149 @param AndData The value to AND with the PCI configuration register.
1151 @return The value written back to the PCI configuration register.
1156 PciExpressBitFieldAnd32 (
1163 ASSERT_INVALID_PCI_ADDRESS (Address
);
1164 return MmioBitFieldAnd32 (
1165 (UINTN
) GetPciExpressBaseAddress () + Address
,
1173 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1174 bitwise OR, and writes the result back to the bit field in the
1177 Reads the 32-bit PCI configuration register specified by Address, performs a
1178 bitwise AND followed by a bitwise OR between the read result and
1179 the value specified by AndData, and writes the result to the 32-bit PCI
1180 configuration register specified by Address. The value written to the PCI
1181 configuration register is returned. This function must guarantee that all PCI
1182 read and write operations are serialized. Extra left bits in both AndData and
1183 OrData are stripped.
1185 If Address > 0x0FFFFFFF, then ASSERT().
1186 If Address is not aligned on a 32-bit boundary, then ASSERT().
1187 If StartBit is greater than 31, then ASSERT().
1188 If EndBit is greater than 31, then ASSERT().
1189 If EndBit is less than StartBit, then ASSERT().
1190 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1191 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1193 @param Address The PCI configuration register to write.
1194 @param StartBit The ordinal of the least significant bit in the bit field.
1196 @param EndBit The ordinal of the most significant bit in the bit field.
1198 @param AndData The value to AND with the PCI configuration register.
1199 @param OrData The value to OR with the result of the AND operation.
1201 @return The value written back to the PCI configuration register.
1206 PciExpressBitFieldAndThenOr32 (
1214 ASSERT_INVALID_PCI_ADDRESS (Address
);
1215 return MmioBitFieldAndThenOr32 (
1216 (UINTN
) GetPciExpressBaseAddress () + Address
,
1225 Reads a range of PCI configuration registers into a caller supplied buffer.
1227 Reads the range of PCI configuration registers specified by StartAddress and
1228 Size into the buffer specified by Buffer. This function only allows the PCI
1229 configuration registers from a single PCI function to be read. Size is
1230 returned. When possible 32-bit PCI configuration read cycles are used to read
1231 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1232 and 16-bit PCI configuration read cycles may be used at the beginning and the
1235 If StartAddress > 0x0FFFFFFF, then ASSERT().
1236 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1237 If Size > 0 and Buffer is NULL, then ASSERT().
1239 @param StartAddress The starting address that encodes the PCI Bus, Device,
1240 Function and Register.
1241 @param Size The size in bytes of the transfer.
1242 @param Buffer The pointer to a buffer receiving the data read.
1244 @return Size read data from StartAddress.
1249 PciExpressReadBuffer (
1250 IN UINTN StartAddress
,
1257 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1258 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1264 ASSERT (Buffer
!= NULL
);
1267 // Save Size for return
1271 if ((StartAddress
& 1) != 0) {
1273 // Read a byte if StartAddress is byte aligned
1275 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1276 StartAddress
+= sizeof (UINT8
);
1277 Size
-= sizeof (UINT8
);
1278 Buffer
= (UINT8
*)Buffer
+ 1;
1281 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1283 // Read a word if StartAddress is word aligned
1285 WriteUnaligned16 ((UINT16
*) Buffer
, (UINT16
) PciExpressRead16 (StartAddress
));
1287 StartAddress
+= sizeof (UINT16
);
1288 Size
-= sizeof (UINT16
);
1289 Buffer
= (UINT16
*)Buffer
+ 1;
1292 while (Size
>= sizeof (UINT32
)) {
1294 // Read as many double words as possible
1296 WriteUnaligned32 ((UINT32
*) Buffer
, (UINT32
) PciExpressRead32 (StartAddress
));
1298 StartAddress
+= sizeof (UINT32
);
1299 Size
-= sizeof (UINT32
);
1300 Buffer
= (UINT32
*)Buffer
+ 1;
1303 if (Size
>= sizeof (UINT16
)) {
1305 // Read the last remaining word if exist
1307 WriteUnaligned16 ((UINT16
*) Buffer
, (UINT16
) PciExpressRead16 (StartAddress
));
1308 StartAddress
+= sizeof (UINT16
);
1309 Size
-= sizeof (UINT16
);
1310 Buffer
= (UINT16
*)Buffer
+ 1;
1313 if (Size
>= sizeof (UINT8
)) {
1315 // Read the last remaining byte if exist
1317 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1324 Copies the data in a caller supplied buffer to a specified range of PCI
1325 configuration space.
1327 Writes the range of PCI configuration registers specified by StartAddress and
1328 Size from the buffer specified by Buffer. This function only allows the PCI
1329 configuration registers from a single PCI function to be written. Size is
1330 returned. When possible 32-bit PCI configuration write cycles are used to
1331 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1332 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1333 and the end of the range.
1335 If StartAddress > 0x0FFFFFFF, then ASSERT().
1336 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1337 If Size > 0 and Buffer is NULL, then ASSERT().
1339 @param StartAddress The starting address that encodes the PCI Bus, Device,
1340 Function and Register.
1341 @param Size The size in bytes of the transfer.
1342 @param Buffer The pointer to a buffer containing the data to write.
1344 @return Size written to StartAddress.
1349 PciExpressWriteBuffer (
1350 IN UINTN StartAddress
,
1357 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1358 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1364 ASSERT (Buffer
!= NULL
);
1367 // Save Size for return
1371 if ((StartAddress
& 1) != 0) {
1373 // Write a byte if StartAddress is byte aligned
1375 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1376 StartAddress
+= sizeof (UINT8
);
1377 Size
-= sizeof (UINT8
);
1378 Buffer
= (UINT8
*)Buffer
+ 1;
1381 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1383 // Write a word if StartAddress is word aligned
1385 PciExpressWrite16 (StartAddress
, ReadUnaligned16 ((UINT16
*)Buffer
));
1386 StartAddress
+= sizeof (UINT16
);
1387 Size
-= sizeof (UINT16
);
1388 Buffer
= (UINT16
*)Buffer
+ 1;
1391 while (Size
>= sizeof (UINT32
)) {
1393 // Write as many double words as possible
1395 PciExpressWrite32 (StartAddress
, ReadUnaligned32 ((UINT32
*)Buffer
));
1396 StartAddress
+= sizeof (UINT32
);
1397 Size
-= sizeof (UINT32
);
1398 Buffer
= (UINT32
*)Buffer
+ 1;
1401 if (Size
>= sizeof (UINT16
)) {
1403 // Write the last remaining word if exist
1405 PciExpressWrite16 (StartAddress
, ReadUnaligned16 ((UINT16
*)Buffer
));
1406 StartAddress
+= sizeof (UINT16
);
1407 Size
-= sizeof (UINT16
);
1408 Buffer
= (UINT16
*)Buffer
+ 1;
1411 if (Size
>= sizeof (UINT8
)) {
1413 // Write the last remaining byte if exist
1415 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);