]>
git.proxmox.com Git - mirror_edk2.git/blob - MdePkg/Library/BasePciExpressLib/PciExpressLib.c
2 Functions in this library instance make use of MMIO functions in IoLib to
3 access memory mapped PCI configuration space.
5 All assertions for I/O operations are handled in MMIO functions in the IoLib
8 Copyright (c) 2006 - 2008, Intel Corporation<BR>
9 All rights reserved. This program and the accompanying materials
10 are licensed and made available under the terms and conditions of the BSD License
11 which accompanies this distribution. The full text of the license may be found at
12 http://opensource.org/licenses/bsd-license.php
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
22 #include <Library/BaseLib.h>
23 #include <Library/PciExpressLib.h>
24 #include <Library/IoLib.h>
25 #include <Library/DebugLib.h>
26 #include <Library/PcdLib.h>
30 Assert the validity of a PCI address. A valid PCI address should contain 1's
31 only in the low 28 bits.
33 @param A The address to validate.
36 #define ASSERT_INVALID_PCI_ADDRESS(A) \
37 ASSERT (((A) & ~0xfffffff) == 0)
40 Registers a PCI device so PCI configuration registers may be accessed after
41 SetVirtualAddressMap().
43 Registers the PCI device specified by Address so all the PCI configuration
44 registers associated with that PCI device may be accessed after SetVirtualAddressMap()
47 If Address > 0x0FFFFFFF, then ASSERT().
49 @param Address Address that encodes the PCI Bus, Device, Function and
52 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
53 @retval RETURN_UNSUPPORTED An attempt was made to call this function
54 after ExitBootServices().
55 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
56 at runtime could not be mapped.
57 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
58 complete the registration.
63 PciExpressRegisterForRuntimeAccess (
67 return RETURN_UNSUPPORTED
;
71 Gets the base address of PCI Express.
73 This internal functions retrieves PCI Express Base Address via a PCD entry
74 PcdPciExpressBaseAddress.
76 @return The base address of PCI Express.
80 GetPciExpressBaseAddress (
84 return (VOID
*)(UINTN
) PcdGet64 (PcdPciExpressBaseAddress
);
88 Reads an 8-bit PCI configuration register.
90 Reads and returns the 8-bit PCI configuration register specified by Address.
91 This function must guarantee that all PCI read and write operations are
94 If Address > 0x0FFFFFFF, then ASSERT().
96 @param Address Address that encodes the PCI Bus, Device, Function and
99 @return The read value from the PCI configuration register.
108 ASSERT_INVALID_PCI_ADDRESS (Address
);
109 return MmioRead8 ((UINTN
) GetPciExpressBaseAddress () + Address
);
113 Writes an 8-bit PCI configuration register.
115 Writes the 8-bit PCI configuration register specified by Address with the
116 value specified by Value. Value is returned. This function must guarantee
117 that all PCI read and write operations are serialized.
119 If Address > 0x0FFFFFFF, then ASSERT().
121 @param Address Address that encodes the PCI Bus, Device, Function and
123 @param Value The value to write.
125 @return The value written to the PCI configuration register.
135 ASSERT_INVALID_PCI_ADDRESS (Address
);
136 return MmioWrite8 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
140 Performs a bitwise OR of an 8-bit PCI configuration register with
143 Reads the 8-bit PCI configuration register specified by Address, performs a
144 bitwise OR between the read result and the value specified by
145 OrData, and writes the result to the 8-bit PCI configuration register
146 specified by Address. The value written to the PCI configuration register is
147 returned. This function must guarantee that all PCI read and write operations
150 If Address > 0x0FFFFFFF, then ASSERT().
152 @param Address Address that encodes the PCI Bus, Device, Function and
154 @param OrData The value to OR with the PCI configuration register.
156 @return The value written back to the PCI configuration register.
166 ASSERT_INVALID_PCI_ADDRESS (Address
);
167 return MmioOr8 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
171 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
174 Reads the 8-bit PCI configuration register specified by Address, performs a
175 bitwise AND between the read result and the value specified by AndData, and
176 writes the result to the 8-bit PCI configuration register specified by
177 Address. The value written to the PCI configuration register is returned.
178 This function must guarantee that all PCI read and write operations are
181 If Address > 0x0FFFFFFF, then ASSERT().
183 @param Address Address that encodes the PCI Bus, Device, Function and
185 @param AndData The value to AND with the PCI configuration register.
187 @return The value written back to the PCI configuration register.
197 ASSERT_INVALID_PCI_ADDRESS (Address
);
198 return MmioAnd8 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
202 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
203 value, followed a bitwise OR with another 8-bit value.
205 Reads the 8-bit PCI configuration register specified by Address, performs a
206 bitwise AND between the read result and the value specified by AndData,
207 performs a bitwise OR between the result of the AND operation and
208 the value specified by OrData, and writes the result to the 8-bit PCI
209 configuration register specified by Address. The value written to the PCI
210 configuration register is returned. This function must guarantee that all PCI
211 read and write operations are serialized.
213 If Address > 0x0FFFFFFF, then ASSERT().
215 @param Address Address that encodes the PCI Bus, Device, Function and
217 @param AndData The value to AND with the PCI configuration register.
218 @param OrData The value to OR with the result of the AND operation.
220 @return The value written back to the PCI configuration register.
225 PciExpressAndThenOr8 (
231 ASSERT_INVALID_PCI_ADDRESS (Address
);
232 return MmioAndThenOr8 (
233 (UINTN
) GetPciExpressBaseAddress () + Address
,
240 Reads a bit field of a PCI configuration register.
242 Reads the bit field in an 8-bit PCI configuration register. The bit field is
243 specified by the StartBit and the EndBit. The value of the bit field is
246 If Address > 0x0FFFFFFF, then ASSERT().
247 If StartBit is greater than 7, then ASSERT().
248 If EndBit is greater than 7, then ASSERT().
249 If EndBit is less than StartBit, then ASSERT().
251 @param Address PCI configuration register to read.
252 @param StartBit The ordinal of the least significant bit in the bit field.
254 @param EndBit The ordinal of the most significant bit in the bit field.
257 @return The value of the bit field read from the PCI configuration register.
262 PciExpressBitFieldRead8 (
268 ASSERT_INVALID_PCI_ADDRESS (Address
);
269 return MmioBitFieldRead8 (
270 (UINTN
) GetPciExpressBaseAddress () + Address
,
277 Writes a bit field to a PCI configuration register.
279 Writes Value to the bit field of the PCI configuration register. The bit
280 field is specified by the StartBit and the EndBit. All other bits in the
281 destination PCI configuration register are preserved. The new value of the
282 8-bit register is returned.
284 If Address > 0x0FFFFFFF, then ASSERT().
285 If StartBit is greater than 7, then ASSERT().
286 If EndBit is greater than 7, then ASSERT().
287 If EndBit is less than StartBit, then ASSERT().
289 @param Address PCI configuration register to write.
290 @param StartBit The ordinal of the least significant bit in the bit field.
292 @param EndBit The ordinal of the most significant bit in the bit field.
294 @param Value New value of the bit field.
296 @return The value written back to the PCI configuration register.
301 PciExpressBitFieldWrite8 (
308 ASSERT_INVALID_PCI_ADDRESS (Address
);
309 return MmioBitFieldWrite8 (
310 (UINTN
) GetPciExpressBaseAddress () + Address
,
318 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
319 writes the result back to the bit field in the 8-bit port.
321 Reads the 8-bit PCI configuration register specified by Address, performs a
322 bitwise OR between the read result and the value specified by
323 OrData, and writes the result to the 8-bit PCI configuration register
324 specified by Address. The value written to the PCI configuration register is
325 returned. This function must guarantee that all PCI read and write operations
326 are serialized. Extra left bits in OrData are stripped.
328 If Address > 0x0FFFFFFF, then ASSERT().
329 If StartBit is greater than 7, then ASSERT().
330 If EndBit is greater than 7, then ASSERT().
331 If EndBit is less than StartBit, then ASSERT().
333 @param Address PCI configuration register to write.
334 @param StartBit The ordinal of the least significant bit in the bit field.
336 @param EndBit The ordinal of the most significant bit in the bit field.
338 @param OrData The value to OR with the PCI configuration register.
340 @return The value written back to the PCI configuration register.
345 PciExpressBitFieldOr8 (
352 ASSERT_INVALID_PCI_ADDRESS (Address
);
353 return MmioBitFieldOr8 (
354 (UINTN
) GetPciExpressBaseAddress () + Address
,
362 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
363 AND, and writes the result back to the bit field in the 8-bit register.
365 Reads the 8-bit PCI configuration register specified by Address, performs a
366 bitwise AND between the read result and the value specified by AndData, and
367 writes the result to the 8-bit PCI configuration register specified by
368 Address. The value written to the PCI configuration register is returned.
369 This function must guarantee that all PCI read and write operations are
370 serialized. Extra left bits in AndData are stripped.
372 If Address > 0x0FFFFFFF, then ASSERT().
373 If StartBit is greater than 7, then ASSERT().
374 If EndBit is greater than 7, then ASSERT().
375 If EndBit is less than StartBit, then ASSERT().
377 @param Address PCI configuration register to write.
378 @param StartBit The ordinal of the least significant bit in the bit field.
380 @param EndBit The ordinal of the most significant bit in the bit field.
382 @param AndData The value to AND with the PCI configuration register.
384 @return The value written back to the PCI configuration register.
389 PciExpressBitFieldAnd8 (
396 ASSERT_INVALID_PCI_ADDRESS (Address
);
397 return MmioBitFieldAnd8 (
398 (UINTN
) GetPciExpressBaseAddress () + Address
,
406 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
407 bitwise OR, and writes the result back to the bit field in the
410 Reads the 8-bit PCI configuration register specified by Address, performs a
411 bitwise AND followed by a bitwise OR between the read result and
412 the value specified by AndData, and writes the result to the 8-bit PCI
413 configuration register specified by Address. The value written to the PCI
414 configuration register is returned. This function must guarantee that all PCI
415 read and write operations are serialized. Extra left bits in both AndData and
418 If Address > 0x0FFFFFFF, then ASSERT().
419 If StartBit is greater than 7, then ASSERT().
420 If EndBit is greater than 7, then ASSERT().
421 If EndBit is less than StartBit, then ASSERT().
423 @param Address PCI configuration register to write.
424 @param StartBit The ordinal of the least significant bit in the bit field.
426 @param EndBit The ordinal of the most significant bit in the bit field.
428 @param AndData The value to AND with the PCI configuration register.
429 @param OrData The value to OR with the result of the AND operation.
431 @return The value written back to the PCI configuration register.
436 PciExpressBitFieldAndThenOr8 (
444 ASSERT_INVALID_PCI_ADDRESS (Address
);
445 return MmioBitFieldAndThenOr8 (
446 (UINTN
) GetPciExpressBaseAddress () + Address
,
455 Reads a 16-bit PCI configuration register.
457 Reads and returns the 16-bit PCI configuration register specified by Address.
458 This function must guarantee that all PCI read and write operations are
461 If Address > 0x0FFFFFFF, then ASSERT().
462 If Address is not aligned on a 16-bit boundary, then ASSERT().
464 @param Address Address that encodes the PCI Bus, Device, Function and
467 @return The read value from the PCI configuration register.
476 ASSERT_INVALID_PCI_ADDRESS (Address
);
477 return MmioRead16 ((UINTN
) GetPciExpressBaseAddress () + Address
);
481 Writes a 16-bit PCI configuration register.
483 Writes the 16-bit PCI configuration register specified by Address with the
484 value specified by Value. Value is returned. This function must guarantee
485 that all PCI read and write operations are serialized.
487 If Address > 0x0FFFFFFF, then ASSERT().
488 If Address is not aligned on a 16-bit boundary, then ASSERT().
490 @param Address Address that encodes the PCI Bus, Device, Function and
492 @param Value The value to write.
494 @return The value written to the PCI configuration register.
504 ASSERT_INVALID_PCI_ADDRESS (Address
);
505 return MmioWrite16 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
509 Performs a bitwise OR of a 16-bit PCI configuration register with
512 Reads the 16-bit PCI configuration register specified by Address, performs a
513 bitwise OR between the read result and the value specified by
514 OrData, and writes the result to the 16-bit PCI configuration register
515 specified by Address. The value written to the PCI configuration register is
516 returned. This function must guarantee that all PCI read and write operations
519 If Address > 0x0FFFFFFF, then ASSERT().
520 If Address is not aligned on a 16-bit boundary, then ASSERT().
522 @param Address Address that encodes the PCI Bus, Device, Function and
524 @param OrData The value to OR with the PCI configuration register.
526 @return The value written back to the PCI configuration register.
536 ASSERT_INVALID_PCI_ADDRESS (Address
);
537 return MmioOr16 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
541 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
544 Reads the 16-bit PCI configuration register specified by Address, performs a
545 bitwise AND between the read result and the value specified by AndData, and
546 writes the result to the 16-bit PCI configuration register specified by
547 Address. The value written to the PCI configuration register is returned.
548 This function must guarantee that all PCI read and write operations are
551 If Address > 0x0FFFFFFF, then ASSERT().
552 If Address is not aligned on a 16-bit boundary, then ASSERT().
554 @param Address Address that encodes the PCI Bus, Device, Function and
556 @param AndData The value to AND with the PCI configuration register.
558 @return The value written back to the PCI configuration register.
568 ASSERT_INVALID_PCI_ADDRESS (Address
);
569 return MmioAnd16 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
573 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
574 value, followed a bitwise OR with another 16-bit value.
576 Reads the 16-bit PCI configuration register specified by Address, performs a
577 bitwise AND between the read result and the value specified by AndData,
578 performs a bitwise OR between the result of the AND operation and
579 the value specified by OrData, and writes the result to the 16-bit PCI
580 configuration register specified by Address. The value written to the PCI
581 configuration register is returned. This function must guarantee that all PCI
582 read and write operations are serialized.
584 If Address > 0x0FFFFFFF, then ASSERT().
585 If Address is not aligned on a 16-bit boundary, then ASSERT().
587 @param Address Address that encodes the PCI Bus, Device, Function and
589 @param AndData The value to AND with the PCI configuration register.
590 @param OrData The value to OR with the result of the AND operation.
592 @return The value written back to the PCI configuration register.
597 PciExpressAndThenOr16 (
603 ASSERT_INVALID_PCI_ADDRESS (Address
);
604 return MmioAndThenOr16 (
605 (UINTN
) GetPciExpressBaseAddress () + Address
,
612 Reads a bit field of a PCI configuration register.
614 Reads the bit field in a 16-bit PCI configuration register. The bit field is
615 specified by the StartBit and the EndBit. The value of the bit field is
618 If Address > 0x0FFFFFFF, then ASSERT().
619 If Address is not aligned on a 16-bit boundary, then ASSERT().
620 If StartBit is greater than 15, then ASSERT().
621 If EndBit is greater than 15, then ASSERT().
622 If EndBit is less than StartBit, then ASSERT().
624 @param Address PCI configuration register to read.
625 @param StartBit The ordinal of the least significant bit in the bit field.
627 @param EndBit The ordinal of the most significant bit in the bit field.
630 @return The value of the bit field read from the PCI configuration register.
635 PciExpressBitFieldRead16 (
641 ASSERT_INVALID_PCI_ADDRESS (Address
);
642 return MmioBitFieldRead16 (
643 (UINTN
) GetPciExpressBaseAddress () + Address
,
650 Writes a bit field to a PCI configuration register.
652 Writes Value to the bit field of the PCI configuration register. The bit
653 field is specified by the StartBit and the EndBit. All other bits in the
654 destination PCI configuration register are preserved. The new value of the
655 16-bit register is returned.
657 If Address > 0x0FFFFFFF, then ASSERT().
658 If Address is not aligned on a 16-bit boundary, then ASSERT().
659 If StartBit is greater than 15, then ASSERT().
660 If EndBit is greater than 15, then ASSERT().
661 If EndBit is less than StartBit, then ASSERT().
663 @param Address PCI configuration register to write.
664 @param StartBit The ordinal of the least significant bit in the bit field.
666 @param EndBit The ordinal of the most significant bit in the bit field.
668 @param Value New value of the bit field.
670 @return The value written back to the PCI configuration register.
675 PciExpressBitFieldWrite16 (
682 ASSERT_INVALID_PCI_ADDRESS (Address
);
683 return MmioBitFieldWrite16 (
684 (UINTN
) GetPciExpressBaseAddress () + Address
,
692 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
693 writes the result back to the bit field in the 16-bit port.
695 Reads the 16-bit PCI configuration register specified by Address, performs a
696 bitwise OR between the read result and the value specified by
697 OrData, and writes the result to the 16-bit PCI configuration register
698 specified by Address. The value written to the PCI configuration register is
699 returned. This function must guarantee that all PCI read and write operations
700 are serialized. Extra left bits in OrData are stripped.
702 If Address > 0x0FFFFFFF, then ASSERT().
703 If Address is not aligned on a 16-bit boundary, then ASSERT().
704 If StartBit is greater than 15, then ASSERT().
705 If EndBit is greater than 15, then ASSERT().
706 If EndBit is less than StartBit, then ASSERT().
708 @param Address PCI configuration register to write.
709 @param StartBit The ordinal of the least significant bit in the bit field.
711 @param EndBit The ordinal of the most significant bit in the bit field.
713 @param OrData The value to OR with the PCI configuration register.
715 @return The value written back to the PCI configuration register.
720 PciExpressBitFieldOr16 (
727 ASSERT_INVALID_PCI_ADDRESS (Address
);
728 return MmioBitFieldOr16 (
729 (UINTN
) GetPciExpressBaseAddress () + Address
,
737 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
738 AND, and writes the result back to the bit field in the 16-bit register.
740 Reads the 16-bit PCI configuration register specified by Address, performs a
741 bitwise AND between the read result and the value specified by AndData, and
742 writes the result to the 16-bit PCI configuration register specified by
743 Address. The value written to the PCI configuration register is returned.
744 This function must guarantee that all PCI read and write operations are
745 serialized. Extra left bits in AndData are stripped.
747 If Address > 0x0FFFFFFF, then ASSERT().
748 If Address is not aligned on a 16-bit boundary, then ASSERT().
749 If StartBit is greater than 15, then ASSERT().
750 If EndBit is greater than 15, then ASSERT().
751 If EndBit is less than StartBit, then ASSERT().
753 @param Address PCI configuration register to write.
754 @param StartBit The ordinal of the least significant bit in the bit field.
756 @param EndBit The ordinal of the most significant bit in the bit field.
758 @param AndData The value to AND with the PCI configuration register.
760 @return The value written back to the PCI configuration register.
765 PciExpressBitFieldAnd16 (
772 ASSERT_INVALID_PCI_ADDRESS (Address
);
773 return MmioBitFieldAnd16 (
774 (UINTN
) GetPciExpressBaseAddress () + Address
,
782 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
783 bitwise OR, and writes the result back to the bit field in the
786 Reads the 16-bit PCI configuration register specified by Address, performs a
787 bitwise AND followed by a bitwise OR between the read result and
788 the value specified by AndData, and writes the result to the 16-bit PCI
789 configuration register specified by Address. The value written to the PCI
790 configuration register is returned. This function must guarantee that all PCI
791 read and write operations are serialized. Extra left bits in both AndData and
794 If Address > 0x0FFFFFFF, then ASSERT().
795 If Address is not aligned on a 16-bit boundary, then ASSERT().
796 If StartBit is greater than 15, then ASSERT().
797 If EndBit is greater than 15, then ASSERT().
798 If EndBit is less than StartBit, then ASSERT().
800 @param Address PCI configuration register to write.
801 @param StartBit The ordinal of the least significant bit in the bit field.
803 @param EndBit The ordinal of the most significant bit in the bit field.
805 @param AndData The value to AND with the PCI configuration register.
806 @param OrData The value to OR with the result of the AND operation.
808 @return The value written back to the PCI configuration register.
813 PciExpressBitFieldAndThenOr16 (
821 ASSERT_INVALID_PCI_ADDRESS (Address
);
822 return MmioBitFieldAndThenOr16 (
823 (UINTN
) GetPciExpressBaseAddress () + Address
,
832 Reads a 32-bit PCI configuration register.
834 Reads and returns the 32-bit PCI configuration register specified by Address.
835 This function must guarantee that all PCI read and write operations are
838 If Address > 0x0FFFFFFF, then ASSERT().
839 If Address is not aligned on a 32-bit boundary, then ASSERT().
841 @param Address Address that encodes the PCI Bus, Device, Function and
844 @return The read value from the PCI configuration register.
853 ASSERT_INVALID_PCI_ADDRESS (Address
);
854 return MmioRead32 ((UINTN
) GetPciExpressBaseAddress () + Address
);
858 Writes a 32-bit PCI configuration register.
860 Writes the 32-bit PCI configuration register specified by Address with the
861 value specified by Value. Value is returned. This function must guarantee
862 that all PCI read and write operations are serialized.
864 If Address > 0x0FFFFFFF, then ASSERT().
865 If Address is not aligned on a 32-bit boundary, then ASSERT().
867 @param Address Address that encodes the PCI Bus, Device, Function and
869 @param Value The value to write.
871 @return The value written to the PCI configuration register.
881 ASSERT_INVALID_PCI_ADDRESS (Address
);
882 return MmioWrite32 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
886 Performs a bitwise OR of a 32-bit PCI configuration register with
889 Reads the 32-bit PCI configuration register specified by Address, performs a
890 bitwise OR between the read result and the value specified by
891 OrData, and writes the result to the 32-bit PCI configuration register
892 specified by Address. The value written to the PCI configuration register is
893 returned. This function must guarantee that all PCI read and write operations
896 If Address > 0x0FFFFFFF, then ASSERT().
897 If Address is not aligned on a 32-bit boundary, then ASSERT().
899 @param Address Address that encodes the PCI Bus, Device, Function and
901 @param OrData The value to OR with the PCI configuration register.
903 @return The value written back to the PCI configuration register.
913 ASSERT_INVALID_PCI_ADDRESS (Address
);
914 return MmioOr32 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
918 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
921 Reads the 32-bit PCI configuration register specified by Address, performs a
922 bitwise AND between the read result and the value specified by AndData, and
923 writes the result to the 32-bit PCI configuration register specified by
924 Address. The value written to the PCI configuration register is returned.
925 This function must guarantee that all PCI read and write operations are
928 If Address > 0x0FFFFFFF, then ASSERT().
929 If Address is not aligned on a 32-bit boundary, then ASSERT().
931 @param Address Address that encodes the PCI Bus, Device, Function and
933 @param AndData The value to AND with the PCI configuration register.
935 @return The value written back to the PCI configuration register.
945 ASSERT_INVALID_PCI_ADDRESS (Address
);
946 return MmioAnd32 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
950 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
951 value, followed a bitwise OR with another 32-bit value.
953 Reads the 32-bit PCI configuration register specified by Address, performs a
954 bitwise AND between the read result and the value specified by AndData,
955 performs a bitwise OR between the result of the AND operation and
956 the value specified by OrData, and writes the result to the 32-bit PCI
957 configuration register specified by Address. The value written to the PCI
958 configuration register is returned. This function must guarantee that all PCI
959 read and write operations are serialized.
961 If Address > 0x0FFFFFFF, then ASSERT().
962 If Address is not aligned on a 32-bit boundary, then ASSERT().
964 @param Address Address that encodes the PCI Bus, Device, Function and
966 @param AndData The value to AND with the PCI configuration register.
967 @param OrData The value to OR with the result of the AND operation.
969 @return The value written back to the PCI configuration register.
974 PciExpressAndThenOr32 (
980 ASSERT_INVALID_PCI_ADDRESS (Address
);
981 return MmioAndThenOr32 (
982 (UINTN
) GetPciExpressBaseAddress () + Address
,
989 Reads a bit field of a PCI configuration register.
991 Reads the bit field in a 32-bit PCI configuration register. The bit field is
992 specified by the StartBit and the EndBit. The value of the bit field is
995 If Address > 0x0FFFFFFF, then ASSERT().
996 If Address is not aligned on a 32-bit boundary, then ASSERT().
997 If StartBit is greater than 31, then ASSERT().
998 If EndBit is greater than 31, then ASSERT().
999 If EndBit is less than StartBit, then ASSERT().
1001 @param Address PCI configuration register to read.
1002 @param StartBit The ordinal of the least significant bit in the bit field.
1004 @param EndBit The ordinal of the most significant bit in the bit field.
1007 @return The value of the bit field read from the PCI configuration register.
1012 PciExpressBitFieldRead32 (
1018 ASSERT_INVALID_PCI_ADDRESS (Address
);
1019 return MmioBitFieldRead32 (
1020 (UINTN
) GetPciExpressBaseAddress () + Address
,
1027 Writes a bit field to a PCI configuration register.
1029 Writes Value to the bit field of the PCI configuration register. The bit
1030 field is specified by the StartBit and the EndBit. All other bits in the
1031 destination PCI configuration register are preserved. The new value of the
1032 32-bit register is returned.
1034 If Address > 0x0FFFFFFF, then ASSERT().
1035 If Address is not aligned on a 32-bit boundary, then ASSERT().
1036 If StartBit is greater than 31, then ASSERT().
1037 If EndBit is greater than 31, then ASSERT().
1038 If EndBit is less than StartBit, then ASSERT().
1040 @param Address PCI configuration register to write.
1041 @param StartBit The ordinal of the least significant bit in the bit field.
1043 @param EndBit The ordinal of the most significant bit in the bit field.
1045 @param Value New value of the bit field.
1047 @return The value written back to the PCI configuration register.
1052 PciExpressBitFieldWrite32 (
1059 ASSERT_INVALID_PCI_ADDRESS (Address
);
1060 return MmioBitFieldWrite32 (
1061 (UINTN
) GetPciExpressBaseAddress () + Address
,
1069 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1070 writes the result back to the bit field in the 32-bit port.
1072 Reads the 32-bit PCI configuration register specified by Address, performs a
1073 bitwise OR between the read result and the value specified by
1074 OrData, and writes the result to the 32-bit PCI configuration register
1075 specified by Address. The value written to the PCI configuration register is
1076 returned. This function must guarantee that all PCI read and write operations
1077 are serialized. Extra left bits in OrData are stripped.
1079 If Address > 0x0FFFFFFF, then ASSERT().
1080 If Address is not aligned on a 32-bit boundary, then ASSERT().
1081 If StartBit is greater than 31, then ASSERT().
1082 If EndBit is greater than 31, then ASSERT().
1083 If EndBit is less than StartBit, then ASSERT().
1085 @param Address PCI configuration register to write.
1086 @param StartBit The ordinal of the least significant bit in the bit field.
1088 @param EndBit The ordinal of the most significant bit in the bit field.
1090 @param OrData The value to OR with the PCI configuration register.
1092 @return The value written back to the PCI configuration register.
1097 PciExpressBitFieldOr32 (
1104 ASSERT_INVALID_PCI_ADDRESS (Address
);
1105 return MmioBitFieldOr32 (
1106 (UINTN
) GetPciExpressBaseAddress () + Address
,
1114 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1115 AND, and writes the result back to the bit field in the 32-bit register.
1117 Reads the 32-bit PCI configuration register specified by Address, performs a
1118 bitwise AND between the read result and the value specified by AndData, and
1119 writes the result to the 32-bit PCI configuration register specified by
1120 Address. The value written to the PCI configuration register is returned.
1121 This function must guarantee that all PCI read and write operations are
1122 serialized. Extra left bits in AndData are stripped.
1124 If Address > 0x0FFFFFFF, then ASSERT().
1125 If Address is not aligned on a 32-bit boundary, then ASSERT().
1126 If StartBit is greater than 31, then ASSERT().
1127 If EndBit is greater than 31, then ASSERT().
1128 If EndBit is less than StartBit, then ASSERT().
1130 @param Address PCI configuration register to write.
1131 @param StartBit The ordinal of the least significant bit in the bit field.
1133 @param EndBit The ordinal of the most significant bit in the bit field.
1135 @param AndData The value to AND with the PCI configuration register.
1137 @return The value written back to the PCI configuration register.
1142 PciExpressBitFieldAnd32 (
1149 ASSERT_INVALID_PCI_ADDRESS (Address
);
1150 return MmioBitFieldAnd32 (
1151 (UINTN
) GetPciExpressBaseAddress () + Address
,
1159 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1160 bitwise OR, and writes the result back to the bit field in the
1163 Reads the 32-bit PCI configuration register specified by Address, performs a
1164 bitwise AND followed by a bitwise OR between the read result and
1165 the value specified by AndData, and writes the result to the 32-bit PCI
1166 configuration register specified by Address. The value written to the PCI
1167 configuration register is returned. This function must guarantee that all PCI
1168 read and write operations are serialized. Extra left bits in both AndData and
1169 OrData are stripped.
1171 If Address > 0x0FFFFFFF, then ASSERT().
1172 If Address is not aligned on a 32-bit boundary, then ASSERT().
1173 If StartBit is greater than 31, then ASSERT().
1174 If EndBit is greater than 31, then ASSERT().
1175 If EndBit is less than StartBit, then ASSERT().
1177 @param Address PCI configuration register to write.
1178 @param StartBit The ordinal of the least significant bit in the bit field.
1180 @param EndBit The ordinal of the most significant bit in the bit field.
1182 @param AndData The value to AND with the PCI configuration register.
1183 @param OrData The value to OR with the result of the AND operation.
1185 @return The value written back to the PCI configuration register.
1190 PciExpressBitFieldAndThenOr32 (
1198 ASSERT_INVALID_PCI_ADDRESS (Address
);
1199 return MmioBitFieldAndThenOr32 (
1200 (UINTN
) GetPciExpressBaseAddress () + Address
,
1209 Reads a range of PCI configuration registers into a caller supplied buffer.
1211 Reads the range of PCI configuration registers specified by StartAddress and
1212 Size into the buffer specified by Buffer. This function only allows the PCI
1213 configuration registers from a single PCI function to be read. Size is
1214 returned. When possible 32-bit PCI configuration read cycles are used to read
1215 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1216 and 16-bit PCI configuration read cycles may be used at the beginning and the
1219 If StartAddress > 0x0FFFFFFF, then ASSERT().
1220 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1221 If Size > 0 and Buffer is NULL, then ASSERT().
1223 @param StartAddress Starting address that encodes the PCI Bus, Device,
1224 Function and Register.
1225 @param Size Size in bytes of the transfer.
1226 @param Buffer Pointer to a buffer receiving the data read.
1228 @return Size read data from StartAddress.
1233 PciExpressReadBuffer (
1234 IN UINTN StartAddress
,
1241 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1242 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1248 ASSERT (Buffer
!= NULL
);
1251 // Save Size for return
1255 if ((StartAddress
& 1) != 0) {
1257 // Read a byte if StartAddress is byte aligned
1259 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1260 StartAddress
+= sizeof (UINT8
);
1261 Size
-= sizeof (UINT8
);
1262 Buffer
= (UINT8
*)Buffer
+ 1;
1265 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1267 // Read a word if StartAddress is word aligned
1269 WriteUnaligned16 ((UINT16
*) Buffer
, (UINT16
) PciExpressRead16 (StartAddress
));
1271 StartAddress
+= sizeof (UINT16
);
1272 Size
-= sizeof (UINT16
);
1273 Buffer
= (UINT16
*)Buffer
+ 1;
1276 while (Size
>= sizeof (UINT32
)) {
1278 // Read as many double words as possible
1280 WriteUnaligned32 ((UINT32
*) Buffer
, (UINT32
) PciExpressRead32 (StartAddress
));
1282 StartAddress
+= sizeof (UINT32
);
1283 Size
-= sizeof (UINT32
);
1284 Buffer
= (UINT32
*)Buffer
+ 1;
1287 if (Size
>= sizeof (UINT16
)) {
1289 // Read the last remaining word if exist
1291 WriteUnaligned16 ((UINT16
*) Buffer
, (UINT16
) PciExpressRead16 (StartAddress
));
1292 StartAddress
+= sizeof (UINT16
);
1293 Size
-= sizeof (UINT16
);
1294 Buffer
= (UINT16
*)Buffer
+ 1;
1297 if (Size
>= sizeof (UINT8
)) {
1299 // Read the last remaining byte if exist
1301 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1308 Copies the data in a caller supplied buffer to a specified range of PCI
1309 configuration space.
1311 Writes the range of PCI configuration registers specified by StartAddress and
1312 Size from the buffer specified by Buffer. This function only allows the PCI
1313 configuration registers from a single PCI function to be written. Size is
1314 returned. When possible 32-bit PCI configuration write cycles are used to
1315 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1316 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1317 and the end of the range.
1319 If StartAddress > 0x0FFFFFFF, then ASSERT().
1320 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1321 If Size > 0 and Buffer is NULL, then ASSERT().
1323 @param StartAddress Starting address that encodes the PCI Bus, Device,
1324 Function and Register.
1325 @param Size Size in bytes of the transfer.
1326 @param Buffer Pointer to a buffer containing the data to write.
1328 @return Size written to StartAddress.
1333 PciExpressWriteBuffer (
1334 IN UINTN StartAddress
,
1341 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1342 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1348 ASSERT (Buffer
!= NULL
);
1351 // Save Size for return
1355 if ((StartAddress
& 1) != 0) {
1357 // Write a byte if StartAddress is byte aligned
1359 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1360 StartAddress
+= sizeof (UINT8
);
1361 Size
-= sizeof (UINT8
);
1362 Buffer
= (UINT8
*)Buffer
+ 1;
1365 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1367 // Write a word if StartAddress is word aligned
1369 PciExpressWrite16 (StartAddress
, ReadUnaligned16 ((UINT16
*)Buffer
));
1370 StartAddress
+= sizeof (UINT16
);
1371 Size
-= sizeof (UINT16
);
1372 Buffer
= (UINT16
*)Buffer
+ 1;
1375 while (Size
>= sizeof (UINT32
)) {
1377 // Write as many double words as possible
1379 PciExpressWrite32 (StartAddress
, ReadUnaligned32 ((UINT32
*)Buffer
));
1380 StartAddress
+= sizeof (UINT32
);
1381 Size
-= sizeof (UINT32
);
1382 Buffer
= (UINT32
*)Buffer
+ 1;
1385 if (Size
>= sizeof (UINT16
)) {
1387 // Write the last remaining word if exist
1389 PciExpressWrite16 (StartAddress
, ReadUnaligned16 ((UINT16
*)Buffer
));
1390 StartAddress
+= sizeof (UINT16
);
1391 Size
-= sizeof (UINT16
);
1392 Buffer
= (UINT16
*)Buffer
+ 1;
1395 if (Size
>= sizeof (UINT8
)) {
1397 // Write the last remaining byte if exist
1399 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);