]>
git.proxmox.com Git - mirror_edk2.git/blob - MdePkg/Library/BasePciExpressLib/PciLib.c
4 Functions in this library instance make use of MMIO functions in IoLib to
5 access memory mapped PCI configuration space.
7 All assertions for I/O operations are handled in MMIO functions in the IoLib
10 Copyright (c) 2006, Intel Corporation<BR>
11 All rights reserved. This program and the accompanying materials
12 are licensed and made available under the terms and conditions of the BSD License
13 which accompanies this distribution. The full text of the license may be found at
14 http://opensource.org/licenses/bsd-license.php
16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
17 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
24 Assert the validity of a PCI address. A valid PCI address should contain 1's
25 only in the low 28 bits.
27 @param A The address to validate.
30 #define ASSERT_INVALID_PCI_ADDRESS(A) \
31 ASSERT (((A) & ~0xfffffff) == 0)
36 GetPciExpressBaseAddress (
40 /// @bug Change this to a PCD Get call to retrieve the PCI-E Base Address
45 Reads an 8-bit PCI configuration register.
47 Reads and returns the 8-bit PCI configuration register specified by Address.
48 This function must guarantee that all PCI read and write operations are
51 If Address > 0x0FFFFFFF, then ASSERT().
53 @param Address Address that encodes the PCI Bus, Device, Function and
56 @return The read value from the PCI configuration register.
65 ASSERT_INVALID_PCI_ADDRESS (Address
);
66 return MmioRead8 (GetPciExpressBaseAddress () + Address
);
70 Writes an 8-bit PCI configuration register.
72 Writes the 8-bit PCI configuration register specified by Address with the
73 value specified by Value. Value is returned. This function must guarantee
74 that all PCI read and write operations are serialized.
76 If Address > 0x0FFFFFFF, then ASSERT().
78 @param Address Address that encodes the PCI Bus, Device, Function and
80 @param Value The value to write.
82 @return The value written to the PCI configuration register.
92 ASSERT_INVALID_PCI_ADDRESS (Address
);
93 return MmioWrite8 (GetPciExpressBaseAddress () + Address
, Value
);
97 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
100 Reads the 8-bit PCI configuration register specified by Address, performs a
101 bitwise inclusive OR between the read result and the value specified by
102 OrData, and writes the result to the 8-bit PCI configuration register
103 specified by Address. The value written to the PCI configuration register is
104 returned. This function must guarantee that all PCI read and write operations
107 If Address > 0x0FFFFFFF, then ASSERT().
109 @param Address Address that encodes the PCI Bus, Device, Function and
111 @param OrData The value to OR with the PCI configuration register.
113 @return The value written back to the PCI configuration register.
123 ASSERT_INVALID_PCI_ADDRESS (Address
);
124 return MmioOr8 (GetPciExpressBaseAddress () + Address
, OrData
);
128 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
131 Reads the 8-bit PCI configuration register specified by Address, performs a
132 bitwise AND between the read result and the value specified by AndData, and
133 writes the result to the 8-bit PCI configuration register specified by
134 Address. The value written to the PCI configuration register is returned.
135 This function must guarantee that all PCI read and write operations are
138 If Address > 0x0FFFFFFF, then ASSERT().
140 @param Address Address that encodes the PCI Bus, Device, Function and
142 @param AndData The value to AND with the PCI configuration register.
144 @return The value written back to the PCI configuration register.
154 ASSERT_INVALID_PCI_ADDRESS (Address
);
155 return MmioAnd8 (GetPciExpressBaseAddress () + Address
, AndData
);
159 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
160 value, followed a bitwise inclusive OR with another 8-bit value.
162 Reads the 8-bit PCI configuration register specified by Address, performs a
163 bitwise AND between the read result and the value specified by AndData,
164 performs a bitwise inclusive OR between the result of the AND operation and
165 the value specified by OrData, and writes the result to the 8-bit PCI
166 configuration register specified by Address. The value written to the PCI
167 configuration register is returned. This function must guarantee that all PCI
168 read and write operations are serialized.
170 If Address > 0x0FFFFFFF, then ASSERT().
172 @param Address Address that encodes the PCI Bus, Device, Function and
174 @param AndData The value to AND with the PCI configuration register.
175 @param OrData The value to OR with the result of the AND operation.
177 @return The value written back to the PCI configuration register.
182 PciExpressAndThenOr8 (
188 ASSERT_INVALID_PCI_ADDRESS (Address
);
189 return MmioAndThenOr8 (
190 GetPciExpressBaseAddress () + Address
,
197 Reads a bit field of a PCI configuration register.
199 Reads the bit field in an 8-bit PCI configuration register. The bit field is
200 specified by the StartBit and the EndBit. The value of the bit field is
203 If Address > 0x0FFFFFFF, then ASSERT().
204 If StartBit is greater than 7, then ASSERT().
205 If EndBit is greater than 7, then ASSERT().
206 If EndBit is less than or equal to StartBit, then ASSERT().
208 @param Address PCI configuration register to read.
209 @param StartBit The ordinal of the least significant bit in the bit field.
211 @param EndBit The ordinal of the most significant bit in the bit field.
214 @return The value of the bit field read from the PCI configuration register.
219 PciExpressBitFieldRead8 (
225 ASSERT_INVALID_PCI_ADDRESS (Address
);
226 return MmioBitFieldRead8 (
227 GetPciExpressBaseAddress () + Address
,
234 Writes a bit field to a PCI configuration register.
236 Writes Value to the bit field of the PCI configuration register. The bit
237 field is specified by the StartBit and the EndBit. All other bits in the
238 destination PCI configuration register are preserved. The new value of the
239 8-bit register is returned.
241 If Address > 0x0FFFFFFF, then ASSERT().
242 If StartBit is greater than 7, then ASSERT().
243 If EndBit is greater than 7, then ASSERT().
244 If EndBit is less than or equal to StartBit, then ASSERT().
246 @param Address PCI configuration register to write.
247 @param StartBit The ordinal of the least significant bit in the bit field.
249 @param EndBit The ordinal of the most significant bit in the bit field.
251 @param Value New value of the bit field.
253 @return The value written back to the PCI configuration register.
258 PciExpressBitFieldWrite8 (
265 ASSERT_INVALID_PCI_ADDRESS (Address
);
266 return MmioBitFieldWrite8 (
267 GetPciExpressBaseAddress () + Address
,
275 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
276 writes the result back to the bit field in the 8-bit port.
278 Reads the 8-bit PCI configuration register specified by Address, performs a
279 bitwise inclusive OR between the read result and the value specified by
280 OrData, and writes the result to the 8-bit PCI configuration register
281 specified by Address. The value written to the PCI configuration register is
282 returned. This function must guarantee that all PCI read and write operations
283 are serialized. Extra left bits in OrData are stripped.
285 If Address > 0x0FFFFFFF, then ASSERT().
286 If StartBit is greater than 7, then ASSERT().
287 If EndBit is greater than 7, then ASSERT().
288 If EndBit is less than or equal to StartBit, then ASSERT().
290 @param Address PCI configuration register to write.
291 @param StartBit The ordinal of the least significant bit in the bit field.
293 @param EndBit The ordinal of the most significant bit in the bit field.
295 @param OrData The value to OR with the PCI configuration register.
297 @return The value written back to the PCI configuration register.
302 PciExpressBitFieldOr8 (
309 ASSERT_INVALID_PCI_ADDRESS (Address
);
310 return MmioBitFieldOr8 (
311 GetPciExpressBaseAddress () + Address
,
319 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
320 AND, and writes the result back to the bit field in the 8-bit register.
322 Reads the 8-bit PCI configuration register specified by Address, performs a
323 bitwise AND between the read result and the value specified by AndData, and
324 writes the result to the 8-bit PCI configuration register specified by
325 Address. The value written to the PCI configuration register is returned.
326 This function must guarantee that all PCI read and write operations are
327 serialized. Extra left bits in AndData are stripped.
329 If Address > 0x0FFFFFFF, then ASSERT().
330 If StartBit is greater than 7, then ASSERT().
331 If EndBit is greater than 7, then ASSERT().
332 If EndBit is less than or equal to StartBit, then ASSERT().
334 @param Address PCI configuration register to write.
335 @param StartBit The ordinal of the least significant bit in the bit field.
337 @param EndBit The ordinal of the most significant bit in the bit field.
339 @param AndData The value to AND with the PCI configuration register.
341 @return The value written back to the PCI configuration register.
346 PciExpressBitFieldAnd8 (
353 ASSERT_INVALID_PCI_ADDRESS (Address
);
354 return MmioBitFieldAnd8 (
355 GetPciExpressBaseAddress () + Address
,
363 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
364 bitwise inclusive OR, and writes the result back to the bit field in the
367 Reads the 8-bit PCI configuration register specified by Address, performs a
368 bitwise AND followed by a bitwise inclusive OR between the read result and
369 the value specified by AndData, and writes the result to the 8-bit PCI
370 configuration register specified by Address. The value written to the PCI
371 configuration register is returned. This function must guarantee that all PCI
372 read and write operations are serialized. Extra left bits in both AndData and
375 If Address > 0x0FFFFFFF, then ASSERT().
376 If StartBit is greater than 7, then ASSERT().
377 If EndBit is greater than 7, then ASSERT().
378 If EndBit is less than or equal to StartBit, then ASSERT().
380 @param Address PCI configuration register to write.
381 @param StartBit The ordinal of the least significant bit in the bit field.
383 @param EndBit The ordinal of the most significant bit in the bit field.
385 @param AndData The value to AND with the PCI configuration register.
386 @param OrData The value to OR with the result of the AND operation.
388 @return The value written back to the PCI configuration register.
393 PciExpressBitFieldAndThenOr8 (
401 ASSERT_INVALID_PCI_ADDRESS (Address
);
402 return MmioBitFieldAndThenOr8 (
403 GetPciExpressBaseAddress () + Address
,
412 Reads a 16-bit PCI configuration register.
414 Reads and returns the 16-bit PCI configuration register specified by Address.
415 This function must guarantee that all PCI read and write operations are
418 If Address > 0x0FFFFFFF, then ASSERT().
419 If Address is not aligned on a 16-bit boundary, then ASSERT().
421 @param Address Address that encodes the PCI Bus, Device, Function and
424 @return The read value from the PCI configuration register.
433 ASSERT_INVALID_PCI_ADDRESS (Address
);
434 return MmioRead16 (GetPciExpressBaseAddress () + Address
);
438 Writes a 16-bit PCI configuration register.
440 Writes the 16-bit PCI configuration register specified by Address with the
441 value specified by Value. Value is returned. This function must guarantee
442 that all PCI read and write operations are serialized.
444 If Address > 0x0FFFFFFF, then ASSERT().
445 If Address is not aligned on a 16-bit boundary, then ASSERT().
447 @param Address Address that encodes the PCI Bus, Device, Function and
449 @param Value The value to write.
451 @return The value written to the PCI configuration register.
461 ASSERT_INVALID_PCI_ADDRESS (Address
);
462 return MmioWrite16 (GetPciExpressBaseAddress () + Address
, Value
);
466 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
469 Reads the 16-bit PCI configuration register specified by Address, performs a
470 bitwise inclusive OR between the read result and the value specified by
471 OrData, and writes the result to the 16-bit PCI configuration register
472 specified by Address. The value written to the PCI configuration register is
473 returned. This function must guarantee that all PCI read and write operations
476 If Address > 0x0FFFFFFF, then ASSERT().
477 If Address is not aligned on a 16-bit boundary, then ASSERT().
479 @param Address Address that encodes the PCI Bus, Device, Function and
481 @param OrData The value to OR with the PCI configuration register.
483 @return The value written back to the PCI configuration register.
493 ASSERT_INVALID_PCI_ADDRESS (Address
);
494 return MmioOr16 (GetPciExpressBaseAddress () + Address
, OrData
);
498 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
501 Reads the 16-bit PCI configuration register specified by Address, performs a
502 bitwise AND between the read result and the value specified by AndData, and
503 writes the result to the 16-bit PCI configuration register specified by
504 Address. The value written to the PCI configuration register is returned.
505 This function must guarantee that all PCI read and write operations are
508 If Address > 0x0FFFFFFF, then ASSERT().
509 If Address is not aligned on a 16-bit boundary, then ASSERT().
511 @param Address Address that encodes the PCI Bus, Device, Function and
513 @param AndData The value to AND with the PCI configuration register.
515 @return The value written back to the PCI configuration register.
525 ASSERT_INVALID_PCI_ADDRESS (Address
);
526 return MmioAnd16 (GetPciExpressBaseAddress () + Address
, AndData
);
530 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
531 value, followed a bitwise inclusive OR with another 16-bit value.
533 Reads the 16-bit PCI configuration register specified by Address, performs a
534 bitwise AND between the read result and the value specified by AndData,
535 performs a bitwise inclusive OR between the result of the AND operation and
536 the value specified by OrData, and writes the result to the 16-bit PCI
537 configuration register specified by Address. The value written to the PCI
538 configuration register is returned. This function must guarantee that all PCI
539 read and write operations are serialized.
541 If Address > 0x0FFFFFFF, then ASSERT().
542 If Address is not aligned on a 16-bit boundary, then ASSERT().
544 @param Address Address that encodes the PCI Bus, Device, Function and
546 @param AndData The value to AND with the PCI configuration register.
547 @param OrData The value to OR with the result of the AND operation.
549 @return The value written back to the PCI configuration register.
554 PciExpressAndThenOr16 (
560 ASSERT_INVALID_PCI_ADDRESS (Address
);
561 return MmioAndThenOr16 (
562 GetPciExpressBaseAddress () + Address
,
569 Reads a bit field of a PCI configuration register.
571 Reads the bit field in a 16-bit PCI configuration register. The bit field is
572 specified by the StartBit and the EndBit. The value of the bit field is
575 If Address > 0x0FFFFFFF, then ASSERT().
576 If Address is not aligned on a 16-bit boundary, then ASSERT().
577 If StartBit is greater than 15, then ASSERT().
578 If EndBit is greater than 15, then ASSERT().
579 If EndBit is less than or equal to StartBit, then ASSERT().
581 @param Address PCI configuration register to read.
582 @param StartBit The ordinal of the least significant bit in the bit field.
584 @param EndBit The ordinal of the most significant bit in the bit field.
587 @return The value of the bit field read from the PCI configuration register.
592 PciExpressBitFieldRead16 (
598 ASSERT_INVALID_PCI_ADDRESS (Address
);
599 return MmioBitFieldRead16 (
600 GetPciExpressBaseAddress () + Address
,
607 Writes a bit field to a PCI configuration register.
609 Writes Value to the bit field of the PCI configuration register. The bit
610 field is specified by the StartBit and the EndBit. All other bits in the
611 destination PCI configuration register are preserved. The new value of the
612 16-bit register is returned.
614 If Address > 0x0FFFFFFF, then ASSERT().
615 If Address is not aligned on a 16-bit boundary, then ASSERT().
616 If StartBit is greater than 15, then ASSERT().
617 If EndBit is greater than 15, then ASSERT().
618 If EndBit is less than or equal to StartBit, then ASSERT().
620 @param Address PCI configuration register to write.
621 @param StartBit The ordinal of the least significant bit in the bit field.
623 @param EndBit The ordinal of the most significant bit in the bit field.
625 @param Value New value of the bit field.
627 @return The value written back to the PCI configuration register.
632 PciExpressBitFieldWrite16 (
639 ASSERT_INVALID_PCI_ADDRESS (Address
);
640 return MmioBitFieldWrite16 (
641 GetPciExpressBaseAddress () + Address
,
649 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
650 writes the result back to the bit field in the 16-bit port.
652 Reads the 16-bit PCI configuration register specified by Address, performs a
653 bitwise inclusive OR between the read result and the value specified by
654 OrData, and writes the result to the 16-bit PCI configuration register
655 specified by Address. The value written to the PCI configuration register is
656 returned. This function must guarantee that all PCI read and write operations
657 are serialized. Extra left bits in OrData are stripped.
659 If Address > 0x0FFFFFFF, then ASSERT().
660 If Address is not aligned on a 16-bit boundary, then ASSERT().
661 If StartBit is greater than 15, then ASSERT().
662 If EndBit is greater than 15, then ASSERT().
663 If EndBit is less than or equal to StartBit, then ASSERT().
665 @param Address PCI configuration register to write.
666 @param StartBit The ordinal of the least significant bit in the bit field.
668 @param EndBit The ordinal of the most significant bit in the bit field.
670 @param OrData The value to OR with the PCI configuration register.
672 @return The value written back to the PCI configuration register.
677 PciExpressBitFieldOr16 (
684 ASSERT_INVALID_PCI_ADDRESS (Address
);
685 return MmioBitFieldOr16 (
686 GetPciExpressBaseAddress () + Address
,
694 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
695 AND, and writes the result back to the bit field in the 16-bit register.
697 Reads the 16-bit PCI configuration register specified by Address, performs a
698 bitwise AND between the read result and the value specified by AndData, and
699 writes the result to the 16-bit PCI configuration register specified by
700 Address. The value written to the PCI configuration register is returned.
701 This function must guarantee that all PCI read and write operations are
702 serialized. Extra left bits in AndData are stripped.
704 If Address > 0x0FFFFFFF, then ASSERT().
705 If Address is not aligned on a 16-bit boundary, then ASSERT().
706 If StartBit is greater than 15, then ASSERT().
707 If EndBit is greater than 15, then ASSERT().
708 If EndBit is less than or equal to StartBit, then ASSERT().
710 @param Address PCI configuration register to write.
711 @param StartBit The ordinal of the least significant bit in the bit field.
713 @param EndBit The ordinal of the most significant bit in the bit field.
715 @param AndData The value to AND with the PCI configuration register.
717 @return The value written back to the PCI configuration register.
722 PciExpressBitFieldAnd16 (
729 ASSERT_INVALID_PCI_ADDRESS (Address
);
730 return MmioBitFieldAnd16 (
731 GetPciExpressBaseAddress () + Address
,
739 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
740 bitwise inclusive OR, and writes the result back to the bit field in the
743 Reads the 16-bit PCI configuration register specified by Address, performs a
744 bitwise AND followed by a bitwise inclusive OR between the read result and
745 the value specified by AndData, and writes the result to the 16-bit PCI
746 configuration register specified by Address. The value written to the PCI
747 configuration register is returned. This function must guarantee that all PCI
748 read and write operations are serialized. Extra left bits in both AndData and
751 If Address > 0x0FFFFFFF, then ASSERT().
752 If Address is not aligned on a 16-bit boundary, then ASSERT().
753 If StartBit is greater than 15, then ASSERT().
754 If EndBit is greater than 15, then ASSERT().
755 If EndBit is less than or equal to StartBit, then ASSERT().
757 @param Address PCI configuration register to write.
758 @param StartBit The ordinal of the least significant bit in the bit field.
760 @param EndBit The ordinal of the most significant bit in the bit field.
762 @param AndData The value to AND with the PCI configuration register.
763 @param OrData The value to OR with the result of the AND operation.
765 @return The value written back to the PCI configuration register.
770 PciExpressBitFieldAndThenOr16 (
778 ASSERT_INVALID_PCI_ADDRESS (Address
);
779 return MmioBitFieldAndThenOr16 (
780 GetPciExpressBaseAddress () + Address
,
789 Reads a 32-bit PCI configuration register.
791 Reads and returns the 32-bit PCI configuration register specified by Address.
792 This function must guarantee that all PCI read and write operations are
795 If Address > 0x0FFFFFFF, then ASSERT().
796 If Address is not aligned on a 32-bit boundary, then ASSERT().
798 @param Address Address that encodes the PCI Bus, Device, Function and
801 @return The read value from the PCI configuration register.
810 ASSERT_INVALID_PCI_ADDRESS (Address
);
811 return MmioRead32 (GetPciExpressBaseAddress () + Address
);
815 Writes a 32-bit PCI configuration register.
817 Writes the 32-bit PCI configuration register specified by Address with the
818 value specified by Value. Value is returned. This function must guarantee
819 that all PCI read and write operations are serialized.
821 If Address > 0x0FFFFFFF, then ASSERT().
822 If Address is not aligned on a 32-bit boundary, then ASSERT().
824 @param Address Address that encodes the PCI Bus, Device, Function and
826 @param Value The value to write.
828 @return The value written to the PCI configuration register.
838 ASSERT_INVALID_PCI_ADDRESS (Address
);
839 return MmioWrite32 (GetPciExpressBaseAddress () + Address
, Value
);
843 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
846 Reads the 32-bit PCI configuration register specified by Address, performs a
847 bitwise inclusive OR between the read result and the value specified by
848 OrData, and writes the result to the 32-bit PCI configuration register
849 specified by Address. The value written to the PCI configuration register is
850 returned. This function must guarantee that all PCI read and write operations
853 If Address > 0x0FFFFFFF, then ASSERT().
854 If Address is not aligned on a 32-bit boundary, then ASSERT().
856 @param Address Address that encodes the PCI Bus, Device, Function and
858 @param OrData The value to OR with the PCI configuration register.
860 @return The value written back to the PCI configuration register.
870 ASSERT_INVALID_PCI_ADDRESS (Address
);
871 return MmioOr32 (GetPciExpressBaseAddress () + Address
, OrData
);
875 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
878 Reads the 32-bit PCI configuration register specified by Address, performs a
879 bitwise AND between the read result and the value specified by AndData, and
880 writes the result to the 32-bit PCI configuration register specified by
881 Address. The value written to the PCI configuration register is returned.
882 This function must guarantee that all PCI read and write operations are
885 If Address > 0x0FFFFFFF, then ASSERT().
886 If Address is not aligned on a 32-bit boundary, then ASSERT().
888 @param Address Address that encodes the PCI Bus, Device, Function and
890 @param AndData The value to AND with the PCI configuration register.
892 @return The value written back to the PCI configuration register.
902 ASSERT_INVALID_PCI_ADDRESS (Address
);
903 return MmioAnd32 (GetPciExpressBaseAddress () + Address
, AndData
);
907 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
908 value, followed a bitwise inclusive OR with another 32-bit value.
910 Reads the 32-bit PCI configuration register specified by Address, performs a
911 bitwise AND between the read result and the value specified by AndData,
912 performs a bitwise inclusive OR between the result of the AND operation and
913 the value specified by OrData, and writes the result to the 32-bit PCI
914 configuration register specified by Address. The value written to the PCI
915 configuration register is returned. This function must guarantee that all PCI
916 read and write operations are serialized.
918 If Address > 0x0FFFFFFF, then ASSERT().
919 If Address is not aligned on a 32-bit boundary, then ASSERT().
921 @param Address Address that encodes the PCI Bus, Device, Function and
923 @param AndData The value to AND with the PCI configuration register.
924 @param OrData The value to OR with the result of the AND operation.
926 @return The value written back to the PCI configuration register.
931 PciExpressAndThenOr32 (
937 ASSERT_INVALID_PCI_ADDRESS (Address
);
938 return MmioAndThenOr32 (
939 GetPciExpressBaseAddress () + Address
,
946 Reads a bit field of a PCI configuration register.
948 Reads the bit field in a 32-bit PCI configuration register. The bit field is
949 specified by the StartBit and the EndBit. The value of the bit field is
952 If Address > 0x0FFFFFFF, then ASSERT().
953 If Address is not aligned on a 32-bit boundary, then ASSERT().
954 If StartBit is greater than 31, then ASSERT().
955 If EndBit is greater than 31, then ASSERT().
956 If EndBit is less than or equal to StartBit, then ASSERT().
958 @param Address PCI configuration register to read.
959 @param StartBit The ordinal of the least significant bit in the bit field.
961 @param EndBit The ordinal of the most significant bit in the bit field.
964 @return The value of the bit field read from the PCI configuration register.
969 PciExpressBitFieldRead32 (
975 ASSERT_INVALID_PCI_ADDRESS (Address
);
976 return MmioBitFieldRead32 (
977 GetPciExpressBaseAddress () + Address
,
984 Writes a bit field to a PCI configuration register.
986 Writes Value to the bit field of the PCI configuration register. The bit
987 field is specified by the StartBit and the EndBit. All other bits in the
988 destination PCI configuration register are preserved. The new value of the
989 32-bit register is returned.
991 If Address > 0x0FFFFFFF, then ASSERT().
992 If Address is not aligned on a 32-bit boundary, then ASSERT().
993 If StartBit is greater than 31, then ASSERT().
994 If EndBit is greater than 31, then ASSERT().
995 If EndBit is less than or equal to StartBit, then ASSERT().
997 @param Address PCI configuration register to write.
998 @param StartBit The ordinal of the least significant bit in the bit field.
1000 @param EndBit The ordinal of the most significant bit in the bit field.
1002 @param Value New value of the bit field.
1004 @return The value written back to the PCI configuration register.
1009 PciExpressBitFieldWrite32 (
1016 ASSERT_INVALID_PCI_ADDRESS (Address
);
1017 return MmioBitFieldWrite32 (
1018 GetPciExpressBaseAddress () + Address
,
1026 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1027 writes the result back to the bit field in the 32-bit port.
1029 Reads the 32-bit PCI configuration register specified by Address, performs a
1030 bitwise inclusive OR between the read result and the value specified by
1031 OrData, and writes the result to the 32-bit PCI configuration register
1032 specified by Address. The value written to the PCI configuration register is
1033 returned. This function must guarantee that all PCI read and write operations
1034 are serialized. Extra left bits in OrData are stripped.
1036 If Address > 0x0FFFFFFF, then ASSERT().
1037 If Address is not aligned on a 32-bit boundary, then ASSERT().
1038 If StartBit is greater than 31, then ASSERT().
1039 If EndBit is greater than 31, then ASSERT().
1040 If EndBit is less than or equal to StartBit, then ASSERT().
1042 @param Address PCI configuration register to write.
1043 @param StartBit The ordinal of the least significant bit in the bit field.
1045 @param EndBit The ordinal of the most significant bit in the bit field.
1047 @param OrData The value to OR with the PCI configuration register.
1049 @return The value written back to the PCI configuration register.
1054 PciExpressBitFieldOr32 (
1061 ASSERT_INVALID_PCI_ADDRESS (Address
);
1062 return MmioBitFieldOr32 (
1063 GetPciExpressBaseAddress () + Address
,
1071 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1072 AND, and writes the result back to the bit field in the 32-bit register.
1074 Reads the 32-bit PCI configuration register specified by Address, performs a
1075 bitwise AND between the read result and the value specified by AndData, and
1076 writes the result to the 32-bit PCI configuration register specified by
1077 Address. The value written to the PCI configuration register is returned.
1078 This function must guarantee that all PCI read and write operations are
1079 serialized. Extra left bits in AndData are stripped.
1081 If Address > 0x0FFFFFFF, then ASSERT().
1082 If Address is not aligned on a 32-bit boundary, then ASSERT().
1083 If StartBit is greater than 31, then ASSERT().
1084 If EndBit is greater than 31, then ASSERT().
1085 If EndBit is less than or equal to StartBit, then ASSERT().
1087 @param Address PCI configuration register to write.
1088 @param StartBit The ordinal of the least significant bit in the bit field.
1090 @param EndBit The ordinal of the most significant bit in the bit field.
1092 @param AndData The value to AND with the PCI configuration register.
1094 @return The value written back to the PCI configuration register.
1099 PciExpressBitFieldAnd32 (
1106 ASSERT_INVALID_PCI_ADDRESS (Address
);
1107 return MmioBitFieldAnd32 (
1108 GetPciExpressBaseAddress () + Address
,
1116 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1117 bitwise inclusive OR, and writes the result back to the bit field in the
1120 Reads the 32-bit PCI configuration register specified by Address, performs a
1121 bitwise AND followed by a bitwise inclusive OR between the read result and
1122 the value specified by AndData, and writes the result to the 32-bit PCI
1123 configuration register specified by Address. The value written to the PCI
1124 configuration register is returned. This function must guarantee that all PCI
1125 read and write operations are serialized. Extra left bits in both AndData and
1126 OrData are stripped.
1128 If Address > 0x0FFFFFFF, then ASSERT().
1129 If Address is not aligned on a 32-bit boundary, then ASSERT().
1130 If StartBit is greater than 31, then ASSERT().
1131 If EndBit is greater than 31, then ASSERT().
1132 If EndBit is less than or equal to StartBit, then ASSERT().
1134 @param Address PCI configuration register to write.
1135 @param StartBit The ordinal of the least significant bit in the bit field.
1137 @param EndBit The ordinal of the most significant bit in the bit field.
1139 @param AndData The value to AND with the PCI configuration register.
1140 @param OrData The value to OR with the result of the AND operation.
1142 @return The value written back to the PCI configuration register.
1147 PciExpressBitFieldAndThenOr32 (
1155 ASSERT_INVALID_PCI_ADDRESS (Address
);
1156 return MmioBitFieldAndThenOr32 (
1157 GetPciExpressBaseAddress () + Address
,
1166 Reads a range of PCI configuration registers into a caller supplied buffer.
1168 Reads the range of PCI configuration registers specified by StartAddress and
1169 Size into the buffer specified by Buffer. This function only allows the PCI
1170 configuration registers from a single PCI function to be read. Size is
1171 returned. When possible 32-bit PCI configuration read cycles are used to read
1172 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1173 and 16-bit PCI configuration read cycles may be used at the beginning and the
1176 If StartAddress > 0x0FFFFFFF, then ASSERT().
1177 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1178 If (StartAddress + Size - 1) > 0x0FFFFFFF, then ASSERT().
1179 If Buffer is NULL, then ASSERT().
1181 @param StartAddress Starting address that encodes the PCI Bus, Device,
1182 Function and Register.
1183 @param Size Size in bytes of the transfer.
1184 @param Buffer Pointer to a buffer receiving the data read.
1191 PciExpressReadBuffer (
1192 IN UINTN StartAddress
,
1199 EndAddress
= StartAddress
+ Size
;
1201 if (StartAddress
< EndAddress
&& (StartAddress
& 1)) {
1203 // Read a byte if StartAddress is byte aligned
1205 *(UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1206 StartAddress
+= sizeof (UINT8
);
1207 Buffer
= (UINT8
*)Buffer
+ 1;
1210 if (StartAddress
< EndAddress
&& (StartAddress
& 2)) {
1212 // Read a word if StartAddress is word aligned
1214 *(UINT16
*)Buffer
= PciExpressRead16 (StartAddress
);
1215 StartAddress
+= sizeof (UINT16
);
1216 Buffer
= (UINT16
*)Buffer
+ 1;
1219 while (EndAddress
- StartAddress
>= 4) {
1221 // Read as many double words as possible
1223 *(UINT32
*)Buffer
= PciExpressRead32 (StartAddress
);
1224 StartAddress
+= sizeof (UINT32
);
1225 Buffer
= (UINT32
*)Buffer
+ 1;
1228 if ((EndAddress
& 2) != 0) {
1230 // Read the last remaining word if exist
1232 *(UINT16
*)Buffer
= PciExpressRead16 (StartAddress
);
1233 StartAddress
+= sizeof (UINT16
);
1234 Buffer
= (UINT16
*)Buffer
+ 1;
1237 if (EndAddress
& 1) {
1239 // Read the last remaining byte if exist
1241 *(UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1248 Copies the data in a caller supplied buffer to a specified range of PCI
1249 configuration space.
1251 Writes the range of PCI configuration registers specified by StartAddress and
1252 Size from the buffer specified by Buffer. This function only allows the PCI
1253 configuration registers from a single PCI function to be written. Size is
1254 returned. When possible 32-bit PCI configuration write cycles are used to
1255 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1256 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1257 and the end of the range.
1259 If StartAddress > 0x0FFFFFFF, then ASSERT().
1260 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1261 If (StartAddress + Size - 1) > 0x0FFFFFFF, then ASSERT().
1262 If Buffer is NULL, then ASSERT().
1264 @param StartAddress Starting address that encodes the PCI Bus, Device,
1265 Function and Register.
1266 @param Size Size in bytes of the transfer.
1267 @param Buffer Pointer to a buffer containing the data to write.
1274 PciExpressWriteBuffer (
1275 IN UINTN StartAddress
,
1282 EndAddress
= StartAddress
+ Size
;
1284 if ((StartAddress
< EndAddress
) && ((StartAddress
& 1)!= 0)) {
1286 // Write a byte if StartAddress is byte aligned
1288 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1289 StartAddress
+= sizeof (UINT8
);
1290 Buffer
= (UINT8
*)Buffer
+ 1;
1293 if (StartAddress
< EndAddress
&& (StartAddress
& 2)) {
1295 // Write a word if StartAddress is word aligned
1297 PciExpressWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1298 StartAddress
+= sizeof (UINT16
);
1299 Buffer
= (UINT16
*)Buffer
+ 1;
1302 while (EndAddress
- StartAddress
>= 4) {
1304 // Write as many double words as possible
1306 PciExpressWrite32 (StartAddress
, *(UINT32
*)Buffer
);
1307 StartAddress
+= sizeof (UINT32
);
1308 Buffer
= (UINT32
*)Buffer
+ 1;
1311 if (EndAddress
& 2) {
1313 // Write the last remaining word if exist
1315 PciExpressWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1316 StartAddress
+= sizeof (UINT16
);
1317 Buffer
= (UINT16
*)Buffer
+ 1;
1320 if (EndAddress
& 1) {
1322 // Write the last remaining byte if exist
1324 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);