]>
git.proxmox.com Git - mirror_edk2.git/blob - MdePkg/Library/BasePciExpressLib/PciLib.c
4 Functions in this library instance make use of MMIO functions in IoLib to
5 access memory mapped PCI configuration space.
7 All assertions for I/O operations are handled in MMIO functions in the IoLib
10 Copyright (c) 2006, Intel Corporation<BR>
11 All rights reserved. This program and the accompanying materials
12 are licensed and made available under the terms and conditions of the BSD License
13 which accompanies this distribution. The full text of the license may be found at
14 http://opensource.org/licenses/bsd-license.php
16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
17 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
24 Assert the validity of a PCI address. A valid PCI address should contain 1's
25 only in the low 28 bits.
27 @param A The address to validate.
30 #define ASSERT_INVALID_PCI_ADDRESS(A) \
31 ASSERT (((A) & ~0xfffffff) == 0)
35 Gets the base address of PCI Express.
37 This internal functions retrieves PCI Express Base Address via a PCD entry
38 PcdPciExpressBaseAddress.
40 @return The base address of PCI Express.
44 GetPciExpressBaseAddress (
48 return (VOID
*)(UINTN
) PcdGet64 (PcdPciExpressBaseAddress
);
52 Reads an 8-bit PCI configuration register.
54 Reads and returns the 8-bit PCI configuration register specified by Address.
55 This function must guarantee that all PCI read and write operations are
58 If Address > 0x0FFFFFFF, then ASSERT().
60 @param Address Address that encodes the PCI Bus, Device, Function and
63 @return The read value from the PCI configuration register.
72 ASSERT_INVALID_PCI_ADDRESS (Address
);
73 return MmioRead8 ((UINTN
) GetPciExpressBaseAddress () + Address
);
77 Writes an 8-bit PCI configuration register.
79 Writes the 8-bit PCI configuration register specified by Address with the
80 value specified by Value. Value is returned. This function must guarantee
81 that all PCI read and write operations are serialized.
83 If Address > 0x0FFFFFFF, then ASSERT().
85 @param Address Address that encodes the PCI Bus, Device, Function and
87 @param Value The value to write.
89 @return The value written to the PCI configuration register.
99 ASSERT_INVALID_PCI_ADDRESS (Address
);
100 return MmioWrite8 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
104 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
107 Reads the 8-bit PCI configuration register specified by Address, performs a
108 bitwise inclusive OR between the read result and the value specified by
109 OrData, and writes the result to the 8-bit PCI configuration register
110 specified by Address. The value written to the PCI configuration register is
111 returned. This function must guarantee that all PCI read and write operations
114 If Address > 0x0FFFFFFF, then ASSERT().
116 @param Address Address that encodes the PCI Bus, Device, Function and
118 @param OrData The value to OR with the PCI configuration register.
120 @return The value written back to the PCI configuration register.
130 ASSERT_INVALID_PCI_ADDRESS (Address
);
131 return MmioOr8 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
135 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
138 Reads the 8-bit PCI configuration register specified by Address, performs a
139 bitwise AND between the read result and the value specified by AndData, and
140 writes the result to the 8-bit PCI configuration register specified by
141 Address. The value written to the PCI configuration register is returned.
142 This function must guarantee that all PCI read and write operations are
145 If Address > 0x0FFFFFFF, then ASSERT().
147 @param Address Address that encodes the PCI Bus, Device, Function and
149 @param AndData The value to AND with the PCI configuration register.
151 @return The value written back to the PCI configuration register.
161 ASSERT_INVALID_PCI_ADDRESS (Address
);
162 return MmioAnd8 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
166 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
167 value, followed a bitwise inclusive OR with another 8-bit value.
169 Reads the 8-bit PCI configuration register specified by Address, performs a
170 bitwise AND between the read result and the value specified by AndData,
171 performs a bitwise inclusive OR between the result of the AND operation and
172 the value specified by OrData, and writes the result to the 8-bit PCI
173 configuration register specified by Address. The value written to the PCI
174 configuration register is returned. This function must guarantee that all PCI
175 read and write operations are serialized.
177 If Address > 0x0FFFFFFF, then ASSERT().
179 @param Address Address that encodes the PCI Bus, Device, Function and
181 @param AndData The value to AND with the PCI configuration register.
182 @param OrData The value to OR with the result of the AND operation.
184 @return The value written back to the PCI configuration register.
189 PciExpressAndThenOr8 (
195 ASSERT_INVALID_PCI_ADDRESS (Address
);
196 return MmioAndThenOr8 (
197 (UINTN
) GetPciExpressBaseAddress () + Address
,
204 Reads a bit field of a PCI configuration register.
206 Reads the bit field in an 8-bit PCI configuration register. The bit field is
207 specified by the StartBit and the EndBit. The value of the bit field is
210 If Address > 0x0FFFFFFF, then ASSERT().
211 If StartBit is greater than 7, then ASSERT().
212 If EndBit is greater than 7, then ASSERT().
213 If EndBit is less than StartBit, then ASSERT().
215 @param Address PCI configuration register to read.
216 @param StartBit The ordinal of the least significant bit in the bit field.
218 @param EndBit The ordinal of the most significant bit in the bit field.
221 @return The value of the bit field read from the PCI configuration register.
226 PciExpressBitFieldRead8 (
232 ASSERT_INVALID_PCI_ADDRESS (Address
);
233 return MmioBitFieldRead8 (
234 (UINTN
) GetPciExpressBaseAddress () + Address
,
241 Writes a bit field to a PCI configuration register.
243 Writes Value to the bit field of the PCI configuration register. The bit
244 field is specified by the StartBit and the EndBit. All other bits in the
245 destination PCI configuration register are preserved. The new value of the
246 8-bit register is returned.
248 If Address > 0x0FFFFFFF, then ASSERT().
249 If StartBit is greater than 7, then ASSERT().
250 If EndBit is greater than 7, then ASSERT().
251 If EndBit is less than StartBit, then ASSERT().
253 @param Address PCI configuration register to write.
254 @param StartBit The ordinal of the least significant bit in the bit field.
256 @param EndBit The ordinal of the most significant bit in the bit field.
258 @param Value New value of the bit field.
260 @return The value written back to the PCI configuration register.
265 PciExpressBitFieldWrite8 (
272 ASSERT_INVALID_PCI_ADDRESS (Address
);
273 return MmioBitFieldWrite8 (
274 (UINTN
) GetPciExpressBaseAddress () + Address
,
282 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
283 writes the result back to the bit field in the 8-bit port.
285 Reads the 8-bit PCI configuration register specified by Address, performs a
286 bitwise inclusive OR between the read result and the value specified by
287 OrData, and writes the result to the 8-bit PCI configuration register
288 specified by Address. The value written to the PCI configuration register is
289 returned. This function must guarantee that all PCI read and write operations
290 are serialized. Extra left bits in OrData are stripped.
292 If Address > 0x0FFFFFFF, then ASSERT().
293 If StartBit is greater than 7, then ASSERT().
294 If EndBit is greater than 7, then ASSERT().
295 If EndBit is less than StartBit, then ASSERT().
297 @param Address PCI configuration register to write.
298 @param StartBit The ordinal of the least significant bit in the bit field.
300 @param EndBit The ordinal of the most significant bit in the bit field.
302 @param OrData The value to OR with the PCI configuration register.
304 @return The value written back to the PCI configuration register.
309 PciExpressBitFieldOr8 (
316 ASSERT_INVALID_PCI_ADDRESS (Address
);
317 return MmioBitFieldOr8 (
318 (UINTN
) GetPciExpressBaseAddress () + Address
,
326 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
327 AND, and writes the result back to the bit field in the 8-bit register.
329 Reads the 8-bit PCI configuration register specified by Address, performs a
330 bitwise AND between the read result and the value specified by AndData, and
331 writes the result to the 8-bit PCI configuration register specified by
332 Address. The value written to the PCI configuration register is returned.
333 This function must guarantee that all PCI read and write operations are
334 serialized. Extra left bits in AndData are stripped.
336 If Address > 0x0FFFFFFF, then ASSERT().
337 If StartBit is greater than 7, then ASSERT().
338 If EndBit is greater than 7, then ASSERT().
339 If EndBit is less than StartBit, then ASSERT().
341 @param Address PCI configuration register to write.
342 @param StartBit The ordinal of the least significant bit in the bit field.
344 @param EndBit The ordinal of the most significant bit in the bit field.
346 @param AndData The value to AND with the PCI configuration register.
348 @return The value written back to the PCI configuration register.
353 PciExpressBitFieldAnd8 (
360 ASSERT_INVALID_PCI_ADDRESS (Address
);
361 return MmioBitFieldAnd8 (
362 (UINTN
) GetPciExpressBaseAddress () + Address
,
370 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
371 bitwise inclusive OR, and writes the result back to the bit field in the
374 Reads the 8-bit PCI configuration register specified by Address, performs a
375 bitwise AND followed by a bitwise inclusive OR between the read result and
376 the value specified by AndData, and writes the result to the 8-bit PCI
377 configuration register specified by Address. The value written to the PCI
378 configuration register is returned. This function must guarantee that all PCI
379 read and write operations are serialized. Extra left bits in both AndData and
382 If Address > 0x0FFFFFFF, then ASSERT().
383 If StartBit is greater than 7, then ASSERT().
384 If EndBit is greater than 7, then ASSERT().
385 If EndBit is less than StartBit, then ASSERT().
387 @param Address PCI configuration register to write.
388 @param StartBit The ordinal of the least significant bit in the bit field.
390 @param EndBit The ordinal of the most significant bit in the bit field.
392 @param AndData The value to AND with the PCI configuration register.
393 @param OrData The value to OR with the result of the AND operation.
395 @return The value written back to the PCI configuration register.
400 PciExpressBitFieldAndThenOr8 (
408 ASSERT_INVALID_PCI_ADDRESS (Address
);
409 return MmioBitFieldAndThenOr8 (
410 (UINTN
) GetPciExpressBaseAddress () + Address
,
419 Reads a 16-bit PCI configuration register.
421 Reads and returns the 16-bit PCI configuration register specified by Address.
422 This function must guarantee that all PCI read and write operations are
425 If Address > 0x0FFFFFFF, then ASSERT().
426 If Address is not aligned on a 16-bit boundary, then ASSERT().
428 @param Address Address that encodes the PCI Bus, Device, Function and
431 @return The read value from the PCI configuration register.
440 ASSERT_INVALID_PCI_ADDRESS (Address
);
441 return MmioRead16 ((UINTN
) GetPciExpressBaseAddress () + Address
);
445 Writes a 16-bit PCI configuration register.
447 Writes the 16-bit PCI configuration register specified by Address with the
448 value specified by Value. Value is returned. This function must guarantee
449 that all PCI read and write operations are serialized.
451 If Address > 0x0FFFFFFF, then ASSERT().
452 If Address is not aligned on a 16-bit boundary, then ASSERT().
454 @param Address Address that encodes the PCI Bus, Device, Function and
456 @param Value The value to write.
458 @return The value written to the PCI configuration register.
468 ASSERT_INVALID_PCI_ADDRESS (Address
);
469 return MmioWrite16 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
473 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
476 Reads the 16-bit PCI configuration register specified by Address, performs a
477 bitwise inclusive OR between the read result and the value specified by
478 OrData, and writes the result to the 16-bit PCI configuration register
479 specified by Address. The value written to the PCI configuration register is
480 returned. This function must guarantee that all PCI read and write operations
483 If Address > 0x0FFFFFFF, then ASSERT().
484 If Address is not aligned on a 16-bit boundary, then ASSERT().
486 @param Address Address that encodes the PCI Bus, Device, Function and
488 @param OrData The value to OR with the PCI configuration register.
490 @return The value written back to the PCI configuration register.
500 ASSERT_INVALID_PCI_ADDRESS (Address
);
501 return MmioOr16 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
505 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
508 Reads the 16-bit PCI configuration register specified by Address, performs a
509 bitwise AND between the read result and the value specified by AndData, and
510 writes the result to the 16-bit PCI configuration register specified by
511 Address. The value written to the PCI configuration register is returned.
512 This function must guarantee that all PCI read and write operations are
515 If Address > 0x0FFFFFFF, then ASSERT().
516 If Address is not aligned on a 16-bit boundary, then ASSERT().
518 @param Address Address that encodes the PCI Bus, Device, Function and
520 @param AndData The value to AND with the PCI configuration register.
522 @return The value written back to the PCI configuration register.
532 ASSERT_INVALID_PCI_ADDRESS (Address
);
533 return MmioAnd16 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
537 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
538 value, followed a bitwise inclusive OR with another 16-bit value.
540 Reads the 16-bit PCI configuration register specified by Address, performs a
541 bitwise AND between the read result and the value specified by AndData,
542 performs a bitwise inclusive OR between the result of the AND operation and
543 the value specified by OrData, and writes the result to the 16-bit PCI
544 configuration register specified by Address. The value written to the PCI
545 configuration register is returned. This function must guarantee that all PCI
546 read and write operations are serialized.
548 If Address > 0x0FFFFFFF, then ASSERT().
549 If Address is not aligned on a 16-bit boundary, then ASSERT().
551 @param Address Address that encodes the PCI Bus, Device, Function and
553 @param AndData The value to AND with the PCI configuration register.
554 @param OrData The value to OR with the result of the AND operation.
556 @return The value written back to the PCI configuration register.
561 PciExpressAndThenOr16 (
567 ASSERT_INVALID_PCI_ADDRESS (Address
);
568 return MmioAndThenOr16 (
569 (UINTN
) GetPciExpressBaseAddress () + Address
,
576 Reads a bit field of a PCI configuration register.
578 Reads the bit field in a 16-bit PCI configuration register. The bit field is
579 specified by the StartBit and the EndBit. The value of the bit field is
582 If Address > 0x0FFFFFFF, then ASSERT().
583 If Address is not aligned on a 16-bit boundary, then ASSERT().
584 If StartBit is greater than 15, then ASSERT().
585 If EndBit is greater than 15, then ASSERT().
586 If EndBit is less than StartBit, then ASSERT().
588 @param Address PCI configuration register to read.
589 @param StartBit The ordinal of the least significant bit in the bit field.
591 @param EndBit The ordinal of the most significant bit in the bit field.
594 @return The value of the bit field read from the PCI configuration register.
599 PciExpressBitFieldRead16 (
605 ASSERT_INVALID_PCI_ADDRESS (Address
);
606 return MmioBitFieldRead16 (
607 (UINTN
) GetPciExpressBaseAddress () + Address
,
614 Writes a bit field to a PCI configuration register.
616 Writes Value to the bit field of the PCI configuration register. The bit
617 field is specified by the StartBit and the EndBit. All other bits in the
618 destination PCI configuration register are preserved. The new value of the
619 16-bit register is returned.
621 If Address > 0x0FFFFFFF, then ASSERT().
622 If Address is not aligned on a 16-bit boundary, then ASSERT().
623 If StartBit is greater than 15, then ASSERT().
624 If EndBit is greater than 15, then ASSERT().
625 If EndBit is less than StartBit, then ASSERT().
627 @param Address PCI configuration register to write.
628 @param StartBit The ordinal of the least significant bit in the bit field.
630 @param EndBit The ordinal of the most significant bit in the bit field.
632 @param Value New value of the bit field.
634 @return The value written back to the PCI configuration register.
639 PciExpressBitFieldWrite16 (
646 ASSERT_INVALID_PCI_ADDRESS (Address
);
647 return MmioBitFieldWrite16 (
648 (UINTN
) GetPciExpressBaseAddress () + Address
,
656 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
657 writes the result back to the bit field in the 16-bit port.
659 Reads the 16-bit PCI configuration register specified by Address, performs a
660 bitwise inclusive OR between the read result and the value specified by
661 OrData, and writes the result to the 16-bit PCI configuration register
662 specified by Address. The value written to the PCI configuration register is
663 returned. This function must guarantee that all PCI read and write operations
664 are serialized. Extra left bits in OrData are stripped.
666 If Address > 0x0FFFFFFF, then ASSERT().
667 If Address is not aligned on a 16-bit boundary, then ASSERT().
668 If StartBit is greater than 15, then ASSERT().
669 If EndBit is greater than 15, then ASSERT().
670 If EndBit is less than StartBit, then ASSERT().
672 @param Address PCI configuration register to write.
673 @param StartBit The ordinal of the least significant bit in the bit field.
675 @param EndBit The ordinal of the most significant bit in the bit field.
677 @param OrData The value to OR with the PCI configuration register.
679 @return The value written back to the PCI configuration register.
684 PciExpressBitFieldOr16 (
691 ASSERT_INVALID_PCI_ADDRESS (Address
);
692 return MmioBitFieldOr16 (
693 (UINTN
) GetPciExpressBaseAddress () + Address
,
701 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
702 AND, and writes the result back to the bit field in the 16-bit register.
704 Reads the 16-bit PCI configuration register specified by Address, performs a
705 bitwise AND between the read result and the value specified by AndData, and
706 writes the result to the 16-bit PCI configuration register specified by
707 Address. The value written to the PCI configuration register is returned.
708 This function must guarantee that all PCI read and write operations are
709 serialized. Extra left bits in AndData are stripped.
711 If Address > 0x0FFFFFFF, then ASSERT().
712 If Address is not aligned on a 16-bit boundary, then ASSERT().
713 If StartBit is greater than 15, then ASSERT().
714 If EndBit is greater than 15, then ASSERT().
715 If EndBit is less than StartBit, then ASSERT().
717 @param Address PCI configuration register to write.
718 @param StartBit The ordinal of the least significant bit in the bit field.
720 @param EndBit The ordinal of the most significant bit in the bit field.
722 @param AndData The value to AND with the PCI configuration register.
724 @return The value written back to the PCI configuration register.
729 PciExpressBitFieldAnd16 (
736 ASSERT_INVALID_PCI_ADDRESS (Address
);
737 return MmioBitFieldAnd16 (
738 (UINTN
) GetPciExpressBaseAddress () + Address
,
746 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
747 bitwise inclusive OR, and writes the result back to the bit field in the
750 Reads the 16-bit PCI configuration register specified by Address, performs a
751 bitwise AND followed by a bitwise inclusive OR between the read result and
752 the value specified by AndData, and writes the result to the 16-bit PCI
753 configuration register specified by Address. The value written to the PCI
754 configuration register is returned. This function must guarantee that all PCI
755 read and write operations are serialized. Extra left bits in both AndData and
758 If Address > 0x0FFFFFFF, then ASSERT().
759 If Address is not aligned on a 16-bit boundary, then ASSERT().
760 If StartBit is greater than 15, then ASSERT().
761 If EndBit is greater than 15, then ASSERT().
762 If EndBit is less than StartBit, then ASSERT().
764 @param Address PCI configuration register to write.
765 @param StartBit The ordinal of the least significant bit in the bit field.
767 @param EndBit The ordinal of the most significant bit in the bit field.
769 @param AndData The value to AND with the PCI configuration register.
770 @param OrData The value to OR with the result of the AND operation.
772 @return The value written back to the PCI configuration register.
777 PciExpressBitFieldAndThenOr16 (
785 ASSERT_INVALID_PCI_ADDRESS (Address
);
786 return MmioBitFieldAndThenOr16 (
787 (UINTN
) GetPciExpressBaseAddress () + Address
,
796 Reads a 32-bit PCI configuration register.
798 Reads and returns the 32-bit PCI configuration register specified by Address.
799 This function must guarantee that all PCI read and write operations are
802 If Address > 0x0FFFFFFF, then ASSERT().
803 If Address is not aligned on a 32-bit boundary, then ASSERT().
805 @param Address Address that encodes the PCI Bus, Device, Function and
808 @return The read value from the PCI configuration register.
817 ASSERT_INVALID_PCI_ADDRESS (Address
);
818 return MmioRead32 ((UINTN
) GetPciExpressBaseAddress () + Address
);
822 Writes a 32-bit PCI configuration register.
824 Writes the 32-bit PCI configuration register specified by Address with the
825 value specified by Value. Value is returned. This function must guarantee
826 that all PCI read and write operations are serialized.
828 If Address > 0x0FFFFFFF, then ASSERT().
829 If Address is not aligned on a 32-bit boundary, then ASSERT().
831 @param Address Address that encodes the PCI Bus, Device, Function and
833 @param Value The value to write.
835 @return The value written to the PCI configuration register.
845 ASSERT_INVALID_PCI_ADDRESS (Address
);
846 return MmioWrite32 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
850 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
853 Reads the 32-bit PCI configuration register specified by Address, performs a
854 bitwise inclusive OR between the read result and the value specified by
855 OrData, and writes the result to the 32-bit PCI configuration register
856 specified by Address. The value written to the PCI configuration register is
857 returned. This function must guarantee that all PCI read and write operations
860 If Address > 0x0FFFFFFF, then ASSERT().
861 If Address is not aligned on a 32-bit boundary, then ASSERT().
863 @param Address Address that encodes the PCI Bus, Device, Function and
865 @param OrData The value to OR with the PCI configuration register.
867 @return The value written back to the PCI configuration register.
877 ASSERT_INVALID_PCI_ADDRESS (Address
);
878 return MmioOr32 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
882 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
885 Reads the 32-bit PCI configuration register specified by Address, performs a
886 bitwise AND between the read result and the value specified by AndData, and
887 writes the result to the 32-bit PCI configuration register specified by
888 Address. The value written to the PCI configuration register is returned.
889 This function must guarantee that all PCI read and write operations are
892 If Address > 0x0FFFFFFF, then ASSERT().
893 If Address is not aligned on a 32-bit boundary, then ASSERT().
895 @param Address Address that encodes the PCI Bus, Device, Function and
897 @param AndData The value to AND with the PCI configuration register.
899 @return The value written back to the PCI configuration register.
909 ASSERT_INVALID_PCI_ADDRESS (Address
);
910 return MmioAnd32 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
914 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
915 value, followed a bitwise inclusive OR with another 32-bit value.
917 Reads the 32-bit PCI configuration register specified by Address, performs a
918 bitwise AND between the read result and the value specified by AndData,
919 performs a bitwise inclusive OR between the result of the AND operation and
920 the value specified by OrData, and writes the result to the 32-bit PCI
921 configuration register specified by Address. The value written to the PCI
922 configuration register is returned. This function must guarantee that all PCI
923 read and write operations are serialized.
925 If Address > 0x0FFFFFFF, then ASSERT().
926 If Address is not aligned on a 32-bit boundary, then ASSERT().
928 @param Address Address that encodes the PCI Bus, Device, Function and
930 @param AndData The value to AND with the PCI configuration register.
931 @param OrData The value to OR with the result of the AND operation.
933 @return The value written back to the PCI configuration register.
938 PciExpressAndThenOr32 (
944 ASSERT_INVALID_PCI_ADDRESS (Address
);
945 return MmioAndThenOr32 (
946 (UINTN
) GetPciExpressBaseAddress () + Address
,
953 Reads a bit field of a PCI configuration register.
955 Reads the bit field in a 32-bit PCI configuration register. The bit field is
956 specified by the StartBit and the EndBit. The value of the bit field is
959 If Address > 0x0FFFFFFF, then ASSERT().
960 If Address is not aligned on a 32-bit boundary, then ASSERT().
961 If StartBit is greater than 31, then ASSERT().
962 If EndBit is greater than 31, then ASSERT().
963 If EndBit is less than StartBit, then ASSERT().
965 @param Address PCI configuration register to read.
966 @param StartBit The ordinal of the least significant bit in the bit field.
968 @param EndBit The ordinal of the most significant bit in the bit field.
971 @return The value of the bit field read from the PCI configuration register.
976 PciExpressBitFieldRead32 (
982 ASSERT_INVALID_PCI_ADDRESS (Address
);
983 return MmioBitFieldRead32 (
984 (UINTN
) GetPciExpressBaseAddress () + Address
,
991 Writes a bit field to a PCI configuration register.
993 Writes Value to the bit field of the PCI configuration register. The bit
994 field is specified by the StartBit and the EndBit. All other bits in the
995 destination PCI configuration register are preserved. The new value of the
996 32-bit register is returned.
998 If Address > 0x0FFFFFFF, then ASSERT().
999 If Address is not aligned on a 32-bit boundary, then ASSERT().
1000 If StartBit is greater than 31, then ASSERT().
1001 If EndBit is greater than 31, then ASSERT().
1002 If EndBit is less than StartBit, then ASSERT().
1004 @param Address PCI configuration register to write.
1005 @param StartBit The ordinal of the least significant bit in the bit field.
1007 @param EndBit The ordinal of the most significant bit in the bit field.
1009 @param Value New value of the bit field.
1011 @return The value written back to the PCI configuration register.
1016 PciExpressBitFieldWrite32 (
1023 ASSERT_INVALID_PCI_ADDRESS (Address
);
1024 return MmioBitFieldWrite32 (
1025 (UINTN
) GetPciExpressBaseAddress () + Address
,
1033 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1034 writes the result back to the bit field in the 32-bit port.
1036 Reads the 32-bit PCI configuration register specified by Address, performs a
1037 bitwise inclusive OR between the read result and the value specified by
1038 OrData, and writes the result to the 32-bit PCI configuration register
1039 specified by Address. The value written to the PCI configuration register is
1040 returned. This function must guarantee that all PCI read and write operations
1041 are serialized. Extra left bits in OrData are stripped.
1043 If Address > 0x0FFFFFFF, then ASSERT().
1044 If Address is not aligned on a 32-bit boundary, then ASSERT().
1045 If StartBit is greater than 31, then ASSERT().
1046 If EndBit is greater than 31, then ASSERT().
1047 If EndBit is less than StartBit, then ASSERT().
1049 @param Address PCI configuration register to write.
1050 @param StartBit The ordinal of the least significant bit in the bit field.
1052 @param EndBit The ordinal of the most significant bit in the bit field.
1054 @param OrData The value to OR with the PCI configuration register.
1056 @return The value written back to the PCI configuration register.
1061 PciExpressBitFieldOr32 (
1068 ASSERT_INVALID_PCI_ADDRESS (Address
);
1069 return MmioBitFieldOr32 (
1070 (UINTN
) GetPciExpressBaseAddress () + Address
,
1078 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1079 AND, and writes the result back to the bit field in the 32-bit register.
1081 Reads the 32-bit PCI configuration register specified by Address, performs a
1082 bitwise AND between the read result and the value specified by AndData, and
1083 writes the result to the 32-bit PCI configuration register specified by
1084 Address. The value written to the PCI configuration register is returned.
1085 This function must guarantee that all PCI read and write operations are
1086 serialized. Extra left bits in AndData are stripped.
1088 If Address > 0x0FFFFFFF, then ASSERT().
1089 If Address is not aligned on a 32-bit boundary, then ASSERT().
1090 If StartBit is greater than 31, then ASSERT().
1091 If EndBit is greater than 31, then ASSERT().
1092 If EndBit is less than StartBit, then ASSERT().
1094 @param Address PCI configuration register to write.
1095 @param StartBit The ordinal of the least significant bit in the bit field.
1097 @param EndBit The ordinal of the most significant bit in the bit field.
1099 @param AndData The value to AND with the PCI configuration register.
1101 @return The value written back to the PCI configuration register.
1106 PciExpressBitFieldAnd32 (
1113 ASSERT_INVALID_PCI_ADDRESS (Address
);
1114 return MmioBitFieldAnd32 (
1115 (UINTN
) GetPciExpressBaseAddress () + Address
,
1123 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1124 bitwise inclusive OR, and writes the result back to the bit field in the
1127 Reads the 32-bit PCI configuration register specified by Address, performs a
1128 bitwise AND followed by a bitwise inclusive OR between the read result and
1129 the value specified by AndData, and writes the result to the 32-bit PCI
1130 configuration register specified by Address. The value written to the PCI
1131 configuration register is returned. This function must guarantee that all PCI
1132 read and write operations are serialized. Extra left bits in both AndData and
1133 OrData are stripped.
1135 If Address > 0x0FFFFFFF, then ASSERT().
1136 If Address is not aligned on a 32-bit boundary, then ASSERT().
1137 If StartBit is greater than 31, then ASSERT().
1138 If EndBit is greater than 31, then ASSERT().
1139 If EndBit is less than StartBit, then ASSERT().
1141 @param Address PCI configuration register to write.
1142 @param StartBit The ordinal of the least significant bit in the bit field.
1144 @param EndBit The ordinal of the most significant bit in the bit field.
1146 @param AndData The value to AND with the PCI configuration register.
1147 @param OrData The value to OR with the result of the AND operation.
1149 @return The value written back to the PCI configuration register.
1154 PciExpressBitFieldAndThenOr32 (
1162 ASSERT_INVALID_PCI_ADDRESS (Address
);
1163 return MmioBitFieldAndThenOr32 (
1164 (UINTN
) GetPciExpressBaseAddress () + Address
,
1173 Reads a range of PCI configuration registers into a caller supplied buffer.
1175 Reads the range of PCI configuration registers specified by StartAddress and
1176 Size into the buffer specified by Buffer. This function only allows the PCI
1177 configuration registers from a single PCI function to be read. Size is
1178 returned. When possible 32-bit PCI configuration read cycles are used to read
1179 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1180 and 16-bit PCI configuration read cycles may be used at the beginning and the
1183 If StartAddress > 0x0FFFFFFF, then ASSERT().
1184 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1185 If Size > 0 and Buffer is NULL, then ASSERT().
1187 @param StartAddress Starting address that encodes the PCI Bus, Device,
1188 Function and Register.
1189 @param Size Size in bytes of the transfer.
1190 @param Buffer Pointer to a buffer receiving the data read.
1197 PciExpressReadBuffer (
1198 IN UINTN StartAddress
,
1205 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1206 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1212 ASSERT (Buffer
!= NULL
);
1215 // Save Size for return
1219 if ((StartAddress
& 1) != 0) {
1221 // Read a byte if StartAddress is byte aligned
1223 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1224 StartAddress
+= sizeof (UINT8
);
1225 Size
-= sizeof (UINT8
);
1226 Buffer
= (UINT8
*)Buffer
+ 1;
1229 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1231 // Read a word if StartAddress is word aligned
1233 *(volatile UINT16
*)Buffer
= PciExpressRead16 (StartAddress
);
1234 StartAddress
+= sizeof (UINT16
);
1235 Size
-= sizeof (UINT16
);
1236 Buffer
= (UINT16
*)Buffer
+ 1;
1239 while (Size
>= sizeof (UINT32
)) {
1241 // Read as many double words as possible
1243 *(volatile UINT32
*)Buffer
= PciExpressRead32 (StartAddress
);
1244 StartAddress
+= sizeof (UINT32
);
1245 Size
-= sizeof (UINT32
);
1246 Buffer
= (UINT32
*)Buffer
+ 1;
1249 if (Size
>= sizeof (UINT16
)) {
1251 // Read the last remaining word if exist
1253 *(volatile UINT16
*)Buffer
= PciExpressRead16 (StartAddress
);
1254 StartAddress
+= sizeof (UINT16
);
1255 Size
-= sizeof (UINT16
);
1256 Buffer
= (UINT16
*)Buffer
+ 1;
1259 if (Size
>= sizeof (UINT8
)) {
1261 // Read the last remaining byte if exist
1263 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1270 Copies the data in a caller supplied buffer to a specified range of PCI
1271 configuration space.
1273 Writes the range of PCI configuration registers specified by StartAddress and
1274 Size from the buffer specified by Buffer. This function only allows the PCI
1275 configuration registers from a single PCI function to be written. Size is
1276 returned. When possible 32-bit PCI configuration write cycles are used to
1277 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1278 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1279 and the end of the range.
1281 If StartAddress > 0x0FFFFFFF, then ASSERT().
1282 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1283 If Size > 0 and Buffer is NULL, then ASSERT().
1285 @param StartAddress Starting address that encodes the PCI Bus, Device,
1286 Function and Register.
1287 @param Size Size in bytes of the transfer.
1288 @param Buffer Pointer to a buffer containing the data to write.
1295 PciExpressWriteBuffer (
1296 IN UINTN StartAddress
,
1303 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1304 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1310 ASSERT (Buffer
!= NULL
);
1313 // Save Size for return
1317 if ((StartAddress
& 1) != 0) {
1319 // Write a byte if StartAddress is byte aligned
1321 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1322 StartAddress
+= sizeof (UINT8
);
1323 Size
-= sizeof (UINT8
);
1324 Buffer
= (UINT8
*)Buffer
+ 1;
1327 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1329 // Write a word if StartAddress is word aligned
1331 PciExpressWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1332 StartAddress
+= sizeof (UINT16
);
1333 Size
-= sizeof (UINT16
);
1334 Buffer
= (UINT16
*)Buffer
+ 1;
1337 while (Size
>= sizeof (UINT32
)) {
1339 // Write as many double words as possible
1341 PciExpressWrite32 (StartAddress
, *(UINT32
*)Buffer
);
1342 StartAddress
+= sizeof (UINT32
);
1343 Size
-= sizeof (UINT32
);
1344 Buffer
= (UINT32
*)Buffer
+ 1;
1347 if (Size
>= sizeof (UINT16
)) {
1349 // Write the last remaining word if exist
1351 PciExpressWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1352 StartAddress
+= sizeof (UINT16
);
1353 Size
-= sizeof (UINT16
);
1354 Buffer
= (UINT16
*)Buffer
+ 1;
1357 if (Size
>= sizeof (UINT8
)) {
1359 // Write the last remaining byte if exist
1361 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);