2 DXE PCI Library instance layered on top of ESAL services.
4 Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php.
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 #include <Protocol/ExtendedSalServiceClasses.h>
19 #include <Library/PciLib.h>
20 #include <Library/BaseLib.h>
21 #include <Library/DebugLib.h>
22 #include <Library/ExtendedSalLib.h>
25 Assert the validity of a PCI address. A valid PCI address should contain 1's
26 only in the low 28 bits.
28 @param A The address to validate.
29 @param M Additional bits to assert to be zero.
32 #define ASSERT_INVALID_PCI_ADDRESS(A,M) \
33 ASSERT (((A) & (~0xfffffff | (M))) == 0)
36 Converts a PCI Library Address to a ESAL PCI Service Address.
37 Based on SAL Spec 3.2, there are two SAL PCI Address:
40 Bits 0..7 - Register address
41 Bits 8..10 - Function number
42 Bits 11..15 - Device number
43 Bits 16..23 - Bus number
44 Bits 24..31 - PCI segment group
45 Bits 32..63 - Reserved (0)
48 Bits 0..7 - Register address
49 Bits 8..11 - Extended Register address
50 Bits 12..14 - Function number
51 Bits 15..19 - Device number
52 Bits 20..27 - Bus number
53 Bits 28..43 - PCI segment group
54 Bits 44..63 - Reserved (0)
56 @param A The PCI Library Address to convert.
59 #define CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0(Address) ((((Address) >> 4) & 0x00ffff00) | ((Address) & 0xff))
60 #define CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1(Address) (Address)
63 Check a PCI Library Address is a PCI Compatible Address or not.
65 #define IS_PCI_COMPATIBLE_ADDRESS(Address) (((Address) & 0xf00) == 0)
68 Internal worker function to read a PCI configuration register.
70 This function wraps EsalPciConfigRead function of Extended SAL PCI
72 It reads and returns the PCI configuration register specified by Address,
73 the width of data is specified by Width.
75 @param Address Address that encodes the PCI Bus, Device, Function and
77 @param Width Width of data to read
79 @return The value read from the PCI configuration register.
83 DxePciLibEsalReadWorker (
88 SAL_RETURN_REGS Return
;
90 if (IS_PCI_COMPATIBLE_ADDRESS(Address
)) {
92 EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO
,
93 EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI
,
94 SalPciConfigReadFunctionId
,
95 CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0 (Address
),
97 EFI_SAL_PCI_COMPATIBLE_ADDRESS
,
105 EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO
,
106 EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI
,
107 SalPciConfigReadFunctionId
,
108 CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1 (Address
),
110 EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS
,
118 return (UINT32
) Return
.r9
;
122 Internal worker function to writes a PCI configuration register.
124 This function wraps EsalPciConfigWrite function of Extended SAL PCI
126 It writes the PCI configuration register specified by Address with the
127 value specified by Data. The width of data is specified by Width.
130 @param Address Address that encodes the PCI Bus, Device, Function and
132 @param Width Width of data to write
133 @param Data The value to write.
135 @return The value written to the PCI configuration register.
139 DxePciLibEsalWriteWorker (
145 if (IS_PCI_COMPATIBLE_ADDRESS(Address
)) {
147 EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO
,
148 EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI
,
149 SalPciConfigWriteFunctionId
,
150 CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0 (Address
),
153 EFI_SAL_PCI_COMPATIBLE_ADDRESS
,
160 EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO
,
161 EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI
,
162 SalPciConfigWriteFunctionId
,
163 CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1 (Address
),
166 EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS
,
177 Register a PCI device so PCI configuration registers may be accessed after
178 SetVirtualAddressMap().
180 If Address > 0x0FFFFFFF, then ASSERT().
182 @param Address Address that encodes the PCI Bus, Device, Function and
185 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
186 @retval RETURN_UNSUPPORTED An attempt was made to call this function
187 after ExitBootServices().
188 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
189 at runtime could not be mapped.
190 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
191 complete the registration.
196 PciRegisterForRuntimeAccess (
200 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
201 return RETURN_SUCCESS
;
205 Reads an 8-bit PCI configuration register.
207 Reads and returns the 8-bit PCI configuration register specified by Address.
208 This function must guarantee that all PCI read and write operations are
211 If Address > 0x0FFFFFFF, then ASSERT().
213 @param Address Address that encodes the PCI Bus, Device, Function and
216 @return The value read from the PCI configuration register.
225 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
227 return (UINT8
) DxePciLibEsalReadWorker (Address
, 1);
231 Writes an 8-bit PCI configuration register.
233 Writes the 8-bit PCI configuration register specified by Address with the
234 value specified by Value. Value is returned. This function must guarantee
235 that all PCI read and write operations are serialized.
237 If Address > 0x0FFFFFFF, then ASSERT().
239 @param Address Address that encodes the PCI Bus, Device, Function and
241 @param Data The value to write.
243 @return The value written to the PCI configuration register.
253 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
255 return (UINT8
) DxePciLibEsalWriteWorker (Address
, 1, Data
);
259 Performs a bitwise OR of an 8-bit PCI configuration register with
262 Reads the 8-bit PCI configuration register specified by Address, performs a
263 bitwise OR between the read result and the value specified by
264 OrData, and writes the result to the 8-bit PCI configuration register
265 specified by Address. The value written to the PCI configuration register is
266 returned. This function must guarantee that all PCI read and write operations
269 If Address > 0x0FFFFFFF, then ASSERT().
271 @param Address Address that encodes the PCI Bus, Device, Function and
273 @param OrData The value to OR with the PCI configuration register.
275 @return The value written back to the PCI configuration register.
285 return PciWrite8 (Address
, (UINT8
)(PciRead8 (Address
) | OrData
));
289 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
292 Reads the 8-bit PCI configuration register specified by Address, performs a
293 bitwise AND between the read result and the value specified by AndData, and
294 writes the result to the 8-bit PCI configuration register specified by
295 Address. The value written to the PCI configuration register is returned.
296 This function must guarantee that all PCI read and write operations are
299 If Address > 0x0FFFFFFF, then ASSERT().
301 @param Address Address that encodes the PCI Bus, Device, Function and
303 @param AndData The value to AND with the PCI configuration register.
305 @return The value written back to the PCI configuration register.
315 return PciWrite8 (Address
, (UINT8
)(PciRead8 (Address
) & AndData
));
319 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
320 value, followed a bitwise OR with another 8-bit value.
322 Reads the 8-bit PCI configuration register specified by Address, performs a
323 bitwise AND between the read result and the value specified by AndData,
324 performs a bitwise OR between the result of the AND operation and
325 the value specified by OrData, and writes the result to the 8-bit PCI
326 configuration register specified by Address. The value written to the PCI
327 configuration register is returned. This function must guarantee that all PCI
328 read and write operations are serialized.
330 If Address > 0x0FFFFFFF, then ASSERT().
332 @param Address Address that encodes the PCI Bus, Device, Function and
334 @param AndData The value to AND with the PCI configuration register.
335 @param OrData The value to OR with the result of the AND operation.
337 @return The value written back to the PCI configuration register.
348 return PciWrite8 (Address
, (UINT8
)((PciRead8 (Address
) & AndData
) | OrData
));
352 Reads a bit field of a PCI configuration register.
354 Reads the bit field in an 8-bit PCI configuration register. The bit field is
355 specified by the StartBit and the EndBit. The value of the bit field is
358 If Address > 0x0FFFFFFF, then ASSERT().
359 If StartBit is greater than 7, then ASSERT().
360 If EndBit is greater than 7, then ASSERT().
361 If EndBit is less than StartBit, then ASSERT().
363 @param Address PCI configuration register to read.
364 @param StartBit The ordinal of the least significant bit in the bit field.
366 @param EndBit The ordinal of the most significant bit in the bit field.
369 @return The value of the bit field read from the PCI configuration register.
380 return BitFieldRead8 (PciRead8 (Address
), StartBit
, EndBit
);
384 Writes a bit field to a PCI configuration register.
386 Writes Value to the bit field of the PCI configuration register. The bit
387 field is specified by the StartBit and the EndBit. All other bits in the
388 destination PCI configuration register are preserved. The new value of the
389 8-bit register is returned.
391 If Address > 0x0FFFFFFF, then ASSERT().
392 If StartBit is greater than 7, then ASSERT().
393 If EndBit is greater than 7, then ASSERT().
394 If EndBit is less than StartBit, then ASSERT().
395 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
397 @param Address PCI configuration register to write.
398 @param StartBit The ordinal of the least significant bit in the bit field.
400 @param EndBit The ordinal of the most significant bit in the bit field.
402 @param Value New value of the bit field.
404 @return The value written back to the PCI configuration register.
418 BitFieldWrite8 (PciRead8 (Address
), StartBit
, EndBit
, Value
)
423 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
424 writes the result back to the bit field in the 8-bit port.
426 Reads the 8-bit PCI configuration register specified by Address, performs a
427 bitwise OR between the read result and the value specified by
428 OrData, and writes the result to the 8-bit PCI configuration register
429 specified by Address. The value written to the PCI configuration register is
430 returned. This function must guarantee that all PCI read and write operations
431 are serialized. Extra left bits in OrData are stripped.
433 If Address > 0x0FFFFFFF, then ASSERT().
434 If StartBit is greater than 7, then ASSERT().
435 If EndBit is greater than 7, then ASSERT().
436 If EndBit is less than StartBit, then ASSERT().
437 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
439 @param Address PCI configuration register to write.
440 @param StartBit The ordinal of the least significant bit in the bit field.
442 @param EndBit The ordinal of the most significant bit in the bit field.
444 @param OrData The value to OR with the PCI configuration register.
446 @return The value written back to the PCI configuration register.
460 BitFieldOr8 (PciRead8 (Address
), StartBit
, EndBit
, OrData
)
465 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
466 AND, and writes the result back to the bit field in the 8-bit register.
468 Reads the 8-bit PCI configuration register specified by Address, performs a
469 bitwise AND between the read result and the value specified by AndData, and
470 writes the result to the 8-bit PCI configuration register specified by
471 Address. The value written to the PCI configuration register is returned.
472 This function must guarantee that all PCI read and write operations are
473 serialized. Extra left bits in AndData are stripped.
475 If Address > 0x0FFFFFFF, then ASSERT().
476 If StartBit is greater than 7, then ASSERT().
477 If EndBit is greater than 7, then ASSERT().
478 If EndBit is less than StartBit, then ASSERT().
479 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
481 @param Address PCI configuration register to write.
482 @param StartBit The ordinal of the least significant bit in the bit field.
484 @param EndBit The ordinal of the most significant bit in the bit field.
486 @param AndData The value to AND with the PCI configuration register.
488 @return The value written back to the PCI configuration register.
502 BitFieldAnd8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
)
507 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
508 bitwise OR, and writes the result back to the bit field in the
511 Reads the 8-bit PCI configuration register specified by Address, performs a
512 bitwise AND followed by a bitwise OR between the read result and
513 the value specified by AndData, and writes the result to the 8-bit PCI
514 configuration register specified by Address. The value written to the PCI
515 configuration register is returned. This function must guarantee that all PCI
516 read and write operations are serialized. Extra left bits in both AndData and
519 If Address > 0x0FFFFFFF, then ASSERT().
520 If StartBit is greater than 7, then ASSERT().
521 If EndBit is greater than 7, then ASSERT().
522 If EndBit is less than StartBit, then ASSERT().
523 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
524 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
526 @param Address PCI configuration register to write.
527 @param StartBit The ordinal of the least significant bit in the bit field.
529 @param EndBit The ordinal of the most significant bit in the bit field.
531 @param AndData The value to AND with the PCI configuration register.
532 @param OrData The value to OR with the result of the AND operation.
534 @return The value written back to the PCI configuration register.
539 PciBitFieldAndThenOr8 (
549 BitFieldAndThenOr8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
, OrData
)
554 Reads a 16-bit PCI configuration register.
556 Reads and returns the 16-bit PCI configuration register specified by Address.
557 This function must guarantee that all PCI read and write operations are
560 If Address > 0x0FFFFFFF, then ASSERT().
561 If Address is not aligned on a 16-bit boundary, then ASSERT().
563 @param Address Address that encodes the PCI Bus, Device, Function and
566 @return The value read from the PCI configuration register.
575 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
577 return (UINT16
) DxePciLibEsalReadWorker (Address
, 2);
581 Writes a 16-bit PCI configuration register.
583 Writes the 16-bit PCI configuration register specified by Address with the
584 value specified by Value. Value is returned. This function must guarantee
585 that all PCI read and write operations are serialized.
587 If Address > 0x0FFFFFFF, then ASSERT().
588 If Address is not aligned on a 16-bit boundary, then ASSERT().
590 @param Address Address that encodes the PCI Bus, Device, Function and
592 @param Data The value to write.
594 @return The value written to the PCI configuration register.
604 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
606 return (UINT16
) DxePciLibEsalWriteWorker (Address
, 2, Data
);
610 Performs a bitwise OR of a 16-bit PCI configuration register with
613 Reads the 16-bit PCI configuration register specified by Address, performs a
614 bitwise OR between the read result and the value specified by
615 OrData, and writes the result to the 16-bit PCI configuration register
616 specified by Address. The value written to the PCI configuration register is
617 returned. This function must guarantee that all PCI read and write operations
620 If Address > 0x0FFFFFFF, then ASSERT().
621 If Address is not aligned on a 16-bit boundary, then ASSERT().
623 @param Address Address that encodes the PCI Bus, Device, Function and
625 @param OrData The value to OR with the PCI configuration register.
627 @return The value written back to the PCI configuration register.
637 return PciWrite16 (Address
, (UINT16
)(PciRead16 (Address
) | OrData
));
641 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
644 Reads the 16-bit PCI configuration register specified by Address, performs a
645 bitwise AND between the read result and the value specified by AndData, and
646 writes the result to the 16-bit PCI configuration register specified by
647 Address. The value written to the PCI configuration register is returned.
648 This function must guarantee that all PCI read and write operations are
651 If Address > 0x0FFFFFFF, then ASSERT().
652 If Address is not aligned on a 16-bit boundary, then ASSERT().
654 @param Address Address that encodes the PCI Bus, Device, Function and
656 @param AndData The value to AND with the PCI configuration register.
658 @return The value written back to the PCI configuration register.
668 return PciWrite16 (Address
, (UINT16
)(PciRead16 (Address
) & AndData
));
672 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
673 value, followed a bitwise OR with another 16-bit value.
675 Reads the 16-bit PCI configuration register specified by Address, performs a
676 bitwise AND between the read result and the value specified by AndData,
677 performs a bitwise OR between the result of the AND operation and
678 the value specified by OrData, and writes the result to the 16-bit PCI
679 configuration register specified by Address. The value written to the PCI
680 configuration register is returned. This function must guarantee that all PCI
681 read and write operations are serialized.
683 If Address > 0x0FFFFFFF, then ASSERT().
684 If Address is not aligned on a 16-bit boundary, then ASSERT().
686 @param Address Address that encodes the PCI Bus, Device, Function and
688 @param AndData The value to AND with the PCI configuration register.
689 @param OrData The value to OR with the result of the AND operation.
691 @return The value written back to the PCI configuration register.
702 return PciWrite16 (Address
, (UINT16
)((PciRead16 (Address
) & AndData
) | OrData
));
706 Reads a bit field of a PCI configuration register.
708 Reads the bit field in a 16-bit PCI configuration register. The bit field is
709 specified by the StartBit and the EndBit. The value of the bit field is
712 If Address > 0x0FFFFFFF, then ASSERT().
713 If Address is not aligned on a 16-bit boundary, then ASSERT().
714 If StartBit is greater than 15, then ASSERT().
715 If EndBit is greater than 15, then ASSERT().
716 If EndBit is less than StartBit, then ASSERT().
718 @param Address PCI configuration register to read.
719 @param StartBit The ordinal of the least significant bit in the bit field.
721 @param EndBit The ordinal of the most significant bit in the bit field.
724 @return The value of the bit field read from the PCI configuration register.
735 return BitFieldRead16 (PciRead16 (Address
), StartBit
, EndBit
);
739 Writes a bit field to a PCI configuration register.
741 Writes Value to the bit field of the PCI configuration register. The bit
742 field is specified by the StartBit and the EndBit. All other bits in the
743 destination PCI configuration register are preserved. The new value of the
744 16-bit register is returned.
746 If Address > 0x0FFFFFFF, then ASSERT().
747 If Address is not aligned on a 16-bit boundary, then ASSERT().
748 If StartBit is greater than 15, then ASSERT().
749 If EndBit is greater than 15, then ASSERT().
750 If EndBit is less than StartBit, then ASSERT().
751 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
753 @param Address PCI configuration register to write.
754 @param StartBit The ordinal of the least significant bit in the bit field.
756 @param EndBit The ordinal of the most significant bit in the bit field.
758 @param Value New value of the bit field.
760 @return The value written back to the PCI configuration register.
774 BitFieldWrite16 (PciRead16 (Address
), StartBit
, EndBit
, Value
)
779 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
780 writes the result back to the bit field in the 16-bit port.
782 Reads the 16-bit PCI configuration register specified by Address, performs a
783 bitwise OR between the read result and the value specified by
784 OrData, and writes the result to the 16-bit PCI configuration register
785 specified by Address. The value written to the PCI configuration register is
786 returned. This function must guarantee that all PCI read and write operations
787 are serialized. Extra left bits in OrData are stripped.
789 If Address > 0x0FFFFFFF, then ASSERT().
790 If Address is not aligned on a 16-bit boundary, then ASSERT().
791 If StartBit is greater than 15, then ASSERT().
792 If EndBit is greater than 15, then ASSERT().
793 If EndBit is less than StartBit, then ASSERT().
794 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
796 @param Address PCI configuration register to write.
797 @param StartBit The ordinal of the least significant bit in the bit field.
799 @param EndBit The ordinal of the most significant bit in the bit field.
801 @param OrData The value to OR with the PCI configuration register.
803 @return The value written back to the PCI configuration register.
817 BitFieldOr16 (PciRead16 (Address
), StartBit
, EndBit
, OrData
)
822 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
823 AND, and writes the result back to the bit field in the 16-bit register.
825 Reads the 16-bit PCI configuration register specified by Address, performs a
826 bitwise AND between the read result and the value specified by AndData, and
827 writes the result to the 16-bit PCI configuration register specified by
828 Address. The value written to the PCI configuration register is returned.
829 This function must guarantee that all PCI read and write operations are
830 serialized. Extra left bits in AndData are stripped.
832 If Address > 0x0FFFFFFF, then ASSERT().
833 If Address is not aligned on a 16-bit boundary, then ASSERT().
834 If StartBit is greater than 15, then ASSERT().
835 If EndBit is greater than 15, then ASSERT().
836 If EndBit is less than StartBit, then ASSERT().
837 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
839 @param Address PCI configuration register to write.
840 @param StartBit The ordinal of the least significant bit in the bit field.
842 @param EndBit The ordinal of the most significant bit in the bit field.
844 @param AndData The value to AND with the PCI configuration register.
846 @return The value written back to the PCI configuration register.
860 BitFieldAnd16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
)
865 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
866 bitwise OR, and writes the result back to the bit field in the
869 Reads the 16-bit PCI configuration register specified by Address, performs a
870 bitwise AND followed by a bitwise OR between the read result and
871 the value specified by AndData, and writes the result to the 16-bit PCI
872 configuration register specified by Address. The value written to the PCI
873 configuration register is returned. This function must guarantee that all PCI
874 read and write operations are serialized. Extra left bits in both AndData and
877 If Address > 0x0FFFFFFF, then ASSERT().
878 If Address is not aligned on a 16-bit boundary, then ASSERT().
879 If StartBit is greater than 15, then ASSERT().
880 If EndBit is greater than 15, then ASSERT().
881 If EndBit is less than StartBit, then ASSERT().
882 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
883 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
885 @param Address PCI configuration register to write.
886 @param StartBit The ordinal of the least significant bit in the bit field.
888 @param EndBit The ordinal of the most significant bit in the bit field.
890 @param AndData The value to AND with the PCI configuration register.
891 @param OrData The value to OR with the result of the AND operation.
893 @return The value written back to the PCI configuration register.
898 PciBitFieldAndThenOr16 (
908 BitFieldAndThenOr16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
, OrData
)
913 Reads a 32-bit PCI configuration register.
915 Reads and returns the 32-bit PCI configuration register specified by Address.
916 This function must guarantee that all PCI read and write operations are
919 If Address > 0x0FFFFFFF, then ASSERT().
920 If Address is not aligned on a 32-bit boundary, then ASSERT().
922 @param Address Address that encodes the PCI Bus, Device, Function and
925 @return The value read from the PCI configuration register.
934 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
936 return DxePciLibEsalReadWorker (Address
, 4);
940 Writes a 32-bit PCI configuration register.
942 Writes the 32-bit PCI configuration register specified by Address with the
943 value specified by Value. Value is returned. This function must guarantee
944 that all PCI read and write operations are serialized.
946 If Address > 0x0FFFFFFF, then ASSERT().
947 If Address is not aligned on a 32-bit boundary, then ASSERT().
949 @param Address Address that encodes the PCI Bus, Device, Function and
951 @param Data The value to write.
953 @return The value written to the PCI configuration register.
963 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
965 return DxePciLibEsalWriteWorker (Address
, 4, Data
);
969 Performs a bitwise OR of a 32-bit PCI configuration register with
972 Reads the 32-bit PCI configuration register specified by Address, performs a
973 bitwise OR between the read result and the value specified by
974 OrData, and writes the result to the 32-bit PCI configuration register
975 specified by Address. The value written to the PCI configuration register is
976 returned. This function must guarantee that all PCI read and write operations
979 If Address > 0x0FFFFFFF, then ASSERT().
980 If Address is not aligned on a 32-bit boundary, then ASSERT().
982 @param Address Address that encodes the PCI Bus, Device, Function and
984 @param OrData The value to OR with the PCI configuration register.
986 @return The value written back to the PCI configuration register.
996 return PciWrite32 (Address
, PciRead32 (Address
) | OrData
);
1000 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
1003 Reads the 32-bit PCI configuration register specified by Address, performs a
1004 bitwise AND between the read result and the value specified by AndData, and
1005 writes the result to the 32-bit PCI configuration register specified by
1006 Address. The value written to the PCI configuration register is returned.
1007 This function must guarantee that all PCI read and write operations are
1010 If Address > 0x0FFFFFFF, then ASSERT().
1011 If Address is not aligned on a 32-bit boundary, then ASSERT().
1013 @param Address Address that encodes the PCI Bus, Device, Function and
1015 @param AndData The value to AND with the PCI configuration register.
1017 @return The value written back to the PCI configuration register.
1027 return PciWrite32 (Address
, PciRead32 (Address
) & AndData
);
1031 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
1032 value, followed a bitwise OR with another 32-bit value.
1034 Reads the 32-bit PCI configuration register specified by Address, performs a
1035 bitwise AND between the read result and the value specified by AndData,
1036 performs a bitwise OR between the result of the AND operation and
1037 the value specified by OrData, and writes the result to the 32-bit PCI
1038 configuration register specified by Address. The value written to the PCI
1039 configuration register is returned. This function must guarantee that all PCI
1040 read and write operations are serialized.
1042 If Address > 0x0FFFFFFF, then ASSERT().
1043 If Address is not aligned on a 32-bit boundary, then ASSERT().
1045 @param Address Address that encodes the PCI Bus, Device, Function and
1047 @param AndData The value to AND with the PCI configuration register.
1048 @param OrData The value to OR with the result of the AND operation.
1050 @return The value written back to the PCI configuration register.
1061 return PciWrite32 (Address
, (PciRead32 (Address
) & AndData
) | OrData
);
1065 Reads a bit field of a PCI configuration register.
1067 Reads the bit field in a 32-bit PCI configuration register. The bit field is
1068 specified by the StartBit and the EndBit. The value of the bit field is
1071 If Address > 0x0FFFFFFF, then ASSERT().
1072 If Address is not aligned on a 32-bit boundary, then ASSERT().
1073 If StartBit is greater than 31, then ASSERT().
1074 If EndBit is greater than 31, then ASSERT().
1075 If EndBit is less than StartBit, then ASSERT().
1077 @param Address PCI configuration register to read.
1078 @param StartBit The ordinal of the least significant bit in the bit field.
1080 @param EndBit The ordinal of the most significant bit in the bit field.
1083 @return The value of the bit field read from the PCI configuration register.
1094 return BitFieldRead32 (PciRead32 (Address
), StartBit
, EndBit
);
1098 Writes a bit field to a PCI configuration register.
1100 Writes Value to the bit field of the PCI configuration register. The bit
1101 field is specified by the StartBit and the EndBit. All other bits in the
1102 destination PCI configuration register are preserved. The new value of the
1103 32-bit register is returned.
1105 If Address > 0x0FFFFFFF, then ASSERT().
1106 If Address is not aligned on a 32-bit boundary, then ASSERT().
1107 If StartBit is greater than 31, then ASSERT().
1108 If EndBit is greater than 31, then ASSERT().
1109 If EndBit is less than StartBit, then ASSERT().
1110 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1112 @param Address PCI configuration register to write.
1113 @param StartBit The ordinal of the least significant bit in the bit field.
1115 @param EndBit The ordinal of the most significant bit in the bit field.
1117 @param Value New value of the bit field.
1119 @return The value written back to the PCI configuration register.
1124 PciBitFieldWrite32 (
1133 BitFieldWrite32 (PciRead32 (Address
), StartBit
, EndBit
, Value
)
1138 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1139 writes the result back to the bit field in the 32-bit port.
1141 Reads the 32-bit PCI configuration register specified by Address, performs a
1142 bitwise OR between the read result and the value specified by
1143 OrData, and writes the result to the 32-bit PCI configuration register
1144 specified by Address. The value written to the PCI configuration register is
1145 returned. This function must guarantee that all PCI read and write operations
1146 are serialized. Extra left bits in OrData are stripped.
1148 If Address > 0x0FFFFFFF, then ASSERT().
1149 If Address is not aligned on a 32-bit boundary, then ASSERT().
1150 If StartBit is greater than 31, then ASSERT().
1151 If EndBit is greater than 31, then ASSERT().
1152 If EndBit is less than StartBit, then ASSERT().
1153 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1155 @param Address PCI configuration register to write.
1156 @param StartBit The ordinal of the least significant bit in the bit field.
1158 @param EndBit The ordinal of the most significant bit in the bit field.
1160 @param OrData The value to OR with the PCI configuration register.
1162 @return The value written back to the PCI configuration register.
1176 BitFieldOr32 (PciRead32 (Address
), StartBit
, EndBit
, OrData
)
1181 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1182 AND, and writes the result back to the bit field in the 32-bit register.
1184 Reads the 32-bit PCI configuration register specified by Address, performs a
1185 bitwise AND between the read result and the value specified by AndData, and
1186 writes the result to the 32-bit PCI configuration register specified by
1187 Address. The value written to the PCI configuration register is returned.
1188 This function must guarantee that all PCI read and write operations are
1189 serialized. Extra left bits in AndData are stripped.
1191 If Address > 0x0FFFFFFF, then ASSERT().
1192 If Address is not aligned on a 32-bit boundary, then ASSERT().
1193 If StartBit is greater than 31, then ASSERT().
1194 If EndBit is greater than 31, then ASSERT().
1195 If EndBit is less than StartBit, then ASSERT().
1196 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1198 @param Address PCI configuration register to write.
1199 @param StartBit The ordinal of the least significant bit in the bit field.
1201 @param EndBit The ordinal of the most significant bit in the bit field.
1203 @param AndData The value to AND with the PCI configuration register.
1205 @return The value written back to the PCI configuration register.
1219 BitFieldAnd32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
)
1224 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1225 bitwise OR, and writes the result back to the bit field in the
1228 Reads the 32-bit PCI configuration register specified by Address, performs a
1229 bitwise AND followed by a bitwise OR between the read result and
1230 the value specified by AndData, and writes the result to the 32-bit PCI
1231 configuration register specified by Address. The value written to the PCI
1232 configuration register is returned. This function must guarantee that all PCI
1233 read and write operations are serialized. Extra left bits in both AndData and
1234 OrData are stripped.
1236 If Address > 0x0FFFFFFF, then ASSERT().
1237 If Address is not aligned on a 32-bit boundary, then ASSERT().
1238 If StartBit is greater than 31, then ASSERT().
1239 If EndBit is greater than 31, then ASSERT().
1240 If EndBit is less than StartBit, then ASSERT().
1241 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1242 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1244 @param Address PCI configuration register to write.
1245 @param StartBit The ordinal of the least significant bit in the bit field.
1247 @param EndBit The ordinal of the most significant bit in the bit field.
1249 @param AndData The value to AND with the PCI configuration register.
1250 @param OrData The value to OR with the result of the AND operation.
1252 @return The value written back to the PCI configuration register.
1257 PciBitFieldAndThenOr32 (
1267 BitFieldAndThenOr32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
, OrData
)
1272 Reads a range of PCI configuration registers into a caller supplied buffer.
1274 Reads the range of PCI configuration registers specified by StartAddress and
1275 Size into the buffer specified by Buffer. This function only allows the PCI
1276 configuration registers from a single PCI function to be read. Size is
1277 returned. When possible 32-bit PCI configuration read cycles are used to read
1278 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1279 and 16-bit PCI configuration read cycles may be used at the beginning and the
1282 If StartAddress > 0x0FFFFFFF, then ASSERT().
1283 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1284 If Size > 0 and Buffer is NULL, then ASSERT().
1286 @param StartAddress Starting address that encodes the PCI Bus, Device,
1287 Function and Register.
1288 @param Size Size in bytes of the transfer.
1289 @param Buffer Pointer to a buffer receiving the data read.
1297 IN UINTN StartAddress
,
1304 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1305 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x100);
1311 ASSERT (Buffer
!= NULL
);
1314 // Save Size for return
1318 if ((StartAddress
& 1) != 0) {
1320 // Read a byte if StartAddress is byte aligned
1322 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1323 StartAddress
+= sizeof (UINT8
);
1324 Size
-= sizeof (UINT8
);
1325 Buffer
= (UINT8
*)Buffer
+ 1;
1328 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1330 // Read a word if StartAddress is word aligned
1332 *(volatile UINT16
*)Buffer
= PciRead16 (StartAddress
);
1333 StartAddress
+= sizeof (UINT16
);
1334 Size
-= sizeof (UINT16
);
1335 Buffer
= (UINT16
*)Buffer
+ 1;
1338 while (Size
>= sizeof (UINT32
)) {
1340 // Read as many double words as possible
1342 *(volatile UINT32
*)Buffer
= PciRead32 (StartAddress
);
1343 StartAddress
+= sizeof (UINT32
);
1344 Size
-= sizeof (UINT32
);
1345 Buffer
= (UINT32
*)Buffer
+ 1;
1348 if (Size
>= sizeof (UINT16
)) {
1350 // Read the last remaining word if exist
1352 *(volatile UINT16
*)Buffer
= PciRead16 (StartAddress
);
1353 StartAddress
+= sizeof (UINT16
);
1354 Size
-= sizeof (UINT16
);
1355 Buffer
= (UINT16
*)Buffer
+ 1;
1358 if (Size
>= sizeof (UINT8
)) {
1360 // Read the last remaining byte if exist
1362 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1369 Copies the data in a caller supplied buffer to a specified range of PCI
1370 configuration space.
1372 Writes the range of PCI configuration registers specified by StartAddress and
1373 Size from the buffer specified by Buffer. This function only allows the PCI
1374 configuration registers from a single PCI function to be written. Size is
1375 returned. When possible 32-bit PCI configuration write cycles are used to
1376 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1377 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1378 and the end of the range.
1380 If StartAddress > 0x0FFFFFFF, then ASSERT().
1381 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1382 If Size > 0 and Buffer is NULL, then ASSERT().
1384 @param StartAddress Starting address that encodes the PCI Bus, Device,
1385 Function and Register.
1386 @param Size Size in bytes of the transfer.
1387 @param Buffer Pointer to a buffer containing the data to write.
1395 IN UINTN StartAddress
,
1402 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1403 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x100);
1409 ASSERT (Buffer
!= NULL
);
1412 // Save Size for return
1416 if ((StartAddress
& 1) != 0) {
1418 // Write a byte if StartAddress is byte aligned
1420 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1421 StartAddress
+= sizeof (UINT8
);
1422 Size
-= sizeof (UINT8
);
1423 Buffer
= (UINT8
*)Buffer
+ 1;
1426 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1428 // Write a word if StartAddress is word aligned
1430 PciWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1431 StartAddress
+= sizeof (UINT16
);
1432 Size
-= sizeof (UINT16
);
1433 Buffer
= (UINT16
*)Buffer
+ 1;
1436 while (Size
>= sizeof (UINT32
)) {
1438 // Write as many double words as possible
1440 PciWrite32 (StartAddress
, *(UINT32
*)Buffer
);
1441 StartAddress
+= sizeof (UINT32
);
1442 Size
-= sizeof (UINT32
);
1443 Buffer
= (UINT32
*)Buffer
+ 1;
1446 if (Size
>= sizeof (UINT16
)) {
1448 // Write the last remaining word if exist
1450 PciWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1451 StartAddress
+= sizeof (UINT16
);
1452 Size
-= sizeof (UINT16
);
1453 Buffer
= (UINT16
*)Buffer
+ 1;
1456 if (Size
>= sizeof (UINT8
)) {
1458 // Write the last remaining byte if exist
1460 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);