2 DXE PCI Library instance layered on top of ESAL services.
4 Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php.
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 #include <Protocol/ExtendedSalServiceClasses.h>
19 #include <Library/PciLib.h>
20 #include <Library/BaseLib.h>
21 #include <Library/DebugLib.h>
22 #include <Library/ExtendedSalLib.h>
25 Assert the validity of a PCI address. A valid PCI address should contain 1's
26 only in the low 28 bits.
28 @param A The address to validate.
29 @param M Additional bits to assert to be zero.
32 #define ASSERT_INVALID_PCI_ADDRESS(A,M) \
33 ASSERT (((A) & (~0xfffffff | (M))) == 0)
36 Converts a PCI Library Address to a ESAL PCI Service Address.
37 Based on SAL Spec 3.2, there are two SAL PCI Address:
40 Bits 0..7 - Register address
41 Bits 8..10 - Function number
42 Bits 11..15 - Device number
43 Bits 16..23 - Bus number
44 Bits 24..31 - PCI segment group
45 Bits 32..63 - Reserved (0)
48 Bits 0..7 - Register address
49 Bits 8..11 - Extended Register address
50 Bits 12..14 - Function number
51 Bits 15..19 - Device number
52 Bits 20..27 - Bus number
53 Bits 28..43 - PCI segment group
54 Bits 44..63 - Reserved (0)
56 @param A The PCI Library Address to convert.
59 #define CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0(Address) ((((Address) >> 4) & 0x00ffff00) | ((Address) & 0xff))
60 #define CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1(Address) (Address)
63 Check a PCI Library Address is a PCI Compatible Address or not.
65 #define IS_PCI_COMPATIBLE_ADDRESS(Address) (((Address) & 0xf00) == 0)
68 Internal worker function to read a PCI configuration register.
70 This function wraps EsalPciConfigRead function of Extended SAL PCI
72 It reads and returns the PCI configuration register specified by Address,
73 the width of data is specified by Width.
75 @param Address Address that encodes the PCI Bus, Device, Function and
77 @param Width Width of data to read
79 @return The value read from the PCI configuration register.
83 DxePciLibEsalReadWorker (
88 SAL_RETURN_REGS Return
;
90 if (IS_PCI_COMPATIBLE_ADDRESS(Address
)) {
92 EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO
,
93 EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI
,
94 SalPciConfigReadFunctionId
,
95 CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0 (Address
),
97 EFI_SAL_PCI_COMPATIBLE_ADDRESS
,
105 EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO
,
106 EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI
,
107 SalPciConfigReadFunctionId
,
108 CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1 (Address
),
110 EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS
,
118 return (UINT32
) Return
.r9
;
122 Internal worker function to writes a PCI configuration register.
124 This function wraps EsalPciConfigWrite function of Extended SAL PCI
126 It writes the PCI configuration register specified by Address with the
127 value specified by Data. The width of data is specifed by Width.
130 @param Address Address that encodes the PCI Bus, Device, Function and
132 @param Width Width of data to write
133 @param Data The value to write.
135 @return The value written to the PCI configuration register.
139 DxePciLibEsalWriteWorker (
145 if (IS_PCI_COMPATIBLE_ADDRESS(Address
)) {
147 EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO
,
148 EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI
,
149 SalPciConfigWriteFunctionId
,
150 CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0 (Address
),
153 EFI_SAL_PCI_COMPATIBLE_ADDRESS
,
160 EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO
,
161 EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI
,
162 SalPciConfigWriteFunctionId
,
163 CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1 (Address
),
166 EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS
,
177 Register a PCI device so PCI configuration registers may be accessed after
178 SetVirtualAddressMap().
180 If Address > 0x0FFFFFFF, then ASSERT().
182 @param Address Address that encodes the PCI Bus, Device, Function and
185 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
186 @retval RETURN_UNSUPPORTED An attempt was made to call this function
187 after ExitBootServices().
188 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
189 at runtime could not be mapped.
190 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
191 complete the registration.
196 PciRegisterForRuntimeAccess (
200 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
201 return RETURN_SUCCESS
;
205 Reads an 8-bit PCI configuration register.
207 Reads and returns the 8-bit PCI configuration register specified by Address.
208 This function must guarantee that all PCI read and write operations are
211 If Address > 0x0FFFFFFF, then ASSERT().
213 @param Address Address that encodes the PCI Bus, Device, Function and
216 @return The value read from the PCI configuration register.
225 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
227 return (UINT8
) DxePciLibEsalReadWorker (Address
, 1);
231 Writes an 8-bit PCI configuration register.
233 Writes the 8-bit PCI configuration register specified by Address with the
234 value specified by Value. Value is returned. This function must guarantee
235 that all PCI read and write operations are serialized.
237 If Address > 0x0FFFFFFF, then ASSERT().
239 @param Address Address that encodes the PCI Bus, Device, Function and
241 @param Data The value to write.
243 @return The value written to the PCI configuration register.
253 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
255 return (UINT8
) DxePciLibEsalWriteWorker (Address
, 1, Data
);
259 Performs a bitwise OR of an 8-bit PCI configuration register with
262 Reads the 8-bit PCI configuration register specified by Address, performs a
263 bitwise OR between the read result and the value specified by
264 OrData, and writes the result to the 8-bit PCI configuration register
265 specified by Address. The value written to the PCI configuration register is
266 returned. This function must guarantee that all PCI read and write operations
269 If Address > 0x0FFFFFFF, then ASSERT().
271 @param Address Address that encodes the PCI Bus, Device, Function and
273 @param OrData The value to OR with the PCI configuration register.
275 @return The value written back to the PCI configuration register.
285 return PciWrite8 (Address
, (UINT8
)(PciRead8 (Address
) | OrData
));
289 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
292 Reads the 8-bit PCI configuration register specified by Address, performs a
293 bitwise AND between the read result and the value specified by AndData, and
294 writes the result to the 8-bit PCI configuration register specified by
295 Address. The value written to the PCI configuration register is returned.
296 This function must guarantee that all PCI read and write operations are
299 If Address > 0x0FFFFFFF, then ASSERT().
301 @param Address Address that encodes the PCI Bus, Device, Function and
303 @param AndData The value to AND with the PCI configuration register.
305 @return The value written back to the PCI configuration register.
315 return PciWrite8 (Address
, (UINT8
)(PciRead8 (Address
) & AndData
));
319 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
320 value, followed a bitwise OR with another 8-bit value.
322 Reads the 8-bit PCI configuration register specified by Address, performs a
323 bitwise AND between the read result and the value specified by AndData,
324 performs a bitwise OR between the result of the AND operation and
325 the value specified by OrData, and writes the result to the 8-bit PCI
326 configuration register specified by Address. The value written to the PCI
327 configuration register is returned. This function must guarantee that all PCI
328 read and write operations are serialized.
330 If Address > 0x0FFFFFFF, then ASSERT().
332 @param Address Address that encodes the PCI Bus, Device, Function and
334 @param AndData The value to AND with the PCI configuration register.
335 @param OrData The value to OR with the result of the AND operation.
337 @return The value written back to the PCI configuration register.
348 return PciWrite8 (Address
, (UINT8
)((PciRead8 (Address
) & AndData
) | OrData
));
352 Reads a bit field of a PCI configuration register.
354 Reads the bit field in an 8-bit PCI configuration register. The bit field is
355 specified by the StartBit and the EndBit. The value of the bit field is
358 If Address > 0x0FFFFFFF, then ASSERT().
359 If StartBit is greater than 7, then ASSERT().
360 If EndBit is greater than 7, then ASSERT().
361 If EndBit is less than StartBit, then ASSERT().
363 @param Address PCI configuration register to read.
364 @param StartBit The ordinal of the least significant bit in the bit field.
366 @param EndBit The ordinal of the most significant bit in the bit field.
369 @return The value of the bit field read from the PCI configuration register.
380 return BitFieldRead8 (PciRead8 (Address
), StartBit
, EndBit
);
384 Writes a bit field to a PCI configuration register.
386 Writes Value to the bit field of the PCI configuration register. The bit
387 field is specified by the StartBit and the EndBit. All other bits in the
388 destination PCI configuration register are preserved. The new value of the
389 8-bit register is returned.
391 If Address > 0x0FFFFFFF, then ASSERT().
392 If StartBit is greater than 7, then ASSERT().
393 If EndBit is greater than 7, then ASSERT().
394 If EndBit is less than StartBit, then ASSERT().
396 @param Address PCI configuration register to write.
397 @param StartBit The ordinal of the least significant bit in the bit field.
399 @param EndBit The ordinal of the most significant bit in the bit field.
401 @param Value New value of the bit field.
403 @return The value written back to the PCI configuration register.
417 BitFieldWrite8 (PciRead8 (Address
), StartBit
, EndBit
, Value
)
422 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
423 writes the result back to the bit field in the 8-bit port.
425 Reads the 8-bit PCI configuration register specified by Address, performs a
426 bitwise OR between the read result and the value specified by
427 OrData, and writes the result to the 8-bit PCI configuration register
428 specified by Address. The value written to the PCI configuration register is
429 returned. This function must guarantee that all PCI read and write operations
430 are serialized. Extra left bits in OrData are stripped.
432 If Address > 0x0FFFFFFF, then ASSERT().
433 If StartBit is greater than 7, then ASSERT().
434 If EndBit is greater than 7, then ASSERT().
435 If EndBit is less than StartBit, then ASSERT().
437 @param Address PCI configuration register to write.
438 @param StartBit The ordinal of the least significant bit in the bit field.
440 @param EndBit The ordinal of the most significant bit in the bit field.
442 @param OrData The value to OR with the PCI configuration register.
444 @return The value written back to the PCI configuration register.
458 BitFieldOr8 (PciRead8 (Address
), StartBit
, EndBit
, OrData
)
463 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
464 AND, and writes the result back to the bit field in the 8-bit register.
466 Reads the 8-bit PCI configuration register specified by Address, performs a
467 bitwise AND between the read result and the value specified by AndData, and
468 writes the result to the 8-bit PCI configuration register specified by
469 Address. The value written to the PCI configuration register is returned.
470 This function must guarantee that all PCI read and write operations are
471 serialized. Extra left bits in AndData are stripped.
473 If Address > 0x0FFFFFFF, then ASSERT().
474 If StartBit is greater than 7, then ASSERT().
475 If EndBit is greater than 7, then ASSERT().
476 If EndBit is less than StartBit, then ASSERT().
478 @param Address PCI configuration register to write.
479 @param StartBit The ordinal of the least significant bit in the bit field.
481 @param EndBit The ordinal of the most significant bit in the bit field.
483 @param AndData The value to AND with the PCI configuration register.
485 @return The value written back to the PCI configuration register.
499 BitFieldAnd8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
)
504 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
505 bitwise OR, and writes the result back to the bit field in the
508 Reads the 8-bit PCI configuration register specified by Address, performs a
509 bitwise AND followed by a bitwise OR between the read result and
510 the value specified by AndData, and writes the result to the 8-bit PCI
511 configuration register specified by Address. The value written to the PCI
512 configuration register is returned. This function must guarantee that all PCI
513 read and write operations are serialized. Extra left bits in both AndData and
516 If Address > 0x0FFFFFFF, then ASSERT().
517 If StartBit is greater than 7, then ASSERT().
518 If EndBit is greater than 7, then ASSERT().
519 If EndBit is less than StartBit, then ASSERT().
521 @param Address PCI configuration register to write.
522 @param StartBit The ordinal of the least significant bit in the bit field.
524 @param EndBit The ordinal of the most significant bit in the bit field.
526 @param AndData The value to AND with the PCI configuration register.
527 @param OrData The value to OR with the result of the AND operation.
529 @return The value written back to the PCI configuration register.
534 PciBitFieldAndThenOr8 (
544 BitFieldAndThenOr8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
, OrData
)
549 Reads a 16-bit PCI configuration register.
551 Reads and returns the 16-bit PCI configuration register specified by Address.
552 This function must guarantee that all PCI read and write operations are
555 If Address > 0x0FFFFFFF, then ASSERT().
556 If Address is not aligned on a 16-bit boundary, then ASSERT().
558 @param Address Address that encodes the PCI Bus, Device, Function and
561 @return The value read from the PCI configuration register.
570 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
572 return (UINT16
) DxePciLibEsalReadWorker (Address
, 2);
576 Writes a 16-bit PCI configuration register.
578 Writes the 16-bit PCI configuration register specified by Address with the
579 value specified by Value. Value is returned. This function must guarantee
580 that all PCI read and write operations are serialized.
582 If Address > 0x0FFFFFFF, then ASSERT().
583 If Address is not aligned on a 16-bit boundary, then ASSERT().
585 @param Address Address that encodes the PCI Bus, Device, Function and
587 @param Data The value to write.
589 @return The value written to the PCI configuration register.
599 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
601 return (UINT16
) DxePciLibEsalWriteWorker (Address
, 2, Data
);
605 Performs a bitwise OR of a 16-bit PCI configuration register with
608 Reads the 16-bit PCI configuration register specified by Address, performs a
609 bitwise OR between the read result and the value specified by
610 OrData, and writes the result to the 16-bit PCI configuration register
611 specified by Address. The value written to the PCI configuration register is
612 returned. This function must guarantee that all PCI read and write operations
615 If Address > 0x0FFFFFFF, then ASSERT().
616 If Address is not aligned on a 16-bit boundary, then ASSERT().
618 @param Address Address that encodes the PCI Bus, Device, Function and
620 @param OrData The value to OR with the PCI configuration register.
622 @return The value written back to the PCI configuration register.
632 return PciWrite16 (Address
, (UINT16
)(PciRead16 (Address
) | OrData
));
636 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
639 Reads the 16-bit PCI configuration register specified by Address, performs a
640 bitwise AND between the read result and the value specified by AndData, and
641 writes the result to the 16-bit PCI configuration register specified by
642 Address. The value written to the PCI configuration register is returned.
643 This function must guarantee that all PCI read and write operations are
646 If Address > 0x0FFFFFFF, then ASSERT().
647 If Address is not aligned on a 16-bit boundary, then ASSERT().
649 @param Address Address that encodes the PCI Bus, Device, Function and
651 @param AndData The value to AND with the PCI configuration register.
653 @return The value written back to the PCI configuration register.
663 return PciWrite16 (Address
, (UINT16
)(PciRead16 (Address
) & AndData
));
667 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
668 value, followed a bitwise OR with another 16-bit value.
670 Reads the 16-bit PCI configuration register specified by Address, performs a
671 bitwise AND between the read result and the value specified by AndData,
672 performs a bitwise OR between the result of the AND operation and
673 the value specified by OrData, and writes the result to the 16-bit PCI
674 configuration register specified by Address. The value written to the PCI
675 configuration register is returned. This function must guarantee that all PCI
676 read and write operations are serialized.
678 If Address > 0x0FFFFFFF, then ASSERT().
679 If Address is not aligned on a 16-bit boundary, then ASSERT().
681 @param Address Address that encodes the PCI Bus, Device, Function and
683 @param AndData The value to AND with the PCI configuration register.
684 @param OrData The value to OR with the result of the AND operation.
686 @return The value written back to the PCI configuration register.
697 return PciWrite16 (Address
, (UINT16
)((PciRead16 (Address
) & AndData
) | OrData
));
701 Reads a bit field of a PCI configuration register.
703 Reads the bit field in a 16-bit PCI configuration register. The bit field is
704 specified by the StartBit and the EndBit. The value of the bit field is
707 If Address > 0x0FFFFFFF, then ASSERT().
708 If Address is not aligned on a 16-bit boundary, then ASSERT().
709 If StartBit is greater than 15, then ASSERT().
710 If EndBit is greater than 15, then ASSERT().
711 If EndBit is less than StartBit, then ASSERT().
713 @param Address PCI configuration register to read.
714 @param StartBit The ordinal of the least significant bit in the bit field.
716 @param EndBit The ordinal of the most significant bit in the bit field.
719 @return The value of the bit field read from the PCI configuration register.
730 return BitFieldRead16 (PciRead16 (Address
), StartBit
, EndBit
);
734 Writes a bit field to a PCI configuration register.
736 Writes Value to the bit field of the PCI configuration register. The bit
737 field is specified by the StartBit and the EndBit. All other bits in the
738 destination PCI configuration register are preserved. The new value of the
739 16-bit register is returned.
741 If Address > 0x0FFFFFFF, then ASSERT().
742 If Address is not aligned on a 16-bit boundary, then ASSERT().
743 If StartBit is greater than 15, then ASSERT().
744 If EndBit is greater than 15, then ASSERT().
745 If EndBit is less than StartBit, then ASSERT().
747 @param Address PCI configuration register to write.
748 @param StartBit The ordinal of the least significant bit in the bit field.
750 @param EndBit The ordinal of the most significant bit in the bit field.
752 @param Value New value of the bit field.
754 @return The value written back to the PCI configuration register.
768 BitFieldWrite16 (PciRead16 (Address
), StartBit
, EndBit
, Value
)
773 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
774 writes the result back to the bit field in the 16-bit port.
776 Reads the 16-bit PCI configuration register specified by Address, performs a
777 bitwise OR between the read result and the value specified by
778 OrData, and writes the result to the 16-bit PCI configuration register
779 specified by Address. The value written to the PCI configuration register is
780 returned. This function must guarantee that all PCI read and write operations
781 are serialized. Extra left bits in OrData are stripped.
783 If Address > 0x0FFFFFFF, then ASSERT().
784 If Address is not aligned on a 16-bit boundary, then ASSERT().
785 If StartBit is greater than 15, then ASSERT().
786 If EndBit is greater than 15, then ASSERT().
787 If EndBit is less than StartBit, then ASSERT().
789 @param Address PCI configuration register to write.
790 @param StartBit The ordinal of the least significant bit in the bit field.
792 @param EndBit The ordinal of the most significant bit in the bit field.
794 @param OrData The value to OR with the PCI configuration register.
796 @return The value written back to the PCI configuration register.
810 BitFieldOr16 (PciRead16 (Address
), StartBit
, EndBit
, OrData
)
815 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
816 AND, and writes the result back to the bit field in the 16-bit register.
818 Reads the 16-bit PCI configuration register specified by Address, performs a
819 bitwise AND between the read result and the value specified by AndData, and
820 writes the result to the 16-bit PCI configuration register specified by
821 Address. The value written to the PCI configuration register is returned.
822 This function must guarantee that all PCI read and write operations are
823 serialized. Extra left bits in AndData are stripped.
825 If Address > 0x0FFFFFFF, then ASSERT().
826 If Address is not aligned on a 16-bit boundary, then ASSERT().
827 If StartBit is greater than 15, then ASSERT().
828 If EndBit is greater than 15, then ASSERT().
829 If EndBit is less than StartBit, then ASSERT().
831 @param Address PCI configuration register to write.
832 @param StartBit The ordinal of the least significant bit in the bit field.
834 @param EndBit The ordinal of the most significant bit in the bit field.
836 @param AndData The value to AND with the PCI configuration register.
838 @return The value written back to the PCI configuration register.
852 BitFieldAnd16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
)
857 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
858 bitwise OR, and writes the result back to the bit field in the
861 Reads the 16-bit PCI configuration register specified by Address, performs a
862 bitwise AND followed by a bitwise OR between the read result and
863 the value specified by AndData, and writes the result to the 16-bit PCI
864 configuration register specified by Address. The value written to the PCI
865 configuration register is returned. This function must guarantee that all PCI
866 read and write operations are serialized. Extra left bits in both AndData and
869 If Address > 0x0FFFFFFF, then ASSERT().
870 If Address is not aligned on a 16-bit boundary, then ASSERT().
871 If StartBit is greater than 15, then ASSERT().
872 If EndBit is greater than 15, then ASSERT().
873 If EndBit is less than StartBit, then ASSERT().
875 @param Address PCI configuration register to write.
876 @param StartBit The ordinal of the least significant bit in the bit field.
878 @param EndBit The ordinal of the most significant bit in the bit field.
880 @param AndData The value to AND with the PCI configuration register.
881 @param OrData The value to OR with the result of the AND operation.
883 @return The value written back to the PCI configuration register.
888 PciBitFieldAndThenOr16 (
898 BitFieldAndThenOr16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
, OrData
)
903 Reads a 32-bit PCI configuration register.
905 Reads and returns the 32-bit PCI configuration register specified by Address.
906 This function must guarantee that all PCI read and write operations are
909 If Address > 0x0FFFFFFF, then ASSERT().
910 If Address is not aligned on a 32-bit boundary, then ASSERT().
912 @param Address Address that encodes the PCI Bus, Device, Function and
915 @return The value read from the PCI configuration register.
924 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
926 return DxePciLibEsalReadWorker (Address
, 4);
930 Writes a 32-bit PCI configuration register.
932 Writes the 32-bit PCI configuration register specified by Address with the
933 value specified by Value. Value is returned. This function must guarantee
934 that all PCI read and write operations are serialized.
936 If Address > 0x0FFFFFFF, then ASSERT().
937 If Address is not aligned on a 32-bit boundary, then ASSERT().
939 @param Address Address that encodes the PCI Bus, Device, Function and
941 @param Data The value to write.
943 @return The value written to the PCI configuration register.
953 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
955 return DxePciLibEsalWriteWorker (Address
, 4, Data
);
959 Performs a bitwise OR of a 32-bit PCI configuration register with
962 Reads the 32-bit PCI configuration register specified by Address, performs a
963 bitwise OR between the read result and the value specified by
964 OrData, and writes the result to the 32-bit PCI configuration register
965 specified by Address. The value written to the PCI configuration register is
966 returned. This function must guarantee that all PCI read and write operations
969 If Address > 0x0FFFFFFF, then ASSERT().
970 If Address is not aligned on a 32-bit boundary, then ASSERT().
972 @param Address Address that encodes the PCI Bus, Device, Function and
974 @param OrData The value to OR with the PCI configuration register.
976 @return The value written back to the PCI configuration register.
986 return PciWrite32 (Address
, PciRead32 (Address
) | OrData
);
990 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
993 Reads the 32-bit PCI configuration register specified by Address, performs a
994 bitwise AND between the read result and the value specified by AndData, and
995 writes the result to the 32-bit PCI configuration register specified by
996 Address. The value written to the PCI configuration register is returned.
997 This function must guarantee that all PCI read and write operations are
1000 If Address > 0x0FFFFFFF, then ASSERT().
1001 If Address is not aligned on a 32-bit boundary, then ASSERT().
1003 @param Address Address that encodes the PCI Bus, Device, Function and
1005 @param AndData The value to AND with the PCI configuration register.
1007 @return The value written back to the PCI configuration register.
1017 return PciWrite32 (Address
, PciRead32 (Address
) & AndData
);
1021 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
1022 value, followed a bitwise OR with another 32-bit value.
1024 Reads the 32-bit PCI configuration register specified by Address, performs a
1025 bitwise AND between the read result and the value specified by AndData,
1026 performs a bitwise OR between the result of the AND operation and
1027 the value specified by OrData, and writes the result to the 32-bit PCI
1028 configuration register specified by Address. The value written to the PCI
1029 configuration register is returned. This function must guarantee that all PCI
1030 read and write operations are serialized.
1032 If Address > 0x0FFFFFFF, then ASSERT().
1033 If Address is not aligned on a 32-bit boundary, then ASSERT().
1035 @param Address Address that encodes the PCI Bus, Device, Function and
1037 @param AndData The value to AND with the PCI configuration register.
1038 @param OrData The value to OR with the result of the AND operation.
1040 @return The value written back to the PCI configuration register.
1051 return PciWrite32 (Address
, (PciRead32 (Address
) & AndData
) | OrData
);
1055 Reads a bit field of a PCI configuration register.
1057 Reads the bit field in a 32-bit PCI configuration register. The bit field is
1058 specified by the StartBit and the EndBit. The value of the bit field is
1061 If Address > 0x0FFFFFFF, then ASSERT().
1062 If Address is not aligned on a 32-bit boundary, then ASSERT().
1063 If StartBit is greater than 31, then ASSERT().
1064 If EndBit is greater than 31, then ASSERT().
1065 If EndBit is less than StartBit, then ASSERT().
1067 @param Address PCI configuration register to read.
1068 @param StartBit The ordinal of the least significant bit in the bit field.
1070 @param EndBit The ordinal of the most significant bit in the bit field.
1073 @return The value of the bit field read from the PCI configuration register.
1084 return BitFieldRead32 (PciRead32 (Address
), StartBit
, EndBit
);
1088 Writes a bit field to a PCI configuration register.
1090 Writes Value to the bit field of the PCI configuration register. The bit
1091 field is specified by the StartBit and the EndBit. All other bits in the
1092 destination PCI configuration register are preserved. The new value of the
1093 32-bit register is returned.
1095 If Address > 0x0FFFFFFF, then ASSERT().
1096 If Address is not aligned on a 32-bit boundary, then ASSERT().
1097 If StartBit is greater than 31, then ASSERT().
1098 If EndBit is greater than 31, then ASSERT().
1099 If EndBit is less than StartBit, then ASSERT().
1101 @param Address PCI configuration register to write.
1102 @param StartBit The ordinal of the least significant bit in the bit field.
1104 @param EndBit The ordinal of the most significant bit in the bit field.
1106 @param Value New value of the bit field.
1108 @return The value written back to the PCI configuration register.
1113 PciBitFieldWrite32 (
1122 BitFieldWrite32 (PciRead32 (Address
), StartBit
, EndBit
, Value
)
1127 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1128 writes the result back to the bit field in the 32-bit port.
1130 Reads the 32-bit PCI configuration register specified by Address, performs a
1131 bitwise OR between the read result and the value specified by
1132 OrData, and writes the result to the 32-bit PCI configuration register
1133 specified by Address. The value written to the PCI configuration register is
1134 returned. This function must guarantee that all PCI read and write operations
1135 are serialized. Extra left bits in OrData are stripped.
1137 If Address > 0x0FFFFFFF, then ASSERT().
1138 If Address is not aligned on a 32-bit boundary, then ASSERT().
1139 If StartBit is greater than 31, then ASSERT().
1140 If EndBit is greater than 31, then ASSERT().
1141 If EndBit is less than StartBit, then ASSERT().
1143 @param Address PCI configuration register to write.
1144 @param StartBit The ordinal of the least significant bit in the bit field.
1146 @param EndBit The ordinal of the most significant bit in the bit field.
1148 @param OrData The value to OR with the PCI configuration register.
1150 @return The value written back to the PCI configuration register.
1164 BitFieldOr32 (PciRead32 (Address
), StartBit
, EndBit
, OrData
)
1169 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1170 AND, and writes the result back to the bit field in the 32-bit register.
1172 Reads the 32-bit PCI configuration register specified by Address, performs a
1173 bitwise AND between the read result and the value specified by AndData, and
1174 writes the result to the 32-bit PCI configuration register specified by
1175 Address. The value written to the PCI configuration register is returned.
1176 This function must guarantee that all PCI read and write operations are
1177 serialized. Extra left bits in AndData are stripped.
1179 If Address > 0x0FFFFFFF, then ASSERT().
1180 If Address is not aligned on a 32-bit boundary, then ASSERT().
1181 If StartBit is greater than 31, then ASSERT().
1182 If EndBit is greater than 31, then ASSERT().
1183 If EndBit is less than StartBit, then ASSERT().
1185 @param Address PCI configuration register to write.
1186 @param StartBit The ordinal of the least significant bit in the bit field.
1188 @param EndBit The ordinal of the most significant bit in the bit field.
1190 @param AndData The value to AND with the PCI configuration register.
1192 @return The value written back to the PCI configuration register.
1206 BitFieldAnd32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
)
1211 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1212 bitwise OR, and writes the result back to the bit field in the
1215 Reads the 32-bit PCI configuration register specified by Address, performs a
1216 bitwise AND followed by a bitwise OR between the read result and
1217 the value specified by AndData, and writes the result to the 32-bit PCI
1218 configuration register specified by Address. The value written to the PCI
1219 configuration register is returned. This function must guarantee that all PCI
1220 read and write operations are serialized. Extra left bits in both AndData and
1221 OrData are stripped.
1223 If Address > 0x0FFFFFFF, then ASSERT().
1224 If Address is not aligned on a 32-bit boundary, then ASSERT().
1225 If StartBit is greater than 31, then ASSERT().
1226 If EndBit is greater than 31, then ASSERT().
1227 If EndBit is less than StartBit, then ASSERT().
1229 @param Address PCI configuration register to write.
1230 @param StartBit The ordinal of the least significant bit in the bit field.
1232 @param EndBit The ordinal of the most significant bit in the bit field.
1234 @param AndData The value to AND with the PCI configuration register.
1235 @param OrData The value to OR with the result of the AND operation.
1237 @return The value written back to the PCI configuration register.
1242 PciBitFieldAndThenOr32 (
1252 BitFieldAndThenOr32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
, OrData
)
1257 Reads a range of PCI configuration registers into a caller supplied buffer.
1259 Reads the range of PCI configuration registers specified by StartAddress and
1260 Size into the buffer specified by Buffer. This function only allows the PCI
1261 configuration registers from a single PCI function to be read. Size is
1262 returned. When possible 32-bit PCI configuration read cycles are used to read
1263 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1264 and 16-bit PCI configuration read cycles may be used at the beginning and the
1267 If StartAddress > 0x0FFFFFFF, then ASSERT().
1268 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1269 If Size > 0 and Buffer is NULL, then ASSERT().
1271 @param StartAddress Starting address that encodes the PCI Bus, Device,
1272 Function and Register.
1273 @param Size Size in bytes of the transfer.
1274 @param Buffer Pointer to a buffer receiving the data read.
1282 IN UINTN StartAddress
,
1289 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1290 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x100);
1296 ASSERT (Buffer
!= NULL
);
1299 // Save Size for return
1303 if ((StartAddress
& 1) != 0) {
1305 // Read a byte if StartAddress is byte aligned
1307 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1308 StartAddress
+= sizeof (UINT8
);
1309 Size
-= sizeof (UINT8
);
1310 Buffer
= (UINT8
*)Buffer
+ 1;
1313 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1315 // Read a word if StartAddress is word aligned
1317 *(volatile UINT16
*)Buffer
= PciRead16 (StartAddress
);
1318 StartAddress
+= sizeof (UINT16
);
1319 Size
-= sizeof (UINT16
);
1320 Buffer
= (UINT16
*)Buffer
+ 1;
1323 while (Size
>= sizeof (UINT32
)) {
1325 // Read as many double words as possible
1327 *(volatile UINT32
*)Buffer
= PciRead32 (StartAddress
);
1328 StartAddress
+= sizeof (UINT32
);
1329 Size
-= sizeof (UINT32
);
1330 Buffer
= (UINT32
*)Buffer
+ 1;
1333 if (Size
>= sizeof (UINT16
)) {
1335 // Read the last remaining word if exist
1337 *(volatile UINT16
*)Buffer
= PciRead16 (StartAddress
);
1338 StartAddress
+= sizeof (UINT16
);
1339 Size
-= sizeof (UINT16
);
1340 Buffer
= (UINT16
*)Buffer
+ 1;
1343 if (Size
>= sizeof (UINT8
)) {
1345 // Read the last remaining byte if exist
1347 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1354 Copies the data in a caller supplied buffer to a specified range of PCI
1355 configuration space.
1357 Writes the range of PCI configuration registers specified by StartAddress and
1358 Size from the buffer specified by Buffer. This function only allows the PCI
1359 configuration registers from a single PCI function to be written. Size is
1360 returned. When possible 32-bit PCI configuration write cycles are used to
1361 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1362 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1363 and the end of the range.
1365 If StartAddress > 0x0FFFFFFF, then ASSERT().
1366 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1367 If Size > 0 and Buffer is NULL, then ASSERT().
1369 @param StartAddress Starting address that encodes the PCI Bus, Device,
1370 Function and Register.
1371 @param Size Size in bytes of the transfer.
1372 @param Buffer Pointer to a buffer containing the data to write.
1380 IN UINTN StartAddress
,
1387 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1388 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x100);
1394 ASSERT (Buffer
!= NULL
);
1397 // Save Size for return
1401 if ((StartAddress
& 1) != 0) {
1403 // Write a byte if StartAddress is byte aligned
1405 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1406 StartAddress
+= sizeof (UINT8
);
1407 Size
-= sizeof (UINT8
);
1408 Buffer
= (UINT8
*)Buffer
+ 1;
1411 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1413 // Write a word if StartAddress is word aligned
1415 PciWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1416 StartAddress
+= sizeof (UINT16
);
1417 Size
-= sizeof (UINT16
);
1418 Buffer
= (UINT16
*)Buffer
+ 1;
1421 while (Size
>= sizeof (UINT32
)) {
1423 // Write as many double words as possible
1425 PciWrite32 (StartAddress
, *(UINT32
*)Buffer
);
1426 StartAddress
+= sizeof (UINT32
);
1427 Size
-= sizeof (UINT32
);
1428 Buffer
= (UINT32
*)Buffer
+ 1;
1431 if (Size
>= sizeof (UINT16
)) {
1433 // Write the last remaining word if exist
1435 PciWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1436 StartAddress
+= sizeof (UINT16
);
1437 Size
-= sizeof (UINT16
);
1438 Buffer
= (UINT16
*)Buffer
+ 1;
1441 if (Size
>= sizeof (UINT8
)) {
1443 // Write the last remaining byte if exist
1445 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);