2 PCI Library using PCI CFG2 PPI.
4 Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials are
6 licensed and made available under the terms and conditions of
7 the BSD License which accompanies this distribution. The full
8 text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php.
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #include <Ppi/PciCfg2.h>
20 #include <Library/PciLib.h>
21 #include <Library/BaseLib.h>
22 #include <Library/PeiServicesTablePointerLib.h>
23 #include <Library/DebugLib.h>
24 #include <Library/PeiServicesLib.h>
27 Assert the validity of a PCI address. A valid PCI address should contain 1's
28 only in the low 28 bits.
30 @param A The address to validate.
31 @param M Additional bits to assert to be zero.
34 #define ASSERT_INVALID_PCI_ADDRESS(A,M) \
35 ASSERT (((A) & (~0xfffffff | (M))) == 0)
38 Translate PCI Lib address into format of PCI CFG2 PPI.
40 @param A The address that encodes the PCI Bus, Device, Function and
44 #define PCI_TO_PCICFG2_ADDRESS(A) \
45 ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))
48 Internal worker function to read a PCI configuration register.
50 This function wraps EFI_PEI_PCI_CFG2_PPI.Read() service.
51 It reads and returns the PCI configuration register specified by Address,
52 the width of data is specified by Width.
54 @param Address The address that encodes the PCI Bus, Device, Function and
56 @param Width The width of data to read
58 @return The value read from the PCI configuration register.
62 PeiPciLibPciCfg2ReadWorker (
64 IN EFI_PEI_PCI_CFG_PPI_WIDTH Width
69 CONST EFI_PEI_PCI_CFG2_PPI
*PciCfg2Ppi
;
70 UINT64 PciCfg2Address
;
72 Status
= PeiServicesLocatePpi (&gEfiPciCfg2PpiGuid
, 0, NULL
, (VOID
**) &PciCfg2Ppi
);
73 ASSERT_EFI_ERROR (Status
);
74 ASSERT (PciCfg2Ppi
!= NULL
);
76 PciCfg2Address
= PCI_TO_PCICFG2_ADDRESS (Address
);
78 GetPeiServicesTablePointer (),
89 Internal worker function to writes a PCI configuration register.
91 This function wraps EFI_PEI_PCI_CFG2_PPI.Write() service.
92 It writes the PCI configuration register specified by Address with the
93 value specified by Data. The width of data is specifed by Width.
96 @param Address The address that encodes the PCI Bus, Device, Function and
98 @param Width The width of data to write
99 @param Data The value to write.
101 @return The value written to the PCI configuration register.
105 PeiPciLibPciCfg2WriteWorker (
107 IN EFI_PEI_PCI_CFG_PPI_WIDTH Width
,
112 CONST EFI_PEI_PCI_CFG2_PPI
*PciCfg2Ppi
;
113 UINT64 PciCfg2Address
;
115 Status
= PeiServicesLocatePpi (&gEfiPciCfg2PpiGuid
, 0, NULL
, (VOID
**) &PciCfg2Ppi
);
116 ASSERT_EFI_ERROR (Status
);
117 ASSERT (PciCfg2Ppi
!= NULL
);
119 PciCfg2Address
= PCI_TO_PCICFG2_ADDRESS (Address
);
121 GetPeiServicesTablePointer (),
132 Registers a PCI device so PCI configuration registers may be accessed after
133 SetVirtualAddressMap().
135 Registers the PCI device specified by Address so all the PCI configuration registers
136 associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
138 If Address > 0x0FFFFFFF, then ASSERT().
140 @param Address The address that encodes the PCI Bus, Device, Function and
143 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
144 @retval RETURN_UNSUPPORTED An attempt was made to call this function
145 after ExitBootServices().
146 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
147 at runtime could not be mapped.
148 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
149 complete the registration.
154 PciRegisterForRuntimeAccess (
158 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
159 return RETURN_UNSUPPORTED
;
163 Reads an 8-bit PCI configuration register.
165 Reads and returns the 8-bit PCI configuration register specified by Address.
166 This function must guarantee that all PCI read and write operations are
169 If Address > 0x0FFFFFFF, then ASSERT().
171 @param Address The address that encodes the PCI Bus, Device, Function and
174 @return The read value from the PCI configuration register.
183 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
185 return (UINT8
) PeiPciLibPciCfg2ReadWorker (Address
, EfiPeiPciCfgWidthUint8
);
189 Writes an 8-bit PCI configuration register.
191 Writes the 8-bit PCI configuration register specified by Address with the
192 value specified by Value. Value is returned. This function must guarantee
193 that all PCI read and write operations are serialized.
195 If Address > 0x0FFFFFFF, then ASSERT().
197 @param Address The address that encodes the PCI Bus, Device, Function and
199 @param Value The value to write.
201 @return The value written to the PCI configuration register.
211 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
213 return (UINT8
) PeiPciLibPciCfg2WriteWorker (Address
, EfiPeiPciCfgWidthUint8
, Value
);
217 Performs a bitwise OR of an 8-bit PCI configuration register with
220 Reads the 8-bit PCI configuration register specified by Address, performs a
221 bitwise OR between the read result and the value specified by
222 OrData, and writes the result to the 8-bit PCI configuration register
223 specified by Address. The value written to the PCI configuration register is
224 returned. This function must guarantee that all PCI read and write operations
227 If Address > 0x0FFFFFFF, then ASSERT().
229 @param Address The address that encodes the PCI Bus, Device, Function and
231 @param OrData The value to OR with the PCI configuration register.
233 @return The value written back to the PCI configuration register.
243 return PciWrite8 (Address
, (UINT8
) (PciRead8 (Address
) | OrData
));
247 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
250 Reads the 8-bit PCI configuration register specified by Address, performs a
251 bitwise AND between the read result and the value specified by AndData, and
252 writes the result to the 8-bit PCI configuration register specified by
253 Address. The value written to the PCI configuration register is returned.
254 This function must guarantee that all PCI read and write operations are
257 If Address > 0x0FFFFFFF, then ASSERT().
259 @param Address The address that encodes the PCI Bus, Device, Function and
261 @param AndData The value to AND with the PCI configuration register.
263 @return The value written back to the PCI configuration register.
273 return PciWrite8 (Address
, (UINT8
) (PciRead8 (Address
) & AndData
));
277 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
278 value, followed a bitwise OR with another 8-bit value.
280 Reads the 8-bit PCI configuration register specified by Address, performs a
281 bitwise AND between the read result and the value specified by AndData,
282 performs a bitwise OR between the result of the AND operation and
283 the value specified by OrData, and writes the result to the 8-bit PCI
284 configuration register specified by Address. The value written to the PCI
285 configuration register is returned. This function must guarantee that all PCI
286 read and write operations are serialized.
288 If Address > 0x0FFFFFFF, then ASSERT().
290 @param Address The address that encodes the PCI Bus, Device, Function and
292 @param AndData The value to AND with the PCI configuration register.
293 @param OrData The value to OR with the result of the AND operation.
295 @return The value written back to the PCI configuration register.
306 return PciWrite8 (Address
, (UINT8
) ((PciRead8 (Address
) & AndData
) | OrData
));
310 Reads a bit field of a PCI configuration register.
312 Reads the bit field in an 8-bit PCI configuration register. The bit field is
313 specified by the StartBit and the EndBit. The value of the bit field is
316 If Address > 0x0FFFFFFF, then ASSERT().
317 If StartBit is greater than 7, then ASSERT().
318 If EndBit is greater than 7, then ASSERT().
319 If EndBit is less than StartBit, then ASSERT().
321 @param Address The PCI configuration register to read.
322 @param StartBit The ordinal of the least significant bit in the bit field.
324 @param EndBit The ordinal of the most significant bit in the bit field.
327 @return The value of the bit field read from the PCI configuration register.
338 return BitFieldRead8 (PciRead8 (Address
), StartBit
, EndBit
);
342 Writes a bit field to a PCI configuration register.
344 Writes Value to the bit field of the PCI configuration register. The bit
345 field is specified by the StartBit and the EndBit. All other bits in the
346 destination PCI configuration register are preserved. The new value of the
347 8-bit register is returned.
349 If Address > 0x0FFFFFFF, then ASSERT().
350 If StartBit is greater than 7, then ASSERT().
351 If EndBit is greater than 7, then ASSERT().
352 If EndBit is less than StartBit, then ASSERT().
354 @param Address The PCI configuration register to write.
355 @param StartBit The ordinal of the least significant bit in the bit field.
357 @param EndBit The ordinal of the most significant bit in the bit field.
359 @param Value The new value of the bit field.
361 @return The value written back to the PCI configuration register.
375 BitFieldWrite8 (PciRead8 (Address
), StartBit
, EndBit
, Value
)
380 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
381 writes the result back to the bit field in the 8-bit port.
383 Reads the 8-bit PCI configuration register specified by Address, performs a
384 bitwise OR between the read result and the value specified by
385 OrData, and writes the result to the 8-bit PCI configuration register
386 specified by Address. The value written to the PCI configuration register is
387 returned. This function must guarantee that all PCI read and write operations
388 are serialized. Extra left bits in OrData are stripped.
390 If Address > 0x0FFFFFFF, then ASSERT().
391 If StartBit is greater than 7, then ASSERT().
392 If EndBit is greater than 7, then ASSERT().
393 If EndBit is less than StartBit, then ASSERT().
395 @param Address The PCI configuration register to write.
396 @param StartBit The ordinal of the least significant bit in the bit field.
398 @param EndBit The ordinal of the most significant bit in the bit field.
400 @param OrData The value to OR with the PCI configuration register.
402 @return The value written back to the PCI configuration register.
416 BitFieldOr8 (PciRead8 (Address
), StartBit
, EndBit
, OrData
)
421 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
422 AND, and writes the result back to the bit field in the 8-bit register.
424 Reads the 8-bit PCI configuration register specified by Address, performs a
425 bitwise AND between the read result and the value specified by AndData, and
426 writes the result to the 8-bit PCI configuration register specified by
427 Address. The value written to the PCI configuration register is returned.
428 This function must guarantee that all PCI read and write operations are
429 serialized. Extra left bits in AndData are stripped.
431 If Address > 0x0FFFFFFF, then ASSERT().
432 If StartBit is greater than 7, then ASSERT().
433 If EndBit is greater than 7, then ASSERT().
434 If EndBit is less than StartBit, then ASSERT().
436 @param Address The PCI configuration register to write.
437 @param StartBit The ordinal of the least significant bit in the bit field.
439 @param EndBit The ordinal of the most significant bit in the bit field.
441 @param AndData The value to AND with the PCI configuration register.
443 @return The value written back to the PCI configuration register.
457 BitFieldAnd8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
)
462 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
463 bitwise OR, and writes the result back to the bit field in the
466 Reads the 8-bit PCI configuration register specified by Address, performs a
467 bitwise AND followed by a bitwise OR between the read result and
468 the value specified by AndData, and writes the result to the 8-bit PCI
469 configuration register specified by Address. The value written to the PCI
470 configuration register is returned. This function must guarantee that all PCI
471 read and write operations are serialized. Extra left bits in both AndData and
474 If Address > 0x0FFFFFFF, then ASSERT().
475 If StartBit is greater than 7, then ASSERT().
476 If EndBit is greater than 7, then ASSERT().
477 If EndBit is less than StartBit, then ASSERT().
479 @param Address The PCI configuration register to write.
480 @param StartBit The ordinal of the least significant bit in the bit field.
482 @param EndBit The ordinal of the most significant bit in the bit field.
484 @param AndData The value to AND with the PCI configuration register.
485 @param OrData The value to OR with the result of the AND operation.
487 @return The value written back to the PCI configuration register.
492 PciBitFieldAndThenOr8 (
502 BitFieldAndThenOr8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
, OrData
)
507 Reads a 16-bit PCI configuration register.
509 Reads and returns the 16-bit PCI configuration register specified by Address.
510 This function must guarantee that all PCI read and write operations are
513 If Address > 0x0FFFFFFF, then ASSERT().
514 If Address is not aligned on a 16-bit boundary, then ASSERT().
516 @param Address The address that encodes the PCI Bus, Device, Function and
519 @return The read value from the PCI configuration register.
528 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
530 return (UINT16
) PeiPciLibPciCfg2ReadWorker (Address
, EfiPeiPciCfgWidthUint16
);
534 Writes a 16-bit PCI configuration register.
536 Writes the 16-bit PCI configuration register specified by Address with the
537 value specified by Value. Value is returned. This function must guarantee
538 that all PCI read and write operations are serialized.
540 If Address > 0x0FFFFFFF, then ASSERT().
541 If Address is not aligned on a 16-bit boundary, then ASSERT().
543 @param Address The address that encodes the PCI Bus, Device, Function and
545 @param Value The value to write.
547 @return The value written to the PCI configuration register.
557 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
559 return (UINT16
) PeiPciLibPciCfg2WriteWorker (Address
, EfiPeiPciCfgWidthUint16
, Value
);
563 Performs a bitwise OR of a 16-bit PCI configuration register with
566 Reads the 16-bit PCI configuration register specified by Address, performs a
567 bitwise OR between the read result and the value specified by
568 OrData, and writes the result to the 16-bit PCI configuration register
569 specified by Address. The value written to the PCI configuration register is
570 returned. This function must guarantee that all PCI read and write operations
573 If Address > 0x0FFFFFFF, then ASSERT().
574 If Address is not aligned on a 16-bit boundary, then ASSERT().
576 @param Address The address that encodes the PCI Bus, Device, Function and
578 @param OrData The value to OR with the PCI configuration register.
580 @return The value written back to the PCI configuration register.
590 return PciWrite16 (Address
, (UINT16
) (PciRead16 (Address
) | OrData
));
594 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
597 Reads the 16-bit PCI configuration register specified by Address, performs a
598 bitwise AND between the read result and the value specified by AndData, and
599 writes the result to the 16-bit PCI configuration register specified by
600 Address. The value written to the PCI configuration register is returned.
601 This function must guarantee that all PCI read and write operations are
604 If Address > 0x0FFFFFFF, then ASSERT().
605 If Address is not aligned on a 16-bit boundary, then ASSERT().
607 @param Address The address that encodes the PCI Bus, Device, Function and
609 @param AndData The value to AND with the PCI configuration register.
611 @return The value written back to the PCI configuration register.
621 return PciWrite16 (Address
, (UINT16
) (PciRead16 (Address
) & AndData
));
625 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
626 value, followed a bitwise OR with another 16-bit value.
628 Reads the 16-bit PCI configuration register specified by Address, performs a
629 bitwise AND between the read result and the value specified by AndData,
630 performs a bitwise OR between the result of the AND operation and
631 the value specified by OrData, and writes the result to the 16-bit PCI
632 configuration register specified by Address. The value written to the PCI
633 configuration register is returned. This function must guarantee that all PCI
634 read and write operations are serialized.
636 If Address > 0x0FFFFFFF, then ASSERT().
637 If Address is not aligned on a 16-bit boundary, then ASSERT().
639 @param Address The address that encodes the PCI Bus, Device, Function and
641 @param AndData The value to AND with the PCI configuration register.
642 @param OrData The value to OR with the result of the AND operation.
644 @return The value written back to the PCI configuration register.
655 return PciWrite16 (Address
, (UINT16
) ((PciRead16 (Address
) & AndData
) | OrData
));
659 Reads a bit field of a PCI configuration register.
661 Reads the bit field in a 16-bit PCI configuration register. The bit field is
662 specified by the StartBit and the EndBit. The value of the bit field is
665 If Address > 0x0FFFFFFF, then ASSERT().
666 If Address is not aligned on a 16-bit boundary, then ASSERT().
667 If StartBit is greater than 15, then ASSERT().
668 If EndBit is greater than 15, then ASSERT().
669 If EndBit is less than StartBit, then ASSERT().
671 @param Address The PCI configuration register to read.
672 @param StartBit The ordinal of the least significant bit in the bit field.
674 @param EndBit The ordinal of the most significant bit in the bit field.
677 @return The value of the bit field read from the PCI configuration register.
688 return BitFieldRead16 (PciRead16 (Address
), StartBit
, EndBit
);
692 Writes a bit field to a PCI configuration register.
694 Writes Value to the bit field of the PCI configuration register. The bit
695 field is specified by the StartBit and the EndBit. All other bits in the
696 destination PCI configuration register are preserved. The new value of the
697 16-bit register is returned.
699 If Address > 0x0FFFFFFF, then ASSERT().
700 If Address is not aligned on a 16-bit boundary, then ASSERT().
701 If StartBit is greater than 15, then ASSERT().
702 If EndBit is greater than 15, then ASSERT().
703 If EndBit is less than StartBit, then ASSERT().
705 @param Address The PCI configuration register to write.
706 @param StartBit The ordinal of the least significant bit in the bit field.
708 @param EndBit The ordinal of the most significant bit in the bit field.
710 @param Value The new value of the bit field.
712 @return The value written back to the PCI configuration register.
726 BitFieldWrite16 (PciRead16 (Address
), StartBit
, EndBit
, Value
)
731 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
732 writes the result back to the bit field in the 16-bit port.
734 Reads the 16-bit PCI configuration register specified by Address, performs a
735 bitwise OR between the read result and the value specified by
736 OrData, and writes the result to the 16-bit PCI configuration register
737 specified by Address. The value written to the PCI configuration register is
738 returned. This function must guarantee that all PCI read and write operations
739 are serialized. Extra left bits in OrData are stripped.
741 If Address > 0x0FFFFFFF, then ASSERT().
742 If Address is not aligned on a 16-bit boundary, then ASSERT().
743 If StartBit is greater than 15, then ASSERT().
744 If EndBit is greater than 15, then ASSERT().
745 If EndBit is less than StartBit, then ASSERT().
747 @param Address The PCI configuration register to write.
748 @param StartBit The ordinal of the least significant bit in the bit field.
750 @param EndBit The ordinal of the most significant bit in the bit field.
752 @param OrData The value to OR with the PCI configuration register.
754 @return The value written back to the PCI configuration register.
768 BitFieldOr16 (PciRead16 (Address
), StartBit
, EndBit
, OrData
)
773 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
774 AND, and writes the result back to the bit field in the 16-bit register.
776 Reads the 16-bit PCI configuration register specified by Address, performs a
777 bitwise AND between the read result and the value specified by AndData, and
778 writes the result to the 16-bit PCI configuration register specified by
779 Address. The value written to the PCI configuration register is returned.
780 This function must guarantee that all PCI read and write operations are
781 serialized. Extra left bits in AndData are stripped.
783 If Address > 0x0FFFFFFF, then ASSERT().
784 If Address is not aligned on a 16-bit boundary, then ASSERT().
785 If StartBit is greater than 15, then ASSERT().
786 If EndBit is greater than 15, then ASSERT().
787 If EndBit is less than StartBit, then ASSERT().
789 @param Address The PCI configuration register to write.
790 @param StartBit The ordinal of the least significant bit in the bit field.
792 @param EndBit The ordinal of the most significant bit in the bit field.
794 @param AndData The value to AND with the PCI configuration register.
796 @return The value written back to the PCI configuration register.
810 BitFieldAnd16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
)
815 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
816 bitwise OR, and writes the result back to the bit field in the
819 Reads the 16-bit PCI configuration register specified by Address, performs a
820 bitwise AND followed by a bitwise OR between the read result and
821 the value specified by AndData, and writes the result to the 16-bit PCI
822 configuration register specified by Address. The value written to the PCI
823 configuration register is returned. This function must guarantee that all PCI
824 read and write operations are serialized. Extra left bits in both AndData and
827 If Address > 0x0FFFFFFF, then ASSERT().
828 If Address is not aligned on a 16-bit boundary, then ASSERT().
829 If StartBit is greater than 15, then ASSERT().
830 If EndBit is greater than 15, then ASSERT().
831 If EndBit is less than StartBit, then ASSERT().
833 @param Address The PCI configuration register to write.
834 @param StartBit The ordinal of the least significant bit in the bit field.
836 @param EndBit The ordinal of the most significant bit in the bit field.
838 @param AndData The value to AND with the PCI configuration register.
839 @param OrData The value to OR with the result of the AND operation.
841 @return The value written back to the PCI configuration register.
846 PciBitFieldAndThenOr16 (
856 BitFieldAndThenOr16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
, OrData
)
861 Reads a 32-bit PCI configuration register.
863 Reads and returns the 32-bit PCI configuration register specified by Address.
864 This function must guarantee that all PCI read and write operations are
867 If Address > 0x0FFFFFFF, then ASSERT().
868 If Address is not aligned on a 32-bit boundary, then ASSERT().
870 @param Address The address that encodes the PCI Bus, Device, Function and
873 @return The read value from the PCI configuration register.
882 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
884 return PeiPciLibPciCfg2ReadWorker (Address
, EfiPeiPciCfgWidthUint32
);
888 Writes a 32-bit PCI configuration register.
890 Writes the 32-bit PCI configuration register specified by Address with the
891 value specified by Value. Value is returned. This function must guarantee
892 that all PCI read and write operations are serialized.
894 If Address > 0x0FFFFFFF, then ASSERT().
895 If Address is not aligned on a 32-bit boundary, then ASSERT().
897 @param Address The address that encodes the PCI Bus, Device, Function and
899 @param Value The value to write.
901 @return The value written to the PCI configuration register.
911 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
913 return PeiPciLibPciCfg2WriteWorker (Address
, EfiPeiPciCfgWidthUint32
, Value
);
917 Performs a bitwise OR of a 32-bit PCI configuration register with
920 Reads the 32-bit PCI configuration register specified by Address, performs a
921 bitwise OR between the read result and the value specified by
922 OrData, and writes the result to the 32-bit PCI configuration register
923 specified by Address. The value written to the PCI configuration register is
924 returned. This function must guarantee that all PCI read and write operations
927 If Address > 0x0FFFFFFF, then ASSERT().
928 If Address is not aligned on a 32-bit boundary, then ASSERT().
930 @param Address The address that encodes the PCI Bus, Device, Function and
932 @param OrData The value to OR with the PCI configuration register.
934 @return The value written back to the PCI configuration register.
944 return PciWrite32 (Address
, PciRead32 (Address
) | OrData
);
948 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
951 Reads the 32-bit PCI configuration register specified by Address, performs a
952 bitwise AND between the read result and the value specified by AndData, and
953 writes the result to the 32-bit PCI configuration register specified by
954 Address. The value written to the PCI configuration register is returned.
955 This function must guarantee that all PCI read and write operations are
958 If Address > 0x0FFFFFFF, then ASSERT().
959 If Address is not aligned on a 32-bit boundary, then ASSERT().
961 @param Address The address that encodes the PCI Bus, Device, Function and
963 @param AndData The value to AND with the PCI configuration register.
965 @return The value written back to the PCI configuration register.
975 return PciWrite32 (Address
, PciRead32 (Address
) & AndData
);
979 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
980 value, followed a bitwise OR with another 32-bit value.
982 Reads the 32-bit PCI configuration register specified by Address, performs a
983 bitwise AND between the read result and the value specified by AndData,
984 performs a bitwise OR between the result of the AND operation and
985 the value specified by OrData, and writes the result to the 32-bit PCI
986 configuration register specified by Address. The value written to the PCI
987 configuration register is returned. This function must guarantee that all PCI
988 read and write operations are serialized.
990 If Address > 0x0FFFFFFF, then ASSERT().
991 If Address is not aligned on a 32-bit boundary, then ASSERT().
993 @param Address The address that encodes the PCI Bus, Device, Function and
995 @param AndData The value to AND with the PCI configuration register.
996 @param OrData The value to OR with the result of the AND operation.
998 @return The value written back to the PCI configuration register.
1009 return PciWrite32 (Address
, (PciRead32 (Address
) & AndData
) | OrData
);
1013 Reads a bit field of a PCI configuration register.
1015 Reads the bit field in a 32-bit PCI configuration register. The bit field is
1016 specified by the StartBit and the EndBit. The value of the bit field is
1019 If Address > 0x0FFFFFFF, then ASSERT().
1020 If Address is not aligned on a 32-bit boundary, then ASSERT().
1021 If StartBit is greater than 31, then ASSERT().
1022 If EndBit is greater than 31, then ASSERT().
1023 If EndBit is less than StartBit, then ASSERT().
1025 @param Address The PCI configuration register to read.
1026 @param StartBit The ordinal of the least significant bit in the bit field.
1028 @param EndBit The ordinal of the most significant bit in the bit field.
1031 @return The value of the bit field read from the PCI configuration register.
1042 return BitFieldRead32 (PciRead32 (Address
), StartBit
, EndBit
);
1046 Writes a bit field to a PCI configuration register.
1048 Writes Value to the bit field of the PCI configuration register. The bit
1049 field is specified by the StartBit and the EndBit. All other bits in the
1050 destination PCI configuration register are preserved. The new value of the
1051 32-bit register is returned.
1053 If Address > 0x0FFFFFFF, then ASSERT().
1054 If Address is not aligned on a 32-bit boundary, then ASSERT().
1055 If StartBit is greater than 31, then ASSERT().
1056 If EndBit is greater than 31, then ASSERT().
1057 If EndBit is less than StartBit, then ASSERT().
1059 @param Address The PCI configuration register to write.
1060 @param StartBit The ordinal of the least significant bit in the bit field.
1062 @param EndBit The ordinal of the most significant bit in the bit field.
1064 @param Value The new value of the bit field.
1066 @return The value written back to the PCI configuration register.
1071 PciBitFieldWrite32 (
1080 BitFieldWrite32 (PciRead32 (Address
), StartBit
, EndBit
, Value
)
1085 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1086 writes the result back to the bit field in the 32-bit port.
1088 Reads the 32-bit PCI configuration register specified by Address, performs a
1089 bitwise OR between the read result and the value specified by
1090 OrData, and writes the result to the 32-bit PCI configuration register
1091 specified by Address. The value written to the PCI configuration register is
1092 returned. This function must guarantee that all PCI read and write operations
1093 are serialized. Extra left bits in OrData are stripped.
1095 If Address > 0x0FFFFFFF, then ASSERT().
1096 If Address is not aligned on a 32-bit boundary, then ASSERT().
1097 If StartBit is greater than 31, then ASSERT().
1098 If EndBit is greater than 31, then ASSERT().
1099 If EndBit is less than StartBit, then ASSERT().
1101 @param Address The PCI configuration register to write.
1102 @param StartBit The ordinal of the least significant bit in the bit field.
1104 @param EndBit The ordinal of the most significant bit in the bit field.
1106 @param OrData The value to OR with the PCI configuration register.
1108 @return The value written back to the PCI configuration register.
1122 BitFieldOr32 (PciRead32 (Address
), StartBit
, EndBit
, OrData
)
1127 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1128 AND, and writes the result back to the bit field in the 32-bit register.
1130 Reads the 32-bit PCI configuration register specified by Address, performs a
1131 bitwise AND between the read result and the value specified by AndData, and
1132 writes the result to the 32-bit PCI configuration register specified by
1133 Address. The value written to the PCI configuration register is returned.
1134 This function must guarantee that all PCI read and write operations are
1135 serialized. Extra left bits in AndData are stripped.
1137 If Address > 0x0FFFFFFF, then ASSERT().
1138 If Address is not aligned on a 32-bit boundary, then ASSERT().
1139 If StartBit is greater than 31, then ASSERT().
1140 If EndBit is greater than 31, then ASSERT().
1141 If EndBit is less than StartBit, then ASSERT().
1143 @param Address The PCI configuration register to write.
1144 @param StartBit The ordinal of the least significant bit in the bit field.
1146 @param EndBit The ordinal of the most significant bit in the bit field.
1148 @param AndData The value to AND with the PCI configuration register.
1150 @return The value written back to the PCI configuration register.
1164 BitFieldAnd32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
)
1169 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1170 bitwise OR, and writes the result back to the bit field in the
1173 Reads the 32-bit PCI configuration register specified by Address, performs a
1174 bitwise AND followed by a bitwise OR between the read result and
1175 the value specified by AndData, and writes the result to the 32-bit PCI
1176 configuration register specified by Address. The value written to the PCI
1177 configuration register is returned. This function must guarantee that all PCI
1178 read and write operations are serialized. Extra left bits in both AndData and
1179 OrData are stripped.
1181 If Address > 0x0FFFFFFF, then ASSERT().
1182 If Address is not aligned on a 32-bit boundary, then ASSERT().
1183 If StartBit is greater than 31, then ASSERT().
1184 If EndBit is greater than 31, then ASSERT().
1185 If EndBit is less than StartBit, then ASSERT().
1187 @param Address The PCI configuration register to write.
1188 @param StartBit The ordinal of the least significant bit in the bit field.
1190 @param EndBit The ordinal of the most significant bit in the bit field.
1192 @param AndData The value to AND with the PCI configuration register.
1193 @param OrData The value to OR with the result of the AND operation.
1195 @return The value written back to the PCI configuration register.
1200 PciBitFieldAndThenOr32 (
1210 BitFieldAndThenOr32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
, OrData
)
1215 Reads a range of PCI configuration registers into a caller supplied buffer.
1217 Reads the range of PCI configuration registers specified by StartAddress and
1218 Size into the buffer specified by Buffer. This function only allows the PCI
1219 configuration registers from a single PCI function to be read. Size is
1220 returned. When possible 32-bit PCI configuration read cycles are used to read
1221 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1222 and 16-bit PCI configuration read cycles may be used at the beginning and the
1225 If StartAddress > 0x0FFFFFFF, then ASSERT().
1226 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1227 If Size > 0 and Buffer is NULL, then ASSERT().
1229 @param StartAddress The starting address that encodes the PCI Bus, Device,
1230 Function and Register.
1231 @param Size The size in bytes of the transfer.
1232 @param Buffer The pointer to a buffer receiving the data read.
1240 IN UINTN StartAddress
,
1247 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1248 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1254 ASSERT (Buffer
!= NULL
);
1257 // Save Size for return
1261 if ((StartAddress
& BIT0
) != 0) {
1263 // Read a byte if StartAddress is byte aligned
1265 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1266 StartAddress
+= sizeof (UINT8
);
1267 Size
-= sizeof (UINT8
);
1268 Buffer
= (UINT8
*)Buffer
+ 1;
1271 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1273 // Read a word if StartAddress is word aligned
1275 WriteUnaligned16 (Buffer
, PciRead16 (StartAddress
));
1276 StartAddress
+= sizeof (UINT16
);
1277 Size
-= sizeof (UINT16
);
1278 Buffer
= (UINT16
*)Buffer
+ 1;
1281 while (Size
>= sizeof (UINT32
)) {
1283 // Read as many double words as possible
1285 WriteUnaligned32 (Buffer
, PciRead32 (StartAddress
));
1286 StartAddress
+= sizeof (UINT32
);
1287 Size
-= sizeof (UINT32
);
1288 Buffer
= (UINT32
*)Buffer
+ 1;
1291 if (Size
>= sizeof (UINT16
)) {
1293 // Read the last remaining word if exist
1295 WriteUnaligned16 (Buffer
, PciRead16 (StartAddress
));
1296 StartAddress
+= sizeof (UINT16
);
1297 Size
-= sizeof (UINT16
);
1298 Buffer
= (UINT16
*)Buffer
+ 1;
1301 if (Size
>= sizeof (UINT8
)) {
1303 // Read the last remaining byte if exist
1305 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1312 Copies the data in a caller supplied buffer to a specified range of PCI
1313 configuration space.
1315 Writes the range of PCI configuration registers specified by StartAddress and
1316 Size from the buffer specified by Buffer. This function only allows the PCI
1317 configuration registers from a single PCI function to be written. Size is
1318 returned. When possible 32-bit PCI configuration write cycles are used to
1319 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1320 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1321 and the end of the range.
1323 If StartAddress > 0x0FFFFFFF, then ASSERT().
1324 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1325 If Size > 0 and Buffer is NULL, then ASSERT().
1327 @param StartAddress The starting address that encodes the PCI Bus, Device,
1328 Function and Register.
1329 @param Size The size in bytes of the transfer.
1330 @param Buffer The pointer to a buffer containing the data to write.
1332 @return Size written to StartAddress.
1338 IN UINTN StartAddress
,
1345 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1346 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1352 ASSERT (Buffer
!= NULL
);
1355 // Save Size for return
1359 if ((StartAddress
& BIT0
) != 0) {
1361 // Write a byte if StartAddress is byte aligned
1363 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1364 StartAddress
+= sizeof (UINT8
);
1365 Size
-= sizeof (UINT8
);
1366 Buffer
= (UINT8
*)Buffer
+ 1;
1369 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1371 // Write a word if StartAddress is word aligned
1373 PciWrite16 (StartAddress
, ReadUnaligned16 (Buffer
));
1374 StartAddress
+= sizeof (UINT16
);
1375 Size
-= sizeof (UINT16
);
1376 Buffer
= (UINT16
*)Buffer
+ 1;
1379 while (Size
>= sizeof (UINT32
)) {
1381 // Write as many double words as possible
1383 PciWrite32 (StartAddress
, ReadUnaligned32 (Buffer
));
1384 StartAddress
+= sizeof (UINT32
);
1385 Size
-= sizeof (UINT32
);
1386 Buffer
= (UINT32
*)Buffer
+ 1;
1389 if (Size
>= sizeof (UINT16
)) {
1391 // Write the last remaining word if exist
1393 PciWrite16 (StartAddress
, ReadUnaligned16 (Buffer
));
1394 StartAddress
+= sizeof (UINT16
);
1395 Size
-= sizeof (UINT16
);
1396 Buffer
= (UINT16
*)Buffer
+ 1;
1399 if (Size
>= sizeof (UINT8
)) {
1401 // Write the last remaining byte if exist
1403 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);