2 PCI Library using PCI CFG2 PPI.
4 Copyright (c) 2007 - 2008, Intel Corporation All rights
5 reserved. This program and the accompanying materials are
6 licensed and made available under the terms and conditions of
7 the BSD License which accompanies this distribution. The full
8 text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #include <Ppi/PciCfg2.h>
20 #include <Library/PciLib.h>
21 #include <Library/BaseLib.h>
22 #include <Library/PeiServicesTablePointerLib.h>
23 #include <Library/DebugLib.h>
24 #include <Library/PeiServicesLib.h>
27 Assert the validity of a PCI address. A valid PCI address should contain 1's
28 only in the low 28 bits.
30 @param A The address to validate.
31 @param M Additional bits to assert to be zero.
34 #define ASSERT_INVALID_PCI_ADDRESS(A,M) \
35 ASSERT (((A) & (~0xfffffff | (M))) == 0)
38 Translate PCI Lib address into format of PCI CFG2 PPI.
40 @param A Address that encodes the PCI Bus, Device, Function and
44 #define PCI_TO_PCICFG2_ADDRESS(A) \
45 ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))
48 Internal worker function to read a PCI configuration register.
50 This function wraps EFI_PEI_PCI_CFG2_PPI.Read() service.
51 It reads and returns the PCI configuration register specified by Address,
52 the width of data is specified by Width.
54 @param Address Address that encodes the PCI Bus, Device, Function and
56 @param Width Width of data to read
58 @return The value read from the PCI configuration register.
62 PeiPciLibPciCfg2ReadWorker (
64 IN EFI_PEI_PCI_CFG_PPI_WIDTH Width
69 CONST EFI_PEI_PCI_CFG2_PPI
*PciCfg2Ppi
;
70 UINT64 PciCfg2Address
;
72 Status
= PeiServicesLocatePpi (&gEfiPciCfg2PpiGuid
, 0, NULL
, (VOID
**) &PciCfg2Ppi
);
73 ASSERT_EFI_ERROR (Status
);
74 ASSERT (PciCfg2Ppi
!= NULL
);
76 PciCfg2Address
= PCI_TO_PCICFG2_ADDRESS (Address
);
78 GetPeiServicesTablePointer (),
89 Internal worker function to writes a PCI configuration register.
91 This function wraps EFI_PEI_PCI_CFG2_PPI.Write() service.
92 It writes the PCI configuration register specified by Address with the
93 value specified by Data. The width of data is specifed by Width.
96 @param Address Address that encodes the PCI Bus, Device, Function and
98 @param Width Width of data to write
99 @param Data The value to write.
101 @return The value written to the PCI configuration register.
105 PeiPciLibPciCfg2WriteWorker (
107 IN EFI_PEI_PCI_CFG_PPI_WIDTH Width
,
112 CONST EFI_PEI_PCI_CFG2_PPI
*PciCfg2Ppi
;
113 UINT64 PciCfg2Address
;
115 Status
= PeiServicesLocatePpi (&gEfiPciCfg2PpiGuid
, 0, NULL
, (VOID
**) &PciCfg2Ppi
);
116 ASSERT_EFI_ERROR (Status
);
117 ASSERT (PciCfg2Ppi
!= NULL
);
119 PciCfg2Address
= PCI_TO_PCICFG2_ADDRESS (Address
);
121 GetPeiServicesTablePointer (),
132 Registers a PCI device so PCI configuration registers may be accessed after
133 SetVirtualAddressMap().
135 Registers the PCI device specified by Address so all the PCI configuration registers
136 associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
138 If Address > 0x0FFFFFFF, then ASSERT().
140 @param Address Address that encodes the PCI Bus, Device, Function and
143 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
144 @retval RETURN_UNSUPPORTED An attempt was made to call this function
145 after ExitBootServices().
146 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
147 at runtime could not be mapped.
148 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
149 complete the registration.
154 PciRegisterForRuntimeAccess (
158 return RETURN_UNSUPPORTED
;
162 Reads an 8-bit PCI configuration register.
164 Reads and returns the 8-bit PCI configuration register specified by Address.
165 This function must guarantee that all PCI read and write operations are
168 If Address > 0x0FFFFFFF, then ASSERT().
170 @param Address Address that encodes the PCI Bus, Device, Function and
173 @return The read value from the PCI configuration register.
182 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
184 return (UINT8
) PeiPciLibPciCfg2ReadWorker (Address
, EfiPeiPciCfgWidthUint8
);
188 Writes an 8-bit PCI configuration register.
190 Writes the 8-bit PCI configuration register specified by Address with the
191 value specified by Value. Value is returned. This function must guarantee
192 that all PCI read and write operations are serialized.
194 If Address > 0x0FFFFFFF, then ASSERT().
196 @param Address Address that encodes the PCI Bus, Device, Function and
198 @param Value The value to write.
200 @return The value written to the PCI configuration register.
210 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
212 return (UINT8
) PeiPciLibPciCfg2WriteWorker (Address
, EfiPeiPciCfgWidthUint8
, Value
);
216 Performs a bitwise OR of an 8-bit PCI configuration register with
219 Reads the 8-bit PCI configuration register specified by Address, performs a
220 bitwise OR between the read result and the value specified by
221 OrData, and writes the result to the 8-bit PCI configuration register
222 specified by Address. The value written to the PCI configuration register is
223 returned. This function must guarantee that all PCI read and write operations
226 If Address > 0x0FFFFFFF, then ASSERT().
228 @param Address Address that encodes the PCI Bus, Device, Function and
230 @param OrData The value to OR with the PCI configuration register.
232 @return The value written back to the PCI configuration register.
242 return PciWrite8 (Address
, (UINT8
) (PciRead8 (Address
) | OrData
));
246 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
249 Reads the 8-bit PCI configuration register specified by Address, performs a
250 bitwise AND between the read result and the value specified by AndData, and
251 writes the result to the 8-bit PCI configuration register specified by
252 Address. The value written to the PCI configuration register is returned.
253 This function must guarantee that all PCI read and write operations are
256 If Address > 0x0FFFFFFF, then ASSERT().
258 @param Address Address that encodes the PCI Bus, Device, Function and
260 @param AndData The value to AND with the PCI configuration register.
262 @return The value written back to the PCI configuration register.
272 return PciWrite8 (Address
, (UINT8
) (PciRead8 (Address
) & AndData
));
276 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
277 value, followed a bitwise OR with another 8-bit value.
279 Reads the 8-bit PCI configuration register specified by Address, performs a
280 bitwise AND between the read result and the value specified by AndData,
281 performs a bitwise OR between the result of the AND operation and
282 the value specified by OrData, and writes the result to the 8-bit PCI
283 configuration register specified by Address. The value written to the PCI
284 configuration register is returned. This function must guarantee that all PCI
285 read and write operations are serialized.
287 If Address > 0x0FFFFFFF, then ASSERT().
289 @param Address Address that encodes the PCI Bus, Device, Function and
291 @param AndData The value to AND with the PCI configuration register.
292 @param OrData The value to OR with the result of the AND operation.
294 @return The value written back to the PCI configuration register.
305 return PciWrite8 (Address
, (UINT8
) ((PciRead8 (Address
) & AndData
) | OrData
));
309 Reads a bit field of a PCI configuration register.
311 Reads the bit field in an 8-bit PCI configuration register. The bit field is
312 specified by the StartBit and the EndBit. The value of the bit field is
315 If Address > 0x0FFFFFFF, then ASSERT().
316 If StartBit is greater than 7, then ASSERT().
317 If EndBit is greater than 7, then ASSERT().
318 If EndBit is less than StartBit, then ASSERT().
320 @param Address PCI configuration register to read.
321 @param StartBit The ordinal of the least significant bit in the bit field.
323 @param EndBit The ordinal of the most significant bit in the bit field.
326 @return The value of the bit field read from the PCI configuration register.
337 return BitFieldRead8 (PciRead8 (Address
), StartBit
, EndBit
);
341 Writes a bit field to a PCI configuration register.
343 Writes Value to the bit field of the PCI configuration register. The bit
344 field is specified by the StartBit and the EndBit. All other bits in the
345 destination PCI configuration register are preserved. The new value of the
346 8-bit register is returned.
348 If Address > 0x0FFFFFFF, then ASSERT().
349 If StartBit is greater than 7, then ASSERT().
350 If EndBit is greater than 7, then ASSERT().
351 If EndBit is less than StartBit, then ASSERT().
353 @param Address PCI configuration register to write.
354 @param StartBit The ordinal of the least significant bit in the bit field.
356 @param EndBit The ordinal of the most significant bit in the bit field.
358 @param Value New value of the bit field.
360 @return The value written back to the PCI configuration register.
374 BitFieldWrite8 (PciRead8 (Address
), StartBit
, EndBit
, Value
)
379 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
380 writes the result back to the bit field in the 8-bit port.
382 Reads the 8-bit PCI configuration register specified by Address, performs a
383 bitwise OR between the read result and the value specified by
384 OrData, and writes the result to the 8-bit PCI configuration register
385 specified by Address. The value written to the PCI configuration register is
386 returned. This function must guarantee that all PCI read and write operations
387 are serialized. Extra left bits in OrData are stripped.
389 If Address > 0x0FFFFFFF, then ASSERT().
390 If StartBit is greater than 7, then ASSERT().
391 If EndBit is greater than 7, then ASSERT().
392 If EndBit is less than StartBit, then ASSERT().
394 @param Address PCI configuration register to write.
395 @param StartBit The ordinal of the least significant bit in the bit field.
397 @param EndBit The ordinal of the most significant bit in the bit field.
399 @param OrData The value to OR with the PCI configuration register.
401 @return The value written back to the PCI configuration register.
415 BitFieldOr8 (PciRead8 (Address
), StartBit
, EndBit
, OrData
)
420 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
421 AND, and writes the result back to the bit field in the 8-bit register.
423 Reads the 8-bit PCI configuration register specified by Address, performs a
424 bitwise AND between the read result and the value specified by AndData, and
425 writes the result to the 8-bit PCI configuration register specified by
426 Address. The value written to the PCI configuration register is returned.
427 This function must guarantee that all PCI read and write operations are
428 serialized. Extra left bits in AndData are stripped.
430 If Address > 0x0FFFFFFF, then ASSERT().
431 If StartBit is greater than 7, then ASSERT().
432 If EndBit is greater than 7, then ASSERT().
433 If EndBit is less than StartBit, then ASSERT().
435 @param Address PCI configuration register to write.
436 @param StartBit The ordinal of the least significant bit in the bit field.
438 @param EndBit The ordinal of the most significant bit in the bit field.
440 @param AndData The value to AND with the PCI configuration register.
442 @return The value written back to the PCI configuration register.
456 BitFieldAnd8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
)
461 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
462 bitwise OR, and writes the result back to the bit field in the
465 Reads the 8-bit PCI configuration register specified by Address, performs a
466 bitwise AND followed by a bitwise OR between the read result and
467 the value specified by AndData, and writes the result to the 8-bit PCI
468 configuration register specified by Address. The value written to the PCI
469 configuration register is returned. This function must guarantee that all PCI
470 read and write operations are serialized. Extra left bits in both AndData and
473 If Address > 0x0FFFFFFF, then ASSERT().
474 If StartBit is greater than 7, then ASSERT().
475 If EndBit is greater than 7, then ASSERT().
476 If EndBit is less than StartBit, then ASSERT().
478 @param Address PCI configuration register to write.
479 @param StartBit The ordinal of the least significant bit in the bit field.
481 @param EndBit The ordinal of the most significant bit in the bit field.
483 @param AndData The value to AND with the PCI configuration register.
484 @param OrData The value to OR with the result of the AND operation.
486 @return The value written back to the PCI configuration register.
491 PciBitFieldAndThenOr8 (
501 BitFieldAndThenOr8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
, OrData
)
506 Reads a 16-bit PCI configuration register.
508 Reads and returns the 16-bit PCI configuration register specified by Address.
509 This function must guarantee that all PCI read and write operations are
512 If Address > 0x0FFFFFFF, then ASSERT().
513 If Address is not aligned on a 16-bit boundary, then ASSERT().
515 @param Address Address that encodes the PCI Bus, Device, Function and
518 @return The read value from the PCI configuration register.
527 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
529 return (UINT16
) PeiPciLibPciCfg2ReadWorker (Address
, EfiPeiPciCfgWidthUint16
);
533 Writes a 16-bit PCI configuration register.
535 Writes the 16-bit PCI configuration register specified by Address with the
536 value specified by Value. Value is returned. This function must guarantee
537 that all PCI read and write operations are serialized.
539 If Address > 0x0FFFFFFF, then ASSERT().
540 If Address is not aligned on a 16-bit boundary, then ASSERT().
542 @param Address Address that encodes the PCI Bus, Device, Function and
544 @param Value The value to write.
546 @return The value written to the PCI configuration register.
556 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
558 return (UINT16
) PeiPciLibPciCfg2WriteWorker (Address
, EfiPeiPciCfgWidthUint16
, Value
);
562 Performs a bitwise OR of a 16-bit PCI configuration register with
565 Reads the 16-bit PCI configuration register specified by Address, performs a
566 bitwise OR between the read result and the value specified by
567 OrData, and writes the result to the 16-bit PCI configuration register
568 specified by Address. The value written to the PCI configuration register is
569 returned. This function must guarantee that all PCI read and write operations
572 If Address > 0x0FFFFFFF, then ASSERT().
573 If Address is not aligned on a 16-bit boundary, then ASSERT().
575 @param Address Address that encodes the PCI Bus, Device, Function and
577 @param OrData The value to OR with the PCI configuration register.
579 @return The value written back to the PCI configuration register.
589 return PciWrite16 (Address
, (UINT16
) (PciRead16 (Address
) | OrData
));
593 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
596 Reads the 16-bit PCI configuration register specified by Address, performs a
597 bitwise AND between the read result and the value specified by AndData, and
598 writes the result to the 16-bit PCI configuration register specified by
599 Address. The value written to the PCI configuration register is returned.
600 This function must guarantee that all PCI read and write operations are
603 If Address > 0x0FFFFFFF, then ASSERT().
604 If Address is not aligned on a 16-bit boundary, then ASSERT().
606 @param Address Address that encodes the PCI Bus, Device, Function and
608 @param AndData The value to AND with the PCI configuration register.
610 @return The value written back to the PCI configuration register.
620 return PciWrite16 (Address
, (UINT16
) (PciRead16 (Address
) & AndData
));
624 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
625 value, followed a bitwise OR with another 16-bit value.
627 Reads the 16-bit PCI configuration register specified by Address, performs a
628 bitwise AND between the read result and the value specified by AndData,
629 performs a bitwise OR between the result of the AND operation and
630 the value specified by OrData, and writes the result to the 16-bit PCI
631 configuration register specified by Address. The value written to the PCI
632 configuration register is returned. This function must guarantee that all PCI
633 read and write operations are serialized.
635 If Address > 0x0FFFFFFF, then ASSERT().
636 If Address is not aligned on a 16-bit boundary, then ASSERT().
638 @param Address Address that encodes the PCI Bus, Device, Function and
640 @param AndData The value to AND with the PCI configuration register.
641 @param OrData The value to OR with the result of the AND operation.
643 @return The value written back to the PCI configuration register.
654 return PciWrite16 (Address
, (UINT16
) ((PciRead16 (Address
) & AndData
) | OrData
));
658 Reads a bit field of a PCI configuration register.
660 Reads the bit field in a 16-bit PCI configuration register. The bit field is
661 specified by the StartBit and the EndBit. The value of the bit field is
664 If Address > 0x0FFFFFFF, then ASSERT().
665 If Address is not aligned on a 16-bit boundary, then ASSERT().
666 If StartBit is greater than 15, then ASSERT().
667 If EndBit is greater than 15, then ASSERT().
668 If EndBit is less than StartBit, then ASSERT().
670 @param Address PCI configuration register to read.
671 @param StartBit The ordinal of the least significant bit in the bit field.
673 @param EndBit The ordinal of the most significant bit in the bit field.
676 @return The value of the bit field read from the PCI configuration register.
687 return BitFieldRead16 (PciRead16 (Address
), StartBit
, EndBit
);
691 Writes a bit field to a PCI configuration register.
693 Writes Value to the bit field of the PCI configuration register. The bit
694 field is specified by the StartBit and the EndBit. All other bits in the
695 destination PCI configuration register are preserved. The new value of the
696 16-bit register is returned.
698 If Address > 0x0FFFFFFF, then ASSERT().
699 If Address is not aligned on a 16-bit boundary, then ASSERT().
700 If StartBit is greater than 15, then ASSERT().
701 If EndBit is greater than 15, then ASSERT().
702 If EndBit is less than StartBit, then ASSERT().
704 @param Address PCI configuration register to write.
705 @param StartBit The ordinal of the least significant bit in the bit field.
707 @param EndBit The ordinal of the most significant bit in the bit field.
709 @param Value New value of the bit field.
711 @return The value written back to the PCI configuration register.
725 BitFieldWrite16 (PciRead16 (Address
), StartBit
, EndBit
, Value
)
730 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
731 writes the result back to the bit field in the 16-bit port.
733 Reads the 16-bit PCI configuration register specified by Address, performs a
734 bitwise OR between the read result and the value specified by
735 OrData, and writes the result to the 16-bit PCI configuration register
736 specified by Address. The value written to the PCI configuration register is
737 returned. This function must guarantee that all PCI read and write operations
738 are serialized. Extra left bits in OrData are stripped.
740 If Address > 0x0FFFFFFF, then ASSERT().
741 If Address is not aligned on a 16-bit boundary, then ASSERT().
742 If StartBit is greater than 15, then ASSERT().
743 If EndBit is greater than 15, then ASSERT().
744 If EndBit is less than StartBit, then ASSERT().
746 @param Address PCI configuration register to write.
747 @param StartBit The ordinal of the least significant bit in the bit field.
749 @param EndBit The ordinal of the most significant bit in the bit field.
751 @param OrData The value to OR with the PCI configuration register.
753 @return The value written back to the PCI configuration register.
767 BitFieldOr16 (PciRead16 (Address
), StartBit
, EndBit
, OrData
)
772 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
773 AND, and writes the result back to the bit field in the 16-bit register.
775 Reads the 16-bit PCI configuration register specified by Address, performs a
776 bitwise AND between the read result and the value specified by AndData, and
777 writes the result to the 16-bit PCI configuration register specified by
778 Address. The value written to the PCI configuration register is returned.
779 This function must guarantee that all PCI read and write operations are
780 serialized. Extra left bits in AndData are stripped.
782 If Address > 0x0FFFFFFF, then ASSERT().
783 If Address is not aligned on a 16-bit boundary, then ASSERT().
784 If StartBit is greater than 15, then ASSERT().
785 If EndBit is greater than 15, then ASSERT().
786 If EndBit is less than StartBit, then ASSERT().
788 @param Address PCI configuration register to write.
789 @param StartBit The ordinal of the least significant bit in the bit field.
791 @param EndBit The ordinal of the most significant bit in the bit field.
793 @param AndData The value to AND with the PCI configuration register.
795 @return The value written back to the PCI configuration register.
809 BitFieldAnd16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
)
814 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
815 bitwise OR, and writes the result back to the bit field in the
818 Reads the 16-bit PCI configuration register specified by Address, performs a
819 bitwise AND followed by a bitwise OR between the read result and
820 the value specified by AndData, and writes the result to the 16-bit PCI
821 configuration register specified by Address. The value written to the PCI
822 configuration register is returned. This function must guarantee that all PCI
823 read and write operations are serialized. Extra left bits in both AndData and
826 If Address > 0x0FFFFFFF, then ASSERT().
827 If Address is not aligned on a 16-bit boundary, then ASSERT().
828 If StartBit is greater than 15, then ASSERT().
829 If EndBit is greater than 15, then ASSERT().
830 If EndBit is less than StartBit, then ASSERT().
832 @param Address PCI configuration register to write.
833 @param StartBit The ordinal of the least significant bit in the bit field.
835 @param EndBit The ordinal of the most significant bit in the bit field.
837 @param AndData The value to AND with the PCI configuration register.
838 @param OrData The value to OR with the result of the AND operation.
840 @return The value written back to the PCI configuration register.
845 PciBitFieldAndThenOr16 (
855 BitFieldAndThenOr16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
, OrData
)
860 Reads a 32-bit PCI configuration register.
862 Reads and returns the 32-bit PCI configuration register specified by Address.
863 This function must guarantee that all PCI read and write operations are
866 If Address > 0x0FFFFFFF, then ASSERT().
867 If Address is not aligned on a 32-bit boundary, then ASSERT().
869 @param Address Address that encodes the PCI Bus, Device, Function and
872 @return The read value from the PCI configuration register.
881 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
883 return PeiPciLibPciCfg2ReadWorker (Address
, EfiPeiPciCfgWidthUint32
);
887 Writes a 32-bit PCI configuration register.
889 Writes the 32-bit PCI configuration register specified by Address with the
890 value specified by Value. Value is returned. This function must guarantee
891 that all PCI read and write operations are serialized.
893 If Address > 0x0FFFFFFF, then ASSERT().
894 If Address is not aligned on a 32-bit boundary, then ASSERT().
896 @param Address Address that encodes the PCI Bus, Device, Function and
898 @param Value The value to write.
900 @return The value written to the PCI configuration register.
910 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
912 return PeiPciLibPciCfg2WriteWorker (Address
, EfiPeiPciCfgWidthUint32
, Value
);
916 Performs a bitwise OR of a 32-bit PCI configuration register with
919 Reads the 32-bit PCI configuration register specified by Address, performs a
920 bitwise OR between the read result and the value specified by
921 OrData, and writes the result to the 32-bit PCI configuration register
922 specified by Address. The value written to the PCI configuration register is
923 returned. This function must guarantee that all PCI read and write operations
926 If Address > 0x0FFFFFFF, then ASSERT().
927 If Address is not aligned on a 32-bit boundary, then ASSERT().
929 @param Address Address that encodes the PCI Bus, Device, Function and
931 @param OrData The value to OR with the PCI configuration register.
933 @return The value written back to the PCI configuration register.
943 return PciWrite32 (Address
, PciRead32 (Address
) | OrData
);
947 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
950 Reads the 32-bit PCI configuration register specified by Address, performs a
951 bitwise AND between the read result and the value specified by AndData, and
952 writes the result to the 32-bit PCI configuration register specified by
953 Address. The value written to the PCI configuration register is returned.
954 This function must guarantee that all PCI read and write operations are
957 If Address > 0x0FFFFFFF, then ASSERT().
958 If Address is not aligned on a 32-bit boundary, then ASSERT().
960 @param Address Address that encodes the PCI Bus, Device, Function and
962 @param AndData The value to AND with the PCI configuration register.
964 @return The value written back to the PCI configuration register.
974 return PciWrite32 (Address
, PciRead32 (Address
) & AndData
);
978 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
979 value, followed a bitwise OR with another 32-bit value.
981 Reads the 32-bit PCI configuration register specified by Address, performs a
982 bitwise AND between the read result and the value specified by AndData,
983 performs a bitwise OR between the result of the AND operation and
984 the value specified by OrData, and writes the result to the 32-bit PCI
985 configuration register specified by Address. The value written to the PCI
986 configuration register is returned. This function must guarantee that all PCI
987 read and write operations are serialized.
989 If Address > 0x0FFFFFFF, then ASSERT().
990 If Address is not aligned on a 32-bit boundary, then ASSERT().
992 @param Address Address that encodes the PCI Bus, Device, Function and
994 @param AndData The value to AND with the PCI configuration register.
995 @param OrData The value to OR with the result of the AND operation.
997 @return The value written back to the PCI configuration register.
1008 return PciWrite32 (Address
, (PciRead32 (Address
) & AndData
) | OrData
);
1012 Reads a bit field of a PCI configuration register.
1014 Reads the bit field in a 32-bit PCI configuration register. The bit field is
1015 specified by the StartBit and the EndBit. The value of the bit field is
1018 If Address > 0x0FFFFFFF, then ASSERT().
1019 If Address is not aligned on a 32-bit boundary, then ASSERT().
1020 If StartBit is greater than 31, then ASSERT().
1021 If EndBit is greater than 31, then ASSERT().
1022 If EndBit is less than StartBit, then ASSERT().
1024 @param Address PCI configuration register to read.
1025 @param StartBit The ordinal of the least significant bit in the bit field.
1027 @param EndBit The ordinal of the most significant bit in the bit field.
1030 @return The value of the bit field read from the PCI configuration register.
1041 return BitFieldRead32 (PciRead32 (Address
), StartBit
, EndBit
);
1045 Writes a bit field to a PCI configuration register.
1047 Writes Value to the bit field of the PCI configuration register. The bit
1048 field is specified by the StartBit and the EndBit. All other bits in the
1049 destination PCI configuration register are preserved. The new value of the
1050 32-bit register is returned.
1052 If Address > 0x0FFFFFFF, then ASSERT().
1053 If Address is not aligned on a 32-bit boundary, then ASSERT().
1054 If StartBit is greater than 31, then ASSERT().
1055 If EndBit is greater than 31, then ASSERT().
1056 If EndBit is less than StartBit, then ASSERT().
1058 @param Address PCI configuration register to write.
1059 @param StartBit The ordinal of the least significant bit in the bit field.
1061 @param EndBit The ordinal of the most significant bit in the bit field.
1063 @param Value New value of the bit field.
1065 @return The value written back to the PCI configuration register.
1070 PciBitFieldWrite32 (
1079 BitFieldWrite32 (PciRead32 (Address
), StartBit
, EndBit
, Value
)
1084 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1085 writes the result back to the bit field in the 32-bit port.
1087 Reads the 32-bit PCI configuration register specified by Address, performs a
1088 bitwise OR between the read result and the value specified by
1089 OrData, and writes the result to the 32-bit PCI configuration register
1090 specified by Address. The value written to the PCI configuration register is
1091 returned. This function must guarantee that all PCI read and write operations
1092 are serialized. Extra left bits in OrData are stripped.
1094 If Address > 0x0FFFFFFF, then ASSERT().
1095 If Address is not aligned on a 32-bit boundary, then ASSERT().
1096 If StartBit is greater than 31, then ASSERT().
1097 If EndBit is greater than 31, then ASSERT().
1098 If EndBit is less than StartBit, then ASSERT().
1100 @param Address PCI configuration register to write.
1101 @param StartBit The ordinal of the least significant bit in the bit field.
1103 @param EndBit The ordinal of the most significant bit in the bit field.
1105 @param OrData The value to OR with the PCI configuration register.
1107 @return The value written back to the PCI configuration register.
1121 BitFieldOr32 (PciRead32 (Address
), StartBit
, EndBit
, OrData
)
1126 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1127 AND, and writes the result back to the bit field in the 32-bit register.
1129 Reads the 32-bit PCI configuration register specified by Address, performs a
1130 bitwise AND between the read result and the value specified by AndData, and
1131 writes the result to the 32-bit PCI configuration register specified by
1132 Address. The value written to the PCI configuration register is returned.
1133 This function must guarantee that all PCI read and write operations are
1134 serialized. Extra left bits in AndData are stripped.
1136 If Address > 0x0FFFFFFF, then ASSERT().
1137 If Address is not aligned on a 32-bit boundary, then ASSERT().
1138 If StartBit is greater than 31, then ASSERT().
1139 If EndBit is greater than 31, then ASSERT().
1140 If EndBit is less than StartBit, then ASSERT().
1142 @param Address PCI configuration register to write.
1143 @param StartBit The ordinal of the least significant bit in the bit field.
1145 @param EndBit The ordinal of the most significant bit in the bit field.
1147 @param AndData The value to AND with the PCI configuration register.
1149 @return The value written back to the PCI configuration register.
1163 BitFieldAnd32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
)
1168 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1169 bitwise OR, and writes the result back to the bit field in the
1172 Reads the 32-bit PCI configuration register specified by Address, performs a
1173 bitwise AND followed by a bitwise OR between the read result and
1174 the value specified by AndData, and writes the result to the 32-bit PCI
1175 configuration register specified by Address. The value written to the PCI
1176 configuration register is returned. This function must guarantee that all PCI
1177 read and write operations are serialized. Extra left bits in both AndData and
1178 OrData are stripped.
1180 If Address > 0x0FFFFFFF, then ASSERT().
1181 If Address is not aligned on a 32-bit boundary, then ASSERT().
1182 If StartBit is greater than 31, then ASSERT().
1183 If EndBit is greater than 31, then ASSERT().
1184 If EndBit is less than StartBit, then ASSERT().
1186 @param Address PCI configuration register to write.
1187 @param StartBit The ordinal of the least significant bit in the bit field.
1189 @param EndBit The ordinal of the most significant bit in the bit field.
1191 @param AndData The value to AND with the PCI configuration register.
1192 @param OrData The value to OR with the result of the AND operation.
1194 @return The value written back to the PCI configuration register.
1199 PciBitFieldAndThenOr32 (
1209 BitFieldAndThenOr32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
, OrData
)
1214 Reads a range of PCI configuration registers into a caller supplied buffer.
1216 Reads the range of PCI configuration registers specified by StartAddress and
1217 Size into the buffer specified by Buffer. This function only allows the PCI
1218 configuration registers from a single PCI function to be read. Size is
1219 returned. When possible 32-bit PCI configuration read cycles are used to read
1220 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1221 and 16-bit PCI configuration read cycles may be used at the beginning and the
1224 If StartAddress > 0x0FFFFFFF, then ASSERT().
1225 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1226 If Size > 0 and Buffer is NULL, then ASSERT().
1228 @param StartAddress Starting address that encodes the PCI Bus, Device,
1229 Function and Register.
1230 @param Size Size in bytes of the transfer.
1231 @param Buffer Pointer to a buffer receiving the data read.
1239 IN UINTN StartAddress
,
1246 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1247 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1253 ASSERT (Buffer
!= NULL
);
1256 // Save Size for return
1260 if ((StartAddress
& BIT0
) != 0) {
1262 // Read a byte if StartAddress is byte aligned
1264 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1265 StartAddress
+= sizeof (UINT8
);
1266 Size
-= sizeof (UINT8
);
1267 Buffer
= (UINT8
*)Buffer
+ 1;
1270 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1272 // Read a word if StartAddress is word aligned
1274 *(volatile UINT16
*)Buffer
= PciRead16 (StartAddress
);
1275 StartAddress
+= sizeof (UINT16
);
1276 Size
-= sizeof (UINT16
);
1277 Buffer
= (UINT16
*)Buffer
+ 1;
1280 while (Size
>= sizeof (UINT32
)) {
1282 // Read as many double words as possible
1284 *(volatile UINT32
*)Buffer
= PciRead32 (StartAddress
);
1285 StartAddress
+= sizeof (UINT32
);
1286 Size
-= sizeof (UINT32
);
1287 Buffer
= (UINT32
*)Buffer
+ 1;
1290 if (Size
>= sizeof (UINT16
)) {
1292 // Read the last remaining word if exist
1294 *(volatile UINT16
*)Buffer
= PciRead16 (StartAddress
);
1295 StartAddress
+= sizeof (UINT16
);
1296 Size
-= sizeof (UINT16
);
1297 Buffer
= (UINT16
*)Buffer
+ 1;
1300 if (Size
>= sizeof (UINT8
)) {
1302 // Read the last remaining byte if exist
1304 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1311 Copies the data in a caller supplied buffer to a specified range of PCI
1312 configuration space.
1314 Writes the range of PCI configuration registers specified by StartAddress and
1315 Size from the buffer specified by Buffer. This function only allows the PCI
1316 configuration registers from a single PCI function to be written. Size is
1317 returned. When possible 32-bit PCI configuration write cycles are used to
1318 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1319 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1320 and the end of the range.
1322 If StartAddress > 0x0FFFFFFF, then ASSERT().
1323 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1324 If Size > 0 and Buffer is NULL, then ASSERT().
1326 @param StartAddress Starting address that encodes the PCI Bus, Device,
1327 Function and Register.
1328 @param Size Size in bytes of the transfer.
1329 @param Buffer Pointer to a buffer containing the data to write.
1331 @return Size written to StartAddress.
1337 IN UINTN StartAddress
,
1344 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1345 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1351 ASSERT (Buffer
!= NULL
);
1354 // Save Size for return
1358 if ((StartAddress
& BIT0
) != 0) {
1360 // Write a byte if StartAddress is byte aligned
1362 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1363 StartAddress
+= sizeof (UINT8
);
1364 Size
-= sizeof (UINT8
);
1365 Buffer
= (UINT8
*)Buffer
+ 1;
1368 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1370 // Write a word if StartAddress is word aligned
1372 PciWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1373 StartAddress
+= sizeof (UINT16
);
1374 Size
-= sizeof (UINT16
);
1375 Buffer
= (UINT16
*)Buffer
+ 1;
1378 while (Size
>= sizeof (UINT32
)) {
1380 // Write as many double words as possible
1382 PciWrite32 (StartAddress
, *(UINT32
*)Buffer
);
1383 StartAddress
+= sizeof (UINT32
);
1384 Size
-= sizeof (UINT32
);
1385 Buffer
= (UINT32
*)Buffer
+ 1;
1388 if (Size
>= sizeof (UINT16
)) {
1390 // Write the last remaining word if exist
1392 PciWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1393 StartAddress
+= sizeof (UINT16
);
1394 Size
-= sizeof (UINT16
);
1395 Buffer
= (UINT16
*)Buffer
+ 1;
1398 if (Size
>= sizeof (UINT8
)) {
1400 // Write the last remaining byte if exist
1402 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);