2 PCI Library using PCI CFG2 PPI.
4 Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials are
6 licensed and made available under the terms and conditions of
7 the BSD License which accompanies this distribution. The full
8 text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php.
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #include <Ppi/PciCfg2.h>
20 #include <Library/PciLib.h>
21 #include <Library/BaseLib.h>
22 #include <Library/PeiServicesTablePointerLib.h>
23 #include <Library/DebugLib.h>
24 #include <Library/PeiServicesLib.h>
27 Assert the validity of a PCI address. A valid PCI address should contain 1's
28 only in the low 28 bits.
30 @param A The address to validate.
31 @param M Additional bits to assert to be zero.
34 #define ASSERT_INVALID_PCI_ADDRESS(A,M) \
35 ASSERT (((A) & (~0xfffffff | (M))) == 0)
38 Translate PCI Lib address into format of PCI CFG2 PPI.
40 @param A The address that encodes the PCI Bus, Device, Function and
44 #define PCI_TO_PCICFG2_ADDRESS(A) \
45 ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))
48 Internal worker function to read a PCI configuration register.
50 This function wraps EFI_PEI_PCI_CFG2_PPI.Read() service.
51 It reads and returns the PCI configuration register specified by Address,
52 the width of data is specified by Width.
54 @param Address The address that encodes the PCI Bus, Device, Function and
56 @param Width The width of data to read
58 @return The value read from the PCI configuration register.
62 PeiPciLibPciCfg2ReadWorker (
64 IN EFI_PEI_PCI_CFG_PPI_WIDTH Width
69 CONST EFI_PEI_PCI_CFG2_PPI
*PciCfg2Ppi
;
70 UINT64 PciCfg2Address
;
72 Status
= PeiServicesLocatePpi (&gEfiPciCfg2PpiGuid
, 0, NULL
, (VOID
**) &PciCfg2Ppi
);
73 ASSERT_EFI_ERROR (Status
);
74 ASSERT (PciCfg2Ppi
!= NULL
);
76 PciCfg2Address
= PCI_TO_PCICFG2_ADDRESS (Address
);
78 GetPeiServicesTablePointer (),
89 Internal worker function to writes a PCI configuration register.
91 This function wraps EFI_PEI_PCI_CFG2_PPI.Write() service.
92 It writes the PCI configuration register specified by Address with the
93 value specified by Data. The width of data is specifed by Width.
96 @param Address The address that encodes the PCI Bus, Device, Function and
98 @param Width The width of data to write
99 @param Data The value to write.
101 @return The value written to the PCI configuration register.
105 PeiPciLibPciCfg2WriteWorker (
107 IN EFI_PEI_PCI_CFG_PPI_WIDTH Width
,
112 CONST EFI_PEI_PCI_CFG2_PPI
*PciCfg2Ppi
;
113 UINT64 PciCfg2Address
;
115 Status
= PeiServicesLocatePpi (&gEfiPciCfg2PpiGuid
, 0, NULL
, (VOID
**) &PciCfg2Ppi
);
116 ASSERT_EFI_ERROR (Status
);
117 ASSERT (PciCfg2Ppi
!= NULL
);
119 PciCfg2Address
= PCI_TO_PCICFG2_ADDRESS (Address
);
121 GetPeiServicesTablePointer (),
132 Registers a PCI device so PCI configuration registers may be accessed after
133 SetVirtualAddressMap().
135 Registers the PCI device specified by Address so all the PCI configuration registers
136 associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
138 If Address > 0x0FFFFFFF, then ASSERT().
140 @param Address The address that encodes the PCI Bus, Device, Function and
143 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
144 @retval RETURN_UNSUPPORTED An attempt was made to call this function
145 after ExitBootServices().
146 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
147 at runtime could not be mapped.
148 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
149 complete the registration.
154 PciRegisterForRuntimeAccess (
158 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
159 return RETURN_UNSUPPORTED
;
163 Reads an 8-bit PCI configuration register.
165 Reads and returns the 8-bit PCI configuration register specified by Address.
166 This function must guarantee that all PCI read and write operations are
169 If Address > 0x0FFFFFFF, then ASSERT().
171 @param Address The address that encodes the PCI Bus, Device, Function and
174 @return The read value from the PCI configuration register.
183 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
185 return (UINT8
) PeiPciLibPciCfg2ReadWorker (Address
, EfiPeiPciCfgWidthUint8
);
189 Writes an 8-bit PCI configuration register.
191 Writes the 8-bit PCI configuration register specified by Address with the
192 value specified by Value. Value is returned. This function must guarantee
193 that all PCI read and write operations are serialized.
195 If Address > 0x0FFFFFFF, then ASSERT().
197 @param Address The address that encodes the PCI Bus, Device, Function and
199 @param Value The value to write.
201 @return The value written to the PCI configuration register.
211 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
213 return (UINT8
) PeiPciLibPciCfg2WriteWorker (Address
, EfiPeiPciCfgWidthUint8
, Value
);
217 Performs a bitwise OR of an 8-bit PCI configuration register with
220 Reads the 8-bit PCI configuration register specified by Address, performs a
221 bitwise OR between the read result and the value specified by
222 OrData, and writes the result to the 8-bit PCI configuration register
223 specified by Address. The value written to the PCI configuration register is
224 returned. This function must guarantee that all PCI read and write operations
227 If Address > 0x0FFFFFFF, then ASSERT().
229 @param Address The address that encodes the PCI Bus, Device, Function and
231 @param OrData The value to OR with the PCI configuration register.
233 @return The value written back to the PCI configuration register.
243 return PciWrite8 (Address
, (UINT8
) (PciRead8 (Address
) | OrData
));
247 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
250 Reads the 8-bit PCI configuration register specified by Address, performs a
251 bitwise AND between the read result and the value specified by AndData, and
252 writes the result to the 8-bit PCI configuration register specified by
253 Address. The value written to the PCI configuration register is returned.
254 This function must guarantee that all PCI read and write operations are
257 If Address > 0x0FFFFFFF, then ASSERT().
259 @param Address The address that encodes the PCI Bus, Device, Function and
261 @param AndData The value to AND with the PCI configuration register.
263 @return The value written back to the PCI configuration register.
273 return PciWrite8 (Address
, (UINT8
) (PciRead8 (Address
) & AndData
));
277 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
278 value, followed a bitwise OR with another 8-bit value.
280 Reads the 8-bit PCI configuration register specified by Address, performs a
281 bitwise AND between the read result and the value specified by AndData,
282 performs a bitwise OR between the result of the AND operation and
283 the value specified by OrData, and writes the result to the 8-bit PCI
284 configuration register specified by Address. The value written to the PCI
285 configuration register is returned. This function must guarantee that all PCI
286 read and write operations are serialized.
288 If Address > 0x0FFFFFFF, then ASSERT().
290 @param Address The address that encodes the PCI Bus, Device, Function and
292 @param AndData The value to AND with the PCI configuration register.
293 @param OrData The value to OR with the result of the AND operation.
295 @return The value written back to the PCI configuration register.
306 return PciWrite8 (Address
, (UINT8
) ((PciRead8 (Address
) & AndData
) | OrData
));
310 Reads a bit field of a PCI configuration register.
312 Reads the bit field in an 8-bit PCI configuration register. The bit field is
313 specified by the StartBit and the EndBit. The value of the bit field is
316 If Address > 0x0FFFFFFF, then ASSERT().
317 If StartBit is greater than 7, then ASSERT().
318 If EndBit is greater than 7, then ASSERT().
319 If EndBit is less than StartBit, then ASSERT().
321 @param Address The PCI configuration register to read.
322 @param StartBit The ordinal of the least significant bit in the bit field.
324 @param EndBit The ordinal of the most significant bit in the bit field.
327 @return The value of the bit field read from the PCI configuration register.
338 return BitFieldRead8 (PciRead8 (Address
), StartBit
, EndBit
);
342 Writes a bit field to a PCI configuration register.
344 Writes Value to the bit field of the PCI configuration register. The bit
345 field is specified by the StartBit and the EndBit. All other bits in the
346 destination PCI configuration register are preserved. The new value of the
347 8-bit register is returned.
349 If Address > 0x0FFFFFFF, then ASSERT().
350 If StartBit is greater than 7, then ASSERT().
351 If EndBit is greater than 7, then ASSERT().
352 If EndBit is less than StartBit, then ASSERT().
353 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
355 @param Address The PCI configuration register to write.
356 @param StartBit The ordinal of the least significant bit in the bit field.
358 @param EndBit The ordinal of the most significant bit in the bit field.
360 @param Value The new value of the bit field.
362 @return The value written back to the PCI configuration register.
376 BitFieldWrite8 (PciRead8 (Address
), StartBit
, EndBit
, Value
)
381 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
382 writes the result back to the bit field in the 8-bit port.
384 Reads the 8-bit PCI configuration register specified by Address, performs a
385 bitwise OR between the read result and the value specified by
386 OrData, and writes the result to the 8-bit PCI configuration register
387 specified by Address. The value written to the PCI configuration register is
388 returned. This function must guarantee that all PCI read and write operations
389 are serialized. Extra left bits in OrData are stripped.
391 If Address > 0x0FFFFFFF, then ASSERT().
392 If StartBit is greater than 7, then ASSERT().
393 If EndBit is greater than 7, then ASSERT().
394 If EndBit is less than StartBit, then ASSERT().
395 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
397 @param Address The PCI configuration register to write.
398 @param StartBit The ordinal of the least significant bit in the bit field.
400 @param EndBit The ordinal of the most significant bit in the bit field.
402 @param OrData The value to OR with the PCI configuration register.
404 @return The value written back to the PCI configuration register.
418 BitFieldOr8 (PciRead8 (Address
), StartBit
, EndBit
, OrData
)
423 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
424 AND, and writes the result back to the bit field in the 8-bit register.
426 Reads the 8-bit PCI configuration register specified by Address, performs a
427 bitwise AND between the read result and the value specified by AndData, and
428 writes the result to the 8-bit PCI configuration register specified by
429 Address. The value written to the PCI configuration register is returned.
430 This function must guarantee that all PCI read and write operations are
431 serialized. Extra left bits in AndData are stripped.
433 If Address > 0x0FFFFFFF, then ASSERT().
434 If StartBit is greater than 7, then ASSERT().
435 If EndBit is greater than 7, then ASSERT().
436 If EndBit is less than StartBit, then ASSERT().
437 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
439 @param Address The PCI configuration register to write.
440 @param StartBit The ordinal of the least significant bit in the bit field.
442 @param EndBit The ordinal of the most significant bit in the bit field.
444 @param AndData The value to AND with the PCI configuration register.
446 @return The value written back to the PCI configuration register.
460 BitFieldAnd8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
)
465 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
466 bitwise OR, and writes the result back to the bit field in the
469 Reads the 8-bit PCI configuration register specified by Address, performs a
470 bitwise AND followed by a bitwise OR between the read result and
471 the value specified by AndData, and writes the result to the 8-bit PCI
472 configuration register specified by Address. The value written to the PCI
473 configuration register is returned. This function must guarantee that all PCI
474 read and write operations are serialized. Extra left bits in both AndData and
477 If Address > 0x0FFFFFFF, then ASSERT().
478 If StartBit is greater than 7, then ASSERT().
479 If EndBit is greater than 7, then ASSERT().
480 If EndBit is less than StartBit, then ASSERT().
481 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
482 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
484 @param Address The PCI configuration register to write.
485 @param StartBit The ordinal of the least significant bit in the bit field.
487 @param EndBit The ordinal of the most significant bit in the bit field.
489 @param AndData The value to AND with the PCI configuration register.
490 @param OrData The value to OR with the result of the AND operation.
492 @return The value written back to the PCI configuration register.
497 PciBitFieldAndThenOr8 (
507 BitFieldAndThenOr8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
, OrData
)
512 Reads a 16-bit PCI configuration register.
514 Reads and returns the 16-bit PCI configuration register specified by Address.
515 This function must guarantee that all PCI read and write operations are
518 If Address > 0x0FFFFFFF, then ASSERT().
519 If Address is not aligned on a 16-bit boundary, then ASSERT().
521 @param Address The address that encodes the PCI Bus, Device, Function and
524 @return The read value from the PCI configuration register.
533 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
535 return (UINT16
) PeiPciLibPciCfg2ReadWorker (Address
, EfiPeiPciCfgWidthUint16
);
539 Writes a 16-bit PCI configuration register.
541 Writes the 16-bit PCI configuration register specified by Address with the
542 value specified by Value. Value is returned. This function must guarantee
543 that all PCI read and write operations are serialized.
545 If Address > 0x0FFFFFFF, then ASSERT().
546 If Address is not aligned on a 16-bit boundary, then ASSERT().
548 @param Address The address that encodes the PCI Bus, Device, Function and
550 @param Value The value to write.
552 @return The value written to the PCI configuration register.
562 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
564 return (UINT16
) PeiPciLibPciCfg2WriteWorker (Address
, EfiPeiPciCfgWidthUint16
, Value
);
568 Performs a bitwise OR of a 16-bit PCI configuration register with
571 Reads the 16-bit PCI configuration register specified by Address, performs a
572 bitwise OR between the read result and the value specified by
573 OrData, and writes the result to the 16-bit PCI configuration register
574 specified by Address. The value written to the PCI configuration register is
575 returned. This function must guarantee that all PCI read and write operations
578 If Address > 0x0FFFFFFF, then ASSERT().
579 If Address is not aligned on a 16-bit boundary, then ASSERT().
581 @param Address The address that encodes the PCI Bus, Device, Function and
583 @param OrData The value to OR with the PCI configuration register.
585 @return The value written back to the PCI configuration register.
595 return PciWrite16 (Address
, (UINT16
) (PciRead16 (Address
) | OrData
));
599 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
602 Reads the 16-bit PCI configuration register specified by Address, performs a
603 bitwise AND between the read result and the value specified by AndData, and
604 writes the result to the 16-bit PCI configuration register specified by
605 Address. The value written to the PCI configuration register is returned.
606 This function must guarantee that all PCI read and write operations are
609 If Address > 0x0FFFFFFF, then ASSERT().
610 If Address is not aligned on a 16-bit boundary, then ASSERT().
612 @param Address The address that encodes the PCI Bus, Device, Function and
614 @param AndData The value to AND with the PCI configuration register.
616 @return The value written back to the PCI configuration register.
626 return PciWrite16 (Address
, (UINT16
) (PciRead16 (Address
) & AndData
));
630 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
631 value, followed a bitwise OR with another 16-bit value.
633 Reads the 16-bit PCI configuration register specified by Address, performs a
634 bitwise AND between the read result and the value specified by AndData,
635 performs a bitwise OR between the result of the AND operation and
636 the value specified by OrData, and writes the result to the 16-bit PCI
637 configuration register specified by Address. The value written to the PCI
638 configuration register is returned. This function must guarantee that all PCI
639 read and write operations are serialized.
641 If Address > 0x0FFFFFFF, then ASSERT().
642 If Address is not aligned on a 16-bit boundary, then ASSERT().
644 @param Address The address that encodes the PCI Bus, Device, Function and
646 @param AndData The value to AND with the PCI configuration register.
647 @param OrData The value to OR with the result of the AND operation.
649 @return The value written back to the PCI configuration register.
660 return PciWrite16 (Address
, (UINT16
) ((PciRead16 (Address
) & AndData
) | OrData
));
664 Reads a bit field of a PCI configuration register.
666 Reads the bit field in a 16-bit PCI configuration register. The bit field is
667 specified by the StartBit and the EndBit. The value of the bit field is
670 If Address > 0x0FFFFFFF, then ASSERT().
671 If Address is not aligned on a 16-bit boundary, then ASSERT().
672 If StartBit is greater than 15, then ASSERT().
673 If EndBit is greater than 15, then ASSERT().
674 If EndBit is less than StartBit, then ASSERT().
676 @param Address The PCI configuration register to read.
677 @param StartBit The ordinal of the least significant bit in the bit field.
679 @param EndBit The ordinal of the most significant bit in the bit field.
682 @return The value of the bit field read from the PCI configuration register.
693 return BitFieldRead16 (PciRead16 (Address
), StartBit
, EndBit
);
697 Writes a bit field to a PCI configuration register.
699 Writes Value to the bit field of the PCI configuration register. The bit
700 field is specified by the StartBit and the EndBit. All other bits in the
701 destination PCI configuration register are preserved. The new value of the
702 16-bit register is returned.
704 If Address > 0x0FFFFFFF, then ASSERT().
705 If Address is not aligned on a 16-bit boundary, then ASSERT().
706 If StartBit is greater than 15, then ASSERT().
707 If EndBit is greater than 15, then ASSERT().
708 If EndBit is less than StartBit, then ASSERT().
709 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
711 @param Address The PCI configuration register to write.
712 @param StartBit The ordinal of the least significant bit in the bit field.
714 @param EndBit The ordinal of the most significant bit in the bit field.
716 @param Value The new value of the bit field.
718 @return The value written back to the PCI configuration register.
732 BitFieldWrite16 (PciRead16 (Address
), StartBit
, EndBit
, Value
)
737 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
738 writes the result back to the bit field in the 16-bit port.
740 Reads the 16-bit PCI configuration register specified by Address, performs a
741 bitwise OR between the read result and the value specified by
742 OrData, and writes the result to the 16-bit PCI configuration register
743 specified by Address. The value written to the PCI configuration register is
744 returned. This function must guarantee that all PCI read and write operations
745 are serialized. Extra left bits in OrData are stripped.
747 If Address > 0x0FFFFFFF, then ASSERT().
748 If Address is not aligned on a 16-bit boundary, then ASSERT().
749 If StartBit is greater than 15, then ASSERT().
750 If EndBit is greater than 15, then ASSERT().
751 If EndBit is less than StartBit, then ASSERT().
752 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
754 @param Address The PCI configuration register to write.
755 @param StartBit The ordinal of the least significant bit in the bit field.
757 @param EndBit The ordinal of the most significant bit in the bit field.
759 @param OrData The value to OR with the PCI configuration register.
761 @return The value written back to the PCI configuration register.
775 BitFieldOr16 (PciRead16 (Address
), StartBit
, EndBit
, OrData
)
780 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
781 AND, and writes the result back to the bit field in the 16-bit register.
783 Reads the 16-bit PCI configuration register specified by Address, performs a
784 bitwise AND between the read result and the value specified by AndData, and
785 writes the result to the 16-bit PCI configuration register specified by
786 Address. The value written to the PCI configuration register is returned.
787 This function must guarantee that all PCI read and write operations are
788 serialized. Extra left bits in AndData are stripped.
790 If Address > 0x0FFFFFFF, then ASSERT().
791 If Address is not aligned on a 16-bit boundary, then ASSERT().
792 If StartBit is greater than 15, then ASSERT().
793 If EndBit is greater than 15, then ASSERT().
794 If EndBit is less than StartBit, then ASSERT().
795 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
797 @param Address The PCI configuration register to write.
798 @param StartBit The ordinal of the least significant bit in the bit field.
800 @param EndBit The ordinal of the most significant bit in the bit field.
802 @param AndData The value to AND with the PCI configuration register.
804 @return The value written back to the PCI configuration register.
818 BitFieldAnd16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
)
823 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
824 bitwise OR, and writes the result back to the bit field in the
827 Reads the 16-bit PCI configuration register specified by Address, performs a
828 bitwise AND followed by a bitwise OR between the read result and
829 the value specified by AndData, and writes the result to the 16-bit PCI
830 configuration register specified by Address. The value written to the PCI
831 configuration register is returned. This function must guarantee that all PCI
832 read and write operations are serialized. Extra left bits in both AndData and
835 If Address > 0x0FFFFFFF, then ASSERT().
836 If Address is not aligned on a 16-bit boundary, then ASSERT().
837 If StartBit is greater than 15, then ASSERT().
838 If EndBit is greater than 15, then ASSERT().
839 If EndBit is less than StartBit, then ASSERT().
840 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
841 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
843 @param Address The PCI configuration register to write.
844 @param StartBit The ordinal of the least significant bit in the bit field.
846 @param EndBit The ordinal of the most significant bit in the bit field.
848 @param AndData The value to AND with the PCI configuration register.
849 @param OrData The value to OR with the result of the AND operation.
851 @return The value written back to the PCI configuration register.
856 PciBitFieldAndThenOr16 (
866 BitFieldAndThenOr16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
, OrData
)
871 Reads a 32-bit PCI configuration register.
873 Reads and returns the 32-bit PCI configuration register specified by Address.
874 This function must guarantee that all PCI read and write operations are
877 If Address > 0x0FFFFFFF, then ASSERT().
878 If Address is not aligned on a 32-bit boundary, then ASSERT().
880 @param Address The address that encodes the PCI Bus, Device, Function and
883 @return The read value from the PCI configuration register.
892 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
894 return PeiPciLibPciCfg2ReadWorker (Address
, EfiPeiPciCfgWidthUint32
);
898 Writes a 32-bit PCI configuration register.
900 Writes the 32-bit PCI configuration register specified by Address with the
901 value specified by Value. Value is returned. This function must guarantee
902 that all PCI read and write operations are serialized.
904 If Address > 0x0FFFFFFF, then ASSERT().
905 If Address is not aligned on a 32-bit boundary, then ASSERT().
907 @param Address The address that encodes the PCI Bus, Device, Function and
909 @param Value The value to write.
911 @return The value written to the PCI configuration register.
921 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
923 return PeiPciLibPciCfg2WriteWorker (Address
, EfiPeiPciCfgWidthUint32
, Value
);
927 Performs a bitwise OR of a 32-bit PCI configuration register with
930 Reads the 32-bit PCI configuration register specified by Address, performs a
931 bitwise OR between the read result and the value specified by
932 OrData, and writes the result to the 32-bit PCI configuration register
933 specified by Address. The value written to the PCI configuration register is
934 returned. This function must guarantee that all PCI read and write operations
937 If Address > 0x0FFFFFFF, then ASSERT().
938 If Address is not aligned on a 32-bit boundary, then ASSERT().
940 @param Address The address that encodes the PCI Bus, Device, Function and
942 @param OrData The value to OR with the PCI configuration register.
944 @return The value written back to the PCI configuration register.
954 return PciWrite32 (Address
, PciRead32 (Address
) | OrData
);
958 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
961 Reads the 32-bit PCI configuration register specified by Address, performs a
962 bitwise AND between the read result and the value specified by AndData, and
963 writes the result to the 32-bit PCI configuration register specified by
964 Address. The value written to the PCI configuration register is returned.
965 This function must guarantee that all PCI read and write operations are
968 If Address > 0x0FFFFFFF, then ASSERT().
969 If Address is not aligned on a 32-bit boundary, then ASSERT().
971 @param Address The address that encodes the PCI Bus, Device, Function and
973 @param AndData The value to AND with the PCI configuration register.
975 @return The value written back to the PCI configuration register.
985 return PciWrite32 (Address
, PciRead32 (Address
) & AndData
);
989 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
990 value, followed a bitwise OR with another 32-bit value.
992 Reads the 32-bit PCI configuration register specified by Address, performs a
993 bitwise AND between the read result and the value specified by AndData,
994 performs a bitwise OR between the result of the AND operation and
995 the value specified by OrData, and writes the result to the 32-bit PCI
996 configuration register specified by Address. The value written to the PCI
997 configuration register is returned. This function must guarantee that all PCI
998 read and write operations are serialized.
1000 If Address > 0x0FFFFFFF, then ASSERT().
1001 If Address is not aligned on a 32-bit boundary, then ASSERT().
1003 @param Address The address that encodes the PCI Bus, Device, Function and
1005 @param AndData The value to AND with the PCI configuration register.
1006 @param OrData The value to OR with the result of the AND operation.
1008 @return The value written back to the PCI configuration register.
1019 return PciWrite32 (Address
, (PciRead32 (Address
) & AndData
) | OrData
);
1023 Reads a bit field of a PCI configuration register.
1025 Reads the bit field in a 32-bit PCI configuration register. The bit field is
1026 specified by the StartBit and the EndBit. The value of the bit field is
1029 If Address > 0x0FFFFFFF, then ASSERT().
1030 If Address is not aligned on a 32-bit boundary, then ASSERT().
1031 If StartBit is greater than 31, then ASSERT().
1032 If EndBit is greater than 31, then ASSERT().
1033 If EndBit is less than StartBit, then ASSERT().
1035 @param Address The PCI configuration register to read.
1036 @param StartBit The ordinal of the least significant bit in the bit field.
1038 @param EndBit The ordinal of the most significant bit in the bit field.
1041 @return The value of the bit field read from the PCI configuration register.
1052 return BitFieldRead32 (PciRead32 (Address
), StartBit
, EndBit
);
1056 Writes a bit field to a PCI configuration register.
1058 Writes Value to the bit field of the PCI configuration register. The bit
1059 field is specified by the StartBit and the EndBit. All other bits in the
1060 destination PCI configuration register are preserved. The new value of the
1061 32-bit register is returned.
1063 If Address > 0x0FFFFFFF, then ASSERT().
1064 If Address is not aligned on a 32-bit boundary, then ASSERT().
1065 If StartBit is greater than 31, then ASSERT().
1066 If EndBit is greater than 31, then ASSERT().
1067 If EndBit is less than StartBit, then ASSERT().
1068 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1070 @param Address The PCI configuration register to write.
1071 @param StartBit The ordinal of the least significant bit in the bit field.
1073 @param EndBit The ordinal of the most significant bit in the bit field.
1075 @param Value The new value of the bit field.
1077 @return The value written back to the PCI configuration register.
1082 PciBitFieldWrite32 (
1091 BitFieldWrite32 (PciRead32 (Address
), StartBit
, EndBit
, Value
)
1096 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1097 writes the result back to the bit field in the 32-bit port.
1099 Reads the 32-bit PCI configuration register specified by Address, performs a
1100 bitwise OR between the read result and the value specified by
1101 OrData, and writes the result to the 32-bit PCI configuration register
1102 specified by Address. The value written to the PCI configuration register is
1103 returned. This function must guarantee that all PCI read and write operations
1104 are serialized. Extra left bits in OrData are stripped.
1106 If Address > 0x0FFFFFFF, then ASSERT().
1107 If Address is not aligned on a 32-bit boundary, then ASSERT().
1108 If StartBit is greater than 31, then ASSERT().
1109 If EndBit is greater than 31, then ASSERT().
1110 If EndBit is less than StartBit, then ASSERT().
1111 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1113 @param Address The PCI configuration register to write.
1114 @param StartBit The ordinal of the least significant bit in the bit field.
1116 @param EndBit The ordinal of the most significant bit in the bit field.
1118 @param OrData The value to OR with the PCI configuration register.
1120 @return The value written back to the PCI configuration register.
1134 BitFieldOr32 (PciRead32 (Address
), StartBit
, EndBit
, OrData
)
1139 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1140 AND, and writes the result back to the bit field in the 32-bit register.
1142 Reads the 32-bit PCI configuration register specified by Address, performs a
1143 bitwise AND between the read result and the value specified by AndData, and
1144 writes the result to the 32-bit PCI configuration register specified by
1145 Address. The value written to the PCI configuration register is returned.
1146 This function must guarantee that all PCI read and write operations are
1147 serialized. Extra left bits in AndData are stripped.
1149 If Address > 0x0FFFFFFF, then ASSERT().
1150 If Address is not aligned on a 32-bit boundary, then ASSERT().
1151 If StartBit is greater than 31, then ASSERT().
1152 If EndBit is greater than 31, then ASSERT().
1153 If EndBit is less than StartBit, then ASSERT().
1154 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1156 @param Address The PCI configuration register to write.
1157 @param StartBit The ordinal of the least significant bit in the bit field.
1159 @param EndBit The ordinal of the most significant bit in the bit field.
1161 @param AndData The value to AND with the PCI configuration register.
1163 @return The value written back to the PCI configuration register.
1177 BitFieldAnd32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
)
1182 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1183 bitwise OR, and writes the result back to the bit field in the
1186 Reads the 32-bit PCI configuration register specified by Address, performs a
1187 bitwise AND followed by a bitwise OR between the read result and
1188 the value specified by AndData, and writes the result to the 32-bit PCI
1189 configuration register specified by Address. The value written to the PCI
1190 configuration register is returned. This function must guarantee that all PCI
1191 read and write operations are serialized. Extra left bits in both AndData and
1192 OrData are stripped.
1194 If Address > 0x0FFFFFFF, then ASSERT().
1195 If Address is not aligned on a 32-bit boundary, then ASSERT().
1196 If StartBit is greater than 31, then ASSERT().
1197 If EndBit is greater than 31, then ASSERT().
1198 If EndBit is less than StartBit, then ASSERT().
1199 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1200 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1202 @param Address The PCI configuration register to write.
1203 @param StartBit The ordinal of the least significant bit in the bit field.
1205 @param EndBit The ordinal of the most significant bit in the bit field.
1207 @param AndData The value to AND with the PCI configuration register.
1208 @param OrData The value to OR with the result of the AND operation.
1210 @return The value written back to the PCI configuration register.
1215 PciBitFieldAndThenOr32 (
1225 BitFieldAndThenOr32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
, OrData
)
1230 Reads a range of PCI configuration registers into a caller supplied buffer.
1232 Reads the range of PCI configuration registers specified by StartAddress and
1233 Size into the buffer specified by Buffer. This function only allows the PCI
1234 configuration registers from a single PCI function to be read. Size is
1235 returned. When possible 32-bit PCI configuration read cycles are used to read
1236 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1237 and 16-bit PCI configuration read cycles may be used at the beginning and the
1240 If StartAddress > 0x0FFFFFFF, then ASSERT().
1241 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1242 If Size > 0 and Buffer is NULL, then ASSERT().
1244 @param StartAddress The starting address that encodes the PCI Bus, Device,
1245 Function and Register.
1246 @param Size The size in bytes of the transfer.
1247 @param Buffer The pointer to a buffer receiving the data read.
1255 IN UINTN StartAddress
,
1262 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1263 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1269 ASSERT (Buffer
!= NULL
);
1272 // Save Size for return
1276 if ((StartAddress
& BIT0
) != 0) {
1278 // Read a byte if StartAddress is byte aligned
1280 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1281 StartAddress
+= sizeof (UINT8
);
1282 Size
-= sizeof (UINT8
);
1283 Buffer
= (UINT8
*)Buffer
+ 1;
1286 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1288 // Read a word if StartAddress is word aligned
1290 WriteUnaligned16 (Buffer
, PciRead16 (StartAddress
));
1291 StartAddress
+= sizeof (UINT16
);
1292 Size
-= sizeof (UINT16
);
1293 Buffer
= (UINT16
*)Buffer
+ 1;
1296 while (Size
>= sizeof (UINT32
)) {
1298 // Read as many double words as possible
1300 WriteUnaligned32 (Buffer
, PciRead32 (StartAddress
));
1301 StartAddress
+= sizeof (UINT32
);
1302 Size
-= sizeof (UINT32
);
1303 Buffer
= (UINT32
*)Buffer
+ 1;
1306 if (Size
>= sizeof (UINT16
)) {
1308 // Read the last remaining word if exist
1310 WriteUnaligned16 (Buffer
, PciRead16 (StartAddress
));
1311 StartAddress
+= sizeof (UINT16
);
1312 Size
-= sizeof (UINT16
);
1313 Buffer
= (UINT16
*)Buffer
+ 1;
1316 if (Size
>= sizeof (UINT8
)) {
1318 // Read the last remaining byte if exist
1320 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1327 Copies the data in a caller supplied buffer to a specified range of PCI
1328 configuration space.
1330 Writes the range of PCI configuration registers specified by StartAddress and
1331 Size from the buffer specified by Buffer. This function only allows the PCI
1332 configuration registers from a single PCI function to be written. Size is
1333 returned. When possible 32-bit PCI configuration write cycles are used to
1334 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1335 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1336 and the end of the range.
1338 If StartAddress > 0x0FFFFFFF, then ASSERT().
1339 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1340 If Size > 0 and Buffer is NULL, then ASSERT().
1342 @param StartAddress The starting address that encodes the PCI Bus, Device,
1343 Function and Register.
1344 @param Size The size in bytes of the transfer.
1345 @param Buffer The pointer to a buffer containing the data to write.
1347 @return Size written to StartAddress.
1353 IN UINTN StartAddress
,
1360 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1361 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1367 ASSERT (Buffer
!= NULL
);
1370 // Save Size for return
1374 if ((StartAddress
& BIT0
) != 0) {
1376 // Write a byte if StartAddress is byte aligned
1378 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1379 StartAddress
+= sizeof (UINT8
);
1380 Size
-= sizeof (UINT8
);
1381 Buffer
= (UINT8
*)Buffer
+ 1;
1384 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1386 // Write a word if StartAddress is word aligned
1388 PciWrite16 (StartAddress
, ReadUnaligned16 (Buffer
));
1389 StartAddress
+= sizeof (UINT16
);
1390 Size
-= sizeof (UINT16
);
1391 Buffer
= (UINT16
*)Buffer
+ 1;
1394 while (Size
>= sizeof (UINT32
)) {
1396 // Write as many double words as possible
1398 PciWrite32 (StartAddress
, ReadUnaligned32 (Buffer
));
1399 StartAddress
+= sizeof (UINT32
);
1400 Size
-= sizeof (UINT32
);
1401 Buffer
= (UINT32
*)Buffer
+ 1;
1404 if (Size
>= sizeof (UINT16
)) {
1406 // Write the last remaining word if exist
1408 PciWrite16 (StartAddress
, ReadUnaligned16 (Buffer
));
1409 StartAddress
+= sizeof (UINT16
);
1410 Size
-= sizeof (UINT16
);
1411 Buffer
= (UINT16
*)Buffer
+ 1;
1414 if (Size
>= sizeof (UINT8
)) {
1416 // Write the last remaining byte if exist
1418 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);