2 PCI Library using PCI CFG2 PPI.
4 Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
11 #include <Ppi/PciCfg2.h>
13 #include <Library/PciLib.h>
14 #include <Library/BaseLib.h>
15 #include <Library/PeiServicesTablePointerLib.h>
16 #include <Library/DebugLib.h>
17 #include <Library/PeiServicesLib.h>
20 Assert the validity of a PCI address. A valid PCI address should contain 1's
21 only in the low 28 bits.
23 @param A The address to validate.
24 @param M Additional bits to assert to be zero.
27 #define ASSERT_INVALID_PCI_ADDRESS(A,M) \
28 ASSERT (((A) & (~0xfffffff | (M))) == 0)
31 Translate PCI Lib address into format of PCI CFG2 PPI.
33 @param A The address that encodes the PCI Bus, Device, Function and
37 #define PCI_TO_PCICFG2_ADDRESS(A) \
38 ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))
41 Internal worker function to read a PCI configuration register.
43 This function wraps EFI_PEI_PCI_CFG2_PPI.Read() service.
44 It reads and returns the PCI configuration register specified by Address,
45 the width of data is specified by Width.
47 @param Address The address that encodes the PCI Bus, Device, Function and
49 @param Width The width of data to read
51 @return The value read from the PCI configuration register.
55 PeiPciLibPciCfg2ReadWorker (
57 IN EFI_PEI_PCI_CFG_PPI_WIDTH Width
62 CONST EFI_PEI_PCI_CFG2_PPI
*PciCfg2Ppi
;
63 UINT64 PciCfg2Address
;
65 Status
= PeiServicesLocatePpi (&gEfiPciCfg2PpiGuid
, 0, NULL
, (VOID
**) &PciCfg2Ppi
);
66 ASSERT_EFI_ERROR (Status
);
67 ASSERT (PciCfg2Ppi
!= NULL
);
69 PciCfg2Address
= PCI_TO_PCICFG2_ADDRESS (Address
);
71 GetPeiServicesTablePointer (),
82 Internal worker function to writes a PCI configuration register.
84 This function wraps EFI_PEI_PCI_CFG2_PPI.Write() service.
85 It writes the PCI configuration register specified by Address with the
86 value specified by Data. The width of data is specified by Width.
89 @param Address The address that encodes the PCI Bus, Device, Function and
91 @param Width The width of data to write
92 @param Data The value to write.
94 @return The value written to the PCI configuration register.
98 PeiPciLibPciCfg2WriteWorker (
100 IN EFI_PEI_PCI_CFG_PPI_WIDTH Width
,
105 CONST EFI_PEI_PCI_CFG2_PPI
*PciCfg2Ppi
;
106 UINT64 PciCfg2Address
;
108 Status
= PeiServicesLocatePpi (&gEfiPciCfg2PpiGuid
, 0, NULL
, (VOID
**) &PciCfg2Ppi
);
109 ASSERT_EFI_ERROR (Status
);
110 ASSERT (PciCfg2Ppi
!= NULL
);
112 PciCfg2Address
= PCI_TO_PCICFG2_ADDRESS (Address
);
114 GetPeiServicesTablePointer (),
125 Registers a PCI device so PCI configuration registers may be accessed after
126 SetVirtualAddressMap().
128 Registers the PCI device specified by Address so all the PCI configuration registers
129 associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
131 If Address > 0x0FFFFFFF, then ASSERT().
133 @param Address The address that encodes the PCI Bus, Device, Function and
136 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
137 @retval RETURN_UNSUPPORTED An attempt was made to call this function
138 after ExitBootServices().
139 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
140 at runtime could not be mapped.
141 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
142 complete the registration.
147 PciRegisterForRuntimeAccess (
151 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
152 return RETURN_UNSUPPORTED
;
156 Reads an 8-bit PCI configuration register.
158 Reads and returns the 8-bit PCI configuration register specified by Address.
159 This function must guarantee that all PCI read and write operations are
162 If Address > 0x0FFFFFFF, then ASSERT().
164 @param Address The address that encodes the PCI Bus, Device, Function and
167 @return The read value from the PCI configuration register.
176 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
178 return (UINT8
) PeiPciLibPciCfg2ReadWorker (Address
, EfiPeiPciCfgWidthUint8
);
182 Writes an 8-bit PCI configuration register.
184 Writes the 8-bit PCI configuration register specified by Address with the
185 value specified by Value. Value is returned. This function must guarantee
186 that all PCI read and write operations are serialized.
188 If Address > 0x0FFFFFFF, then ASSERT().
190 @param Address The address that encodes the PCI Bus, Device, Function and
192 @param Value The value to write.
194 @return The value written to the PCI configuration register.
204 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
206 return (UINT8
) PeiPciLibPciCfg2WriteWorker (Address
, EfiPeiPciCfgWidthUint8
, Value
);
210 Performs a bitwise OR of an 8-bit PCI configuration register with
213 Reads the 8-bit PCI configuration register specified by Address, performs a
214 bitwise OR between the read result and the value specified by
215 OrData, and writes the result to the 8-bit PCI configuration register
216 specified by Address. The value written to the PCI configuration register is
217 returned. This function must guarantee that all PCI read and write operations
220 If Address > 0x0FFFFFFF, then ASSERT().
222 @param Address The address that encodes the PCI Bus, Device, Function and
224 @param OrData The value to OR with the PCI configuration register.
226 @return The value written back to the PCI configuration register.
236 return PciWrite8 (Address
, (UINT8
) (PciRead8 (Address
) | OrData
));
240 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
243 Reads the 8-bit PCI configuration register specified by Address, performs a
244 bitwise AND between the read result and the value specified by AndData, and
245 writes the result to the 8-bit PCI configuration register specified by
246 Address. The value written to the PCI configuration register is returned.
247 This function must guarantee that all PCI read and write operations are
250 If Address > 0x0FFFFFFF, then ASSERT().
252 @param Address The address that encodes the PCI Bus, Device, Function and
254 @param AndData The value to AND with the PCI configuration register.
256 @return The value written back to the PCI configuration register.
266 return PciWrite8 (Address
, (UINT8
) (PciRead8 (Address
) & AndData
));
270 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
271 value, followed a bitwise OR with another 8-bit value.
273 Reads the 8-bit PCI configuration register specified by Address, performs a
274 bitwise AND between the read result and the value specified by AndData,
275 performs a bitwise OR between the result of the AND operation and
276 the value specified by OrData, and writes the result to the 8-bit PCI
277 configuration register specified by Address. The value written to the PCI
278 configuration register is returned. This function must guarantee that all PCI
279 read and write operations are serialized.
281 If Address > 0x0FFFFFFF, then ASSERT().
283 @param Address The address that encodes the PCI Bus, Device, Function and
285 @param AndData The value to AND with the PCI configuration register.
286 @param OrData The value to OR with the result of the AND operation.
288 @return The value written back to the PCI configuration register.
299 return PciWrite8 (Address
, (UINT8
) ((PciRead8 (Address
) & AndData
) | OrData
));
303 Reads a bit field of a PCI configuration register.
305 Reads the bit field in an 8-bit PCI configuration register. The bit field is
306 specified by the StartBit and the EndBit. The value of the bit field is
309 If Address > 0x0FFFFFFF, then ASSERT().
310 If StartBit is greater than 7, then ASSERT().
311 If EndBit is greater than 7, then ASSERT().
312 If EndBit is less than StartBit, then ASSERT().
314 @param Address The PCI configuration register to read.
315 @param StartBit The ordinal of the least significant bit in the bit field.
317 @param EndBit The ordinal of the most significant bit in the bit field.
320 @return The value of the bit field read from the PCI configuration register.
331 return BitFieldRead8 (PciRead8 (Address
), StartBit
, EndBit
);
335 Writes a bit field to a PCI configuration register.
337 Writes Value to the bit field of the PCI configuration register. The bit
338 field is specified by the StartBit and the EndBit. All other bits in the
339 destination PCI configuration register are preserved. The new value of the
340 8-bit register is returned.
342 If Address > 0x0FFFFFFF, then ASSERT().
343 If StartBit is greater than 7, then ASSERT().
344 If EndBit is greater than 7, then ASSERT().
345 If EndBit is less than StartBit, then ASSERT().
346 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
348 @param Address The PCI configuration register to write.
349 @param StartBit The ordinal of the least significant bit in the bit field.
351 @param EndBit The ordinal of the most significant bit in the bit field.
353 @param Value The new value of the bit field.
355 @return The value written back to the PCI configuration register.
369 BitFieldWrite8 (PciRead8 (Address
), StartBit
, EndBit
, Value
)
374 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
375 writes the result back to the bit field in the 8-bit port.
377 Reads the 8-bit PCI configuration register specified by Address, performs a
378 bitwise OR between the read result and the value specified by
379 OrData, and writes the result to the 8-bit PCI configuration register
380 specified by Address. The value written to the PCI configuration register is
381 returned. This function must guarantee that all PCI read and write operations
382 are serialized. Extra left bits in OrData are stripped.
384 If Address > 0x0FFFFFFF, then ASSERT().
385 If StartBit is greater than 7, then ASSERT().
386 If EndBit is greater than 7, then ASSERT().
387 If EndBit is less than StartBit, then ASSERT().
388 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
390 @param Address The PCI configuration register to write.
391 @param StartBit The ordinal of the least significant bit in the bit field.
393 @param EndBit The ordinal of the most significant bit in the bit field.
395 @param OrData The value to OR with the PCI configuration register.
397 @return The value written back to the PCI configuration register.
411 BitFieldOr8 (PciRead8 (Address
), StartBit
, EndBit
, OrData
)
416 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
417 AND, and writes the result back to the bit field in the 8-bit register.
419 Reads the 8-bit PCI configuration register specified by Address, performs a
420 bitwise AND between the read result and the value specified by AndData, and
421 writes the result to the 8-bit PCI configuration register specified by
422 Address. The value written to the PCI configuration register is returned.
423 This function must guarantee that all PCI read and write operations are
424 serialized. Extra left bits in AndData are stripped.
426 If Address > 0x0FFFFFFF, then ASSERT().
427 If StartBit is greater than 7, then ASSERT().
428 If EndBit is greater than 7, then ASSERT().
429 If EndBit is less than StartBit, then ASSERT().
430 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
432 @param Address The PCI configuration register to write.
433 @param StartBit The ordinal of the least significant bit in the bit field.
435 @param EndBit The ordinal of the most significant bit in the bit field.
437 @param AndData The value to AND with the PCI configuration register.
439 @return The value written back to the PCI configuration register.
453 BitFieldAnd8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
)
458 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
459 bitwise OR, and writes the result back to the bit field in the
462 Reads the 8-bit PCI configuration register specified by Address, performs a
463 bitwise AND followed by a bitwise OR between the read result and
464 the value specified by AndData, and writes the result to the 8-bit PCI
465 configuration register specified by Address. The value written to the PCI
466 configuration register is returned. This function must guarantee that all PCI
467 read and write operations are serialized. Extra left bits in both AndData and
470 If Address > 0x0FFFFFFF, then ASSERT().
471 If StartBit is greater than 7, then ASSERT().
472 If EndBit is greater than 7, then ASSERT().
473 If EndBit is less than StartBit, then ASSERT().
474 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
475 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
477 @param Address The PCI configuration register to write.
478 @param StartBit The ordinal of the least significant bit in the bit field.
480 @param EndBit The ordinal of the most significant bit in the bit field.
482 @param AndData The value to AND with the PCI configuration register.
483 @param OrData The value to OR with the result of the AND operation.
485 @return The value written back to the PCI configuration register.
490 PciBitFieldAndThenOr8 (
500 BitFieldAndThenOr8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
, OrData
)
505 Reads a 16-bit PCI configuration register.
507 Reads and returns the 16-bit PCI configuration register specified by Address.
508 This function must guarantee that all PCI read and write operations are
511 If Address > 0x0FFFFFFF, then ASSERT().
512 If Address is not aligned on a 16-bit boundary, then ASSERT().
514 @param Address The address that encodes the PCI Bus, Device, Function and
517 @return The read value from the PCI configuration register.
526 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
528 return (UINT16
) PeiPciLibPciCfg2ReadWorker (Address
, EfiPeiPciCfgWidthUint16
);
532 Writes a 16-bit PCI configuration register.
534 Writes the 16-bit PCI configuration register specified by Address with the
535 value specified by Value. Value is returned. This function must guarantee
536 that all PCI read and write operations are serialized.
538 If Address > 0x0FFFFFFF, then ASSERT().
539 If Address is not aligned on a 16-bit boundary, then ASSERT().
541 @param Address The address that encodes the PCI Bus, Device, Function and
543 @param Value The value to write.
545 @return The value written to the PCI configuration register.
555 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
557 return (UINT16
) PeiPciLibPciCfg2WriteWorker (Address
, EfiPeiPciCfgWidthUint16
, Value
);
561 Performs a bitwise OR of a 16-bit PCI configuration register with
564 Reads the 16-bit PCI configuration register specified by Address, performs a
565 bitwise OR between the read result and the value specified by
566 OrData, and writes the result to the 16-bit PCI configuration register
567 specified by Address. The value written to the PCI configuration register is
568 returned. This function must guarantee that all PCI read and write operations
571 If Address > 0x0FFFFFFF, then ASSERT().
572 If Address is not aligned on a 16-bit boundary, then ASSERT().
574 @param Address The address that encodes the PCI Bus, Device, Function and
576 @param OrData The value to OR with the PCI configuration register.
578 @return The value written back to the PCI configuration register.
588 return PciWrite16 (Address
, (UINT16
) (PciRead16 (Address
) | OrData
));
592 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
595 Reads the 16-bit PCI configuration register specified by Address, performs a
596 bitwise AND between the read result and the value specified by AndData, and
597 writes the result to the 16-bit PCI configuration register specified by
598 Address. The value written to the PCI configuration register is returned.
599 This function must guarantee that all PCI read and write operations are
602 If Address > 0x0FFFFFFF, then ASSERT().
603 If Address is not aligned on a 16-bit boundary, then ASSERT().
605 @param Address The address that encodes the PCI Bus, Device, Function and
607 @param AndData The value to AND with the PCI configuration register.
609 @return The value written back to the PCI configuration register.
619 return PciWrite16 (Address
, (UINT16
) (PciRead16 (Address
) & AndData
));
623 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
624 value, followed a bitwise OR with another 16-bit value.
626 Reads the 16-bit PCI configuration register specified by Address, performs a
627 bitwise AND between the read result and the value specified by AndData,
628 performs a bitwise OR between the result of the AND operation and
629 the value specified by OrData, and writes the result to the 16-bit PCI
630 configuration register specified by Address. The value written to the PCI
631 configuration register is returned. This function must guarantee that all PCI
632 read and write operations are serialized.
634 If Address > 0x0FFFFFFF, then ASSERT().
635 If Address is not aligned on a 16-bit boundary, then ASSERT().
637 @param Address The address that encodes the PCI Bus, Device, Function and
639 @param AndData The value to AND with the PCI configuration register.
640 @param OrData The value to OR with the result of the AND operation.
642 @return The value written back to the PCI configuration register.
653 return PciWrite16 (Address
, (UINT16
) ((PciRead16 (Address
) & AndData
) | OrData
));
657 Reads a bit field of a PCI configuration register.
659 Reads the bit field in a 16-bit PCI configuration register. The bit field is
660 specified by the StartBit and the EndBit. The value of the bit field is
663 If Address > 0x0FFFFFFF, then ASSERT().
664 If Address is not aligned on a 16-bit boundary, then ASSERT().
665 If StartBit is greater than 15, then ASSERT().
666 If EndBit is greater than 15, then ASSERT().
667 If EndBit is less than StartBit, then ASSERT().
669 @param Address The PCI configuration register to read.
670 @param StartBit The ordinal of the least significant bit in the bit field.
672 @param EndBit The ordinal of the most significant bit in the bit field.
675 @return The value of the bit field read from the PCI configuration register.
686 return BitFieldRead16 (PciRead16 (Address
), StartBit
, EndBit
);
690 Writes a bit field to a PCI configuration register.
692 Writes Value to the bit field of the PCI configuration register. The bit
693 field is specified by the StartBit and the EndBit. All other bits in the
694 destination PCI configuration register are preserved. The new value of the
695 16-bit register is returned.
697 If Address > 0x0FFFFFFF, then ASSERT().
698 If Address is not aligned on a 16-bit boundary, then ASSERT().
699 If StartBit is greater than 15, then ASSERT().
700 If EndBit is greater than 15, then ASSERT().
701 If EndBit is less than StartBit, then ASSERT().
702 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
704 @param Address The PCI configuration register to write.
705 @param StartBit The ordinal of the least significant bit in the bit field.
707 @param EndBit The ordinal of the most significant bit in the bit field.
709 @param Value The new value of the bit field.
711 @return The value written back to the PCI configuration register.
725 BitFieldWrite16 (PciRead16 (Address
), StartBit
, EndBit
, Value
)
730 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
731 writes the result back to the bit field in the 16-bit port.
733 Reads the 16-bit PCI configuration register specified by Address, performs a
734 bitwise OR between the read result and the value specified by
735 OrData, and writes the result to the 16-bit PCI configuration register
736 specified by Address. The value written to the PCI configuration register is
737 returned. This function must guarantee that all PCI read and write operations
738 are serialized. Extra left bits in OrData are stripped.
740 If Address > 0x0FFFFFFF, then ASSERT().
741 If Address is not aligned on a 16-bit boundary, then ASSERT().
742 If StartBit is greater than 15, then ASSERT().
743 If EndBit is greater than 15, then ASSERT().
744 If EndBit is less than StartBit, then ASSERT().
745 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
747 @param Address The PCI configuration register to write.
748 @param StartBit The ordinal of the least significant bit in the bit field.
750 @param EndBit The ordinal of the most significant bit in the bit field.
752 @param OrData The value to OR with the PCI configuration register.
754 @return The value written back to the PCI configuration register.
768 BitFieldOr16 (PciRead16 (Address
), StartBit
, EndBit
, OrData
)
773 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
774 AND, and writes the result back to the bit field in the 16-bit register.
776 Reads the 16-bit PCI configuration register specified by Address, performs a
777 bitwise AND between the read result and the value specified by AndData, and
778 writes the result to the 16-bit PCI configuration register specified by
779 Address. The value written to the PCI configuration register is returned.
780 This function must guarantee that all PCI read and write operations are
781 serialized. Extra left bits in AndData are stripped.
783 If Address > 0x0FFFFFFF, then ASSERT().
784 If Address is not aligned on a 16-bit boundary, then ASSERT().
785 If StartBit is greater than 15, then ASSERT().
786 If EndBit is greater than 15, then ASSERT().
787 If EndBit is less than StartBit, then ASSERT().
788 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
790 @param Address The PCI configuration register to write.
791 @param StartBit The ordinal of the least significant bit in the bit field.
793 @param EndBit The ordinal of the most significant bit in the bit field.
795 @param AndData The value to AND with the PCI configuration register.
797 @return The value written back to the PCI configuration register.
811 BitFieldAnd16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
)
816 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
817 bitwise OR, and writes the result back to the bit field in the
820 Reads the 16-bit PCI configuration register specified by Address, performs a
821 bitwise AND followed by a bitwise OR between the read result and
822 the value specified by AndData, and writes the result to the 16-bit PCI
823 configuration register specified by Address. The value written to the PCI
824 configuration register is returned. This function must guarantee that all PCI
825 read and write operations are serialized. Extra left bits in both AndData and
828 If Address > 0x0FFFFFFF, then ASSERT().
829 If Address is not aligned on a 16-bit boundary, then ASSERT().
830 If StartBit is greater than 15, then ASSERT().
831 If EndBit is greater than 15, then ASSERT().
832 If EndBit is less than StartBit, then ASSERT().
833 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
834 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
836 @param Address The PCI configuration register to write.
837 @param StartBit The ordinal of the least significant bit in the bit field.
839 @param EndBit The ordinal of the most significant bit in the bit field.
841 @param AndData The value to AND with the PCI configuration register.
842 @param OrData The value to OR with the result of the AND operation.
844 @return The value written back to the PCI configuration register.
849 PciBitFieldAndThenOr16 (
859 BitFieldAndThenOr16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
, OrData
)
864 Reads a 32-bit PCI configuration register.
866 Reads and returns the 32-bit PCI configuration register specified by Address.
867 This function must guarantee that all PCI read and write operations are
870 If Address > 0x0FFFFFFF, then ASSERT().
871 If Address is not aligned on a 32-bit boundary, then ASSERT().
873 @param Address The address that encodes the PCI Bus, Device, Function and
876 @return The read value from the PCI configuration register.
885 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
887 return PeiPciLibPciCfg2ReadWorker (Address
, EfiPeiPciCfgWidthUint32
);
891 Writes a 32-bit PCI configuration register.
893 Writes the 32-bit PCI configuration register specified by Address with the
894 value specified by Value. Value is returned. This function must guarantee
895 that all PCI read and write operations are serialized.
897 If Address > 0x0FFFFFFF, then ASSERT().
898 If Address is not aligned on a 32-bit boundary, then ASSERT().
900 @param Address The address that encodes the PCI Bus, Device, Function and
902 @param Value The value to write.
904 @return The value written to the PCI configuration register.
914 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
916 return PeiPciLibPciCfg2WriteWorker (Address
, EfiPeiPciCfgWidthUint32
, Value
);
920 Performs a bitwise OR of a 32-bit PCI configuration register with
923 Reads the 32-bit PCI configuration register specified by Address, performs a
924 bitwise OR between the read result and the value specified by
925 OrData, and writes the result to the 32-bit PCI configuration register
926 specified by Address. The value written to the PCI configuration register is
927 returned. This function must guarantee that all PCI read and write operations
930 If Address > 0x0FFFFFFF, then ASSERT().
931 If Address is not aligned on a 32-bit boundary, then ASSERT().
933 @param Address The address that encodes the PCI Bus, Device, Function and
935 @param OrData The value to OR with the PCI configuration register.
937 @return The value written back to the PCI configuration register.
947 return PciWrite32 (Address
, PciRead32 (Address
) | OrData
);
951 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
954 Reads the 32-bit PCI configuration register specified by Address, performs a
955 bitwise AND between the read result and the value specified by AndData, and
956 writes the result to the 32-bit PCI configuration register specified by
957 Address. The value written to the PCI configuration register is returned.
958 This function must guarantee that all PCI read and write operations are
961 If Address > 0x0FFFFFFF, then ASSERT().
962 If Address is not aligned on a 32-bit boundary, then ASSERT().
964 @param Address The address that encodes the PCI Bus, Device, Function and
966 @param AndData The value to AND with the PCI configuration register.
968 @return The value written back to the PCI configuration register.
978 return PciWrite32 (Address
, PciRead32 (Address
) & AndData
);
982 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
983 value, followed a bitwise OR with another 32-bit value.
985 Reads the 32-bit PCI configuration register specified by Address, performs a
986 bitwise AND between the read result and the value specified by AndData,
987 performs a bitwise OR between the result of the AND operation and
988 the value specified by OrData, and writes the result to the 32-bit PCI
989 configuration register specified by Address. The value written to the PCI
990 configuration register is returned. This function must guarantee that all PCI
991 read and write operations are serialized.
993 If Address > 0x0FFFFFFF, then ASSERT().
994 If Address is not aligned on a 32-bit boundary, then ASSERT().
996 @param Address The address that encodes the PCI Bus, Device, Function and
998 @param AndData The value to AND with the PCI configuration register.
999 @param OrData The value to OR with the result of the AND operation.
1001 @return The value written back to the PCI configuration register.
1012 return PciWrite32 (Address
, (PciRead32 (Address
) & AndData
) | OrData
);
1016 Reads a bit field of a PCI configuration register.
1018 Reads the bit field in a 32-bit PCI configuration register. The bit field is
1019 specified by the StartBit and the EndBit. The value of the bit field is
1022 If Address > 0x0FFFFFFF, then ASSERT().
1023 If Address is not aligned on a 32-bit boundary, then ASSERT().
1024 If StartBit is greater than 31, then ASSERT().
1025 If EndBit is greater than 31, then ASSERT().
1026 If EndBit is less than StartBit, then ASSERT().
1028 @param Address The PCI configuration register to read.
1029 @param StartBit The ordinal of the least significant bit in the bit field.
1031 @param EndBit The ordinal of the most significant bit in the bit field.
1034 @return The value of the bit field read from the PCI configuration register.
1045 return BitFieldRead32 (PciRead32 (Address
), StartBit
, EndBit
);
1049 Writes a bit field to a PCI configuration register.
1051 Writes Value to the bit field of the PCI configuration register. The bit
1052 field is specified by the StartBit and the EndBit. All other bits in the
1053 destination PCI configuration register are preserved. The new value of the
1054 32-bit register is returned.
1056 If Address > 0x0FFFFFFF, then ASSERT().
1057 If Address is not aligned on a 32-bit boundary, then ASSERT().
1058 If StartBit is greater than 31, then ASSERT().
1059 If EndBit is greater than 31, then ASSERT().
1060 If EndBit is less than StartBit, then ASSERT().
1061 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1063 @param Address The PCI configuration register to write.
1064 @param StartBit The ordinal of the least significant bit in the bit field.
1066 @param EndBit The ordinal of the most significant bit in the bit field.
1068 @param Value The new value of the bit field.
1070 @return The value written back to the PCI configuration register.
1075 PciBitFieldWrite32 (
1084 BitFieldWrite32 (PciRead32 (Address
), StartBit
, EndBit
, Value
)
1089 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1090 writes the result back to the bit field in the 32-bit port.
1092 Reads the 32-bit PCI configuration register specified by Address, performs a
1093 bitwise OR between the read result and the value specified by
1094 OrData, and writes the result to the 32-bit PCI configuration register
1095 specified by Address. The value written to the PCI configuration register is
1096 returned. This function must guarantee that all PCI read and write operations
1097 are serialized. Extra left bits in OrData are stripped.
1099 If Address > 0x0FFFFFFF, then ASSERT().
1100 If Address is not aligned on a 32-bit boundary, then ASSERT().
1101 If StartBit is greater than 31, then ASSERT().
1102 If EndBit is greater than 31, then ASSERT().
1103 If EndBit is less than StartBit, then ASSERT().
1104 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1106 @param Address The PCI configuration register to write.
1107 @param StartBit The ordinal of the least significant bit in the bit field.
1109 @param EndBit The ordinal of the most significant bit in the bit field.
1111 @param OrData The value to OR with the PCI configuration register.
1113 @return The value written back to the PCI configuration register.
1127 BitFieldOr32 (PciRead32 (Address
), StartBit
, EndBit
, OrData
)
1132 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1133 AND, and writes the result back to the bit field in the 32-bit register.
1135 Reads the 32-bit PCI configuration register specified by Address, performs a
1136 bitwise AND between the read result and the value specified by AndData, and
1137 writes the result to the 32-bit PCI configuration register specified by
1138 Address. The value written to the PCI configuration register is returned.
1139 This function must guarantee that all PCI read and write operations are
1140 serialized. Extra left bits in AndData are stripped.
1142 If Address > 0x0FFFFFFF, then ASSERT().
1143 If Address is not aligned on a 32-bit boundary, then ASSERT().
1144 If StartBit is greater than 31, then ASSERT().
1145 If EndBit is greater than 31, then ASSERT().
1146 If EndBit is less than StartBit, then ASSERT().
1147 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1149 @param Address The PCI configuration register to write.
1150 @param StartBit The ordinal of the least significant bit in the bit field.
1152 @param EndBit The ordinal of the most significant bit in the bit field.
1154 @param AndData The value to AND with the PCI configuration register.
1156 @return The value written back to the PCI configuration register.
1170 BitFieldAnd32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
)
1175 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1176 bitwise OR, and writes the result back to the bit field in the
1179 Reads the 32-bit PCI configuration register specified by Address, performs a
1180 bitwise AND followed by a bitwise OR between the read result and
1181 the value specified by AndData, and writes the result to the 32-bit PCI
1182 configuration register specified by Address. The value written to the PCI
1183 configuration register is returned. This function must guarantee that all PCI
1184 read and write operations are serialized. Extra left bits in both AndData and
1185 OrData are stripped.
1187 If Address > 0x0FFFFFFF, then ASSERT().
1188 If Address is not aligned on a 32-bit boundary, then ASSERT().
1189 If StartBit is greater than 31, then ASSERT().
1190 If EndBit is greater than 31, then ASSERT().
1191 If EndBit is less than StartBit, then ASSERT().
1192 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1193 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1195 @param Address The PCI configuration register to write.
1196 @param StartBit The ordinal of the least significant bit in the bit field.
1198 @param EndBit The ordinal of the most significant bit in the bit field.
1200 @param AndData The value to AND with the PCI configuration register.
1201 @param OrData The value to OR with the result of the AND operation.
1203 @return The value written back to the PCI configuration register.
1208 PciBitFieldAndThenOr32 (
1218 BitFieldAndThenOr32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
, OrData
)
1223 Reads a range of PCI configuration registers into a caller supplied buffer.
1225 Reads the range of PCI configuration registers specified by StartAddress and
1226 Size into the buffer specified by Buffer. This function only allows the PCI
1227 configuration registers from a single PCI function to be read. Size is
1228 returned. When possible 32-bit PCI configuration read cycles are used to read
1229 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1230 and 16-bit PCI configuration read cycles may be used at the beginning and the
1233 If StartAddress > 0x0FFFFFFF, then ASSERT().
1234 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1235 If Size > 0 and Buffer is NULL, then ASSERT().
1237 @param StartAddress The starting address that encodes the PCI Bus, Device,
1238 Function and Register.
1239 @param Size The size in bytes of the transfer.
1240 @param Buffer The pointer to a buffer receiving the data read.
1248 IN UINTN StartAddress
,
1255 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1256 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1262 ASSERT (Buffer
!= NULL
);
1265 // Save Size for return
1269 if ((StartAddress
& BIT0
) != 0) {
1271 // Read a byte if StartAddress is byte aligned
1273 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1274 StartAddress
+= sizeof (UINT8
);
1275 Size
-= sizeof (UINT8
);
1276 Buffer
= (UINT8
*)Buffer
+ 1;
1279 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1281 // Read a word if StartAddress is word aligned
1283 WriteUnaligned16 (Buffer
, PciRead16 (StartAddress
));
1284 StartAddress
+= sizeof (UINT16
);
1285 Size
-= sizeof (UINT16
);
1286 Buffer
= (UINT16
*)Buffer
+ 1;
1289 while (Size
>= sizeof (UINT32
)) {
1291 // Read as many double words as possible
1293 WriteUnaligned32 (Buffer
, PciRead32 (StartAddress
));
1294 StartAddress
+= sizeof (UINT32
);
1295 Size
-= sizeof (UINT32
);
1296 Buffer
= (UINT32
*)Buffer
+ 1;
1299 if (Size
>= sizeof (UINT16
)) {
1301 // Read the last remaining word if exist
1303 WriteUnaligned16 (Buffer
, PciRead16 (StartAddress
));
1304 StartAddress
+= sizeof (UINT16
);
1305 Size
-= sizeof (UINT16
);
1306 Buffer
= (UINT16
*)Buffer
+ 1;
1309 if (Size
>= sizeof (UINT8
)) {
1311 // Read the last remaining byte if exist
1313 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1320 Copies the data in a caller supplied buffer to a specified range of PCI
1321 configuration space.
1323 Writes the range of PCI configuration registers specified by StartAddress and
1324 Size from the buffer specified by Buffer. This function only allows the PCI
1325 configuration registers from a single PCI function to be written. Size is
1326 returned. When possible 32-bit PCI configuration write cycles are used to
1327 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1328 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1329 and the end of the range.
1331 If StartAddress > 0x0FFFFFFF, then ASSERT().
1332 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1333 If Size > 0 and Buffer is NULL, then ASSERT().
1335 @param StartAddress The starting address that encodes the PCI Bus, Device,
1336 Function and Register.
1337 @param Size The size in bytes of the transfer.
1338 @param Buffer The pointer to a buffer containing the data to write.
1340 @return Size written to StartAddress.
1346 IN UINTN StartAddress
,
1353 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1354 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1360 ASSERT (Buffer
!= NULL
);
1363 // Save Size for return
1367 if ((StartAddress
& BIT0
) != 0) {
1369 // Write a byte if StartAddress is byte aligned
1371 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1372 StartAddress
+= sizeof (UINT8
);
1373 Size
-= sizeof (UINT8
);
1374 Buffer
= (UINT8
*)Buffer
+ 1;
1377 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1379 // Write a word if StartAddress is word aligned
1381 PciWrite16 (StartAddress
, ReadUnaligned16 (Buffer
));
1382 StartAddress
+= sizeof (UINT16
);
1383 Size
-= sizeof (UINT16
);
1384 Buffer
= (UINT16
*)Buffer
+ 1;
1387 while (Size
>= sizeof (UINT32
)) {
1389 // Write as many double words as possible
1391 PciWrite32 (StartAddress
, ReadUnaligned32 (Buffer
));
1392 StartAddress
+= sizeof (UINT32
);
1393 Size
-= sizeof (UINT32
);
1394 Buffer
= (UINT32
*)Buffer
+ 1;
1397 if (Size
>= sizeof (UINT16
)) {
1399 // Write the last remaining word if exist
1401 PciWrite16 (StartAddress
, ReadUnaligned16 (Buffer
));
1402 StartAddress
+= sizeof (UINT16
);
1403 Size
-= sizeof (UINT16
);
1404 Buffer
= (UINT16
*)Buffer
+ 1;
1407 if (Size
>= sizeof (UINT8
)) {
1409 // Write the last remaining byte if exist
1411 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);