2 PCI Segment Library implementation using PCI CFG2 PPI.
4 Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials are
6 licensed and made available under the terms and conditions of
7 the BSD License which accompanies this distribution. The full
8 text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php.
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #include <Ppi/PciCfg2.h>
20 #include <Library/PciSegmentLib.h>
21 #include <Library/BaseLib.h>
22 #include <Library/PeiServicesTablePointerLib.h>
23 #include <Library/DebugLib.h>
24 #include <Library/PeiServicesLib.h>
27 Assert the validity of a PCI Segment address.
28 A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63
30 @param A The address to validate.
31 @param M Additional bits to assert to be zero.
34 #define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
35 ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
38 Translate PCI Lib address into format of PCI CFG2 PPI.
40 @param A The address that encodes the PCI Bus, Device, Function and
44 #define PCI_TO_PCICFG2_ADDRESS(A) \
45 ((((UINT32)(A) << 4) & 0xff000000) | (((UINT32)(A) >> 4) & 0x00000700) | (((UINT32)(A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))
50 This internal function retrieves PCI CFG2 PPI from PPI database.
52 @param Address The address that encodes the PCI Segment, Bus, Device,
53 Function and Register.
55 @return The pointer to PCI CFG2 PPI.
58 EFI_PEI_PCI_CFG2_PPI
*
59 InternalGetPciCfg2Ppi (
65 EFI_PEI_PCI_CFG2_PPI
*PciCfg2Ppi
;
70 SegmentNumber
= BitFieldRead64 (Address
, 32, 63);
73 // Loop through all instances of the PPI and match segment number
76 Status
= PeiServicesLocatePpi(
82 ASSERT_EFI_ERROR (Status
);
84 } while (PciCfg2Ppi
->Segment
!= SegmentNumber
);
90 Internal worker function to read a PCI configuration register.
92 This function wraps EFI_PEI_PCI_CFG2_PPI.Read() service.
93 It reads and returns the PCI configuration register specified by Address,
94 the width of data is specified by Width.
96 @param Address The address that encodes the PCI Bus, Device, Function and
98 @param Width The width of data to read
100 @return The value read from the PCI configuration register.
104 PeiPciSegmentLibPciCfg2ReadWorker (
106 IN EFI_PEI_PCI_CFG_PPI_WIDTH Width
110 CONST EFI_PEI_PCI_CFG2_PPI
*PciCfg2Ppi
;
111 UINT64 PciCfg2Address
;
113 PciCfg2Ppi
= InternalGetPciCfg2Ppi (Address
);
114 PciCfg2Address
= PCI_TO_PCICFG2_ADDRESS (Address
);
116 GetPeiServicesTablePointer (),
127 Internal worker function to writes a PCI configuration register.
129 This function wraps EFI_PEI_PCI_CFG2_PPI.Write() service.
130 It writes the PCI configuration register specified by Address with the
131 value specified by Data. The width of data is specifed by Width.
134 @param Address The address that encodes the PCI Bus, Device, Function and
136 @param Width The width of data to write
137 @param Data The value to write.
139 @return The value written to the PCI configuration register.
143 PeiPciSegmentLibPciCfg2WriteWorker (
145 IN EFI_PEI_PCI_CFG_PPI_WIDTH Width
,
149 CONST EFI_PEI_PCI_CFG2_PPI
*PciCfg2Ppi
;
150 UINT64 PciCfg2Address
;
152 PciCfg2Ppi
= InternalGetPciCfg2Ppi (Address
);
153 PciCfg2Address
= PCI_TO_PCICFG2_ADDRESS (Address
);
155 GetPeiServicesTablePointer (),
166 Register a PCI device so PCI configuration registers may be accessed after
167 SetVirtualAddressMap().
169 If any reserved bits in Address are set, then ASSERT().
171 @param Address Address that encodes the PCI Bus, Device, Function and
174 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
175 @retval RETURN_UNSUPPORTED An attempt was made to call this function
176 after ExitBootServices().
177 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
178 at runtime could not be mapped.
179 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
180 complete the registration.
185 PciSegmentRegisterForRuntimeAccess (
189 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address
, 0);
190 return RETURN_UNSUPPORTED
;
194 Reads an 8-bit PCI configuration register.
196 Reads and returns the 8-bit PCI configuration register specified by Address.
197 This function must guarantee that all PCI read and write operations are serialized.
199 If any reserved bits in Address are set, then ASSERT().
201 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
203 @return The 8-bit PCI configuration register specified by Address.
212 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address
, 0);
214 return (UINT8
) PeiPciSegmentLibPciCfg2ReadWorker (Address
, EfiPeiPciCfgWidthUint8
);
218 Writes an 8-bit PCI configuration register.
220 Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
221 Value is returned. This function must guarantee that all PCI read and write operations are serialized.
223 If any reserved bits in Address are set, then ASSERT().
225 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
226 @param Value The value to write.
228 @return The value written to the PCI configuration register.
238 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address
, 0);
240 return (UINT8
) PeiPciSegmentLibPciCfg2WriteWorker (Address
, EfiPeiPciCfgWidthUint8
, Value
);
244 Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
246 Reads the 8-bit PCI configuration register specified by Address,
247 performs a bitwise OR between the read result and the value specified by OrData,
248 and writes the result to the 8-bit PCI configuration register specified by Address.
249 The value written to the PCI configuration register is returned.
250 This function must guarantee that all PCI read and write operations are serialized.
252 If any reserved bits in Address are set, then ASSERT().
254 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
255 @param OrData The value to OR with the PCI configuration register.
257 @return The value written to the PCI configuration register.
267 return PciSegmentWrite8 (Address
, (UINT8
) (PciSegmentRead8 (Address
) | OrData
));
271 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
273 Reads the 8-bit PCI configuration register specified by Address,
274 performs a bitwise AND between the read result and the value specified by AndData,
275 and writes the result to the 8-bit PCI configuration register specified by Address.
276 The value written to the PCI configuration register is returned.
277 This function must guarantee that all PCI read and write operations are serialized.
278 If any reserved bits in Address are set, then ASSERT().
280 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
281 @param AndData The value to AND with the PCI configuration register.
283 @return The value written to the PCI configuration register.
293 return PciSegmentWrite8 (Address
, (UINT8
) (PciSegmentRead8 (Address
) & AndData
));
297 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
298 followed a bitwise OR with another 8-bit value.
300 Reads the 8-bit PCI configuration register specified by Address,
301 performs a bitwise AND between the read result and the value specified by AndData,
302 performs a bitwise OR between the result of the AND operation and the value specified by OrData,
303 and writes the result to the 8-bit PCI configuration register specified by Address.
304 The value written to the PCI configuration register is returned.
305 This function must guarantee that all PCI read and write operations are serialized.
307 If any reserved bits in Address are set, then ASSERT().
309 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
310 @param AndData The value to AND with the PCI configuration register.
311 @param OrData The value to OR with the PCI configuration register.
313 @return The value written to the PCI configuration register.
318 PciSegmentAndThenOr8 (
324 return PciSegmentWrite8 (Address
, (UINT8
) ((PciSegmentRead8 (Address
) & AndData
) | OrData
));
328 Reads a bit field of a PCI configuration register.
330 Reads the bit field in an 8-bit PCI configuration register. The bit field is
331 specified by the StartBit and the EndBit. The value of the bit field is
334 If any reserved bits in Address are set, then ASSERT().
335 If StartBit is greater than 7, then ASSERT().
336 If EndBit is greater than 7, then ASSERT().
337 If EndBit is less than StartBit, then ASSERT().
339 @param Address PCI configuration register to read.
340 @param StartBit The ordinal of the least significant bit in the bit field.
342 @param EndBit The ordinal of the most significant bit in the bit field.
345 @return The value of the bit field read from the PCI configuration register.
350 PciSegmentBitFieldRead8 (
356 return BitFieldRead8 (PciSegmentRead8 (Address
), StartBit
, EndBit
);
360 Writes a bit field to a PCI configuration register.
362 Writes Value to the bit field of the PCI configuration register. The bit
363 field is specified by the StartBit and the EndBit. All other bits in the
364 destination PCI configuration register are preserved. The new value of the
365 8-bit register is returned.
367 If any reserved bits in Address are set, then ASSERT().
368 If StartBit is greater than 7, then ASSERT().
369 If EndBit is greater than 7, then ASSERT().
370 If EndBit is less than StartBit, then ASSERT().
371 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
373 @param Address PCI configuration register to write.
374 @param StartBit The ordinal of the least significant bit in the bit field.
376 @param EndBit The ordinal of the most significant bit in the bit field.
378 @param Value New value of the bit field.
380 @return The value written back to the PCI configuration register.
385 PciSegmentBitFieldWrite8 (
392 return PciSegmentWrite8 (
394 BitFieldWrite8 (PciSegmentRead8 (Address
), StartBit
, EndBit
, Value
)
399 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
400 writes the result back to the bit field in the 8-bit port.
402 Reads the 8-bit PCI configuration register specified by Address, performs a
403 bitwise OR between the read result and the value specified by
404 OrData, and writes the result to the 8-bit PCI configuration register
405 specified by Address. The value written to the PCI configuration register is
406 returned. This function must guarantee that all PCI read and write operations
407 are serialized. Extra left bits in OrData are stripped.
409 If any reserved bits in Address are set, then ASSERT().
410 If StartBit is greater than 7, then ASSERT().
411 If EndBit is greater than 7, then ASSERT().
412 If EndBit is less than StartBit, then ASSERT().
413 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
415 @param Address PCI configuration register to write.
416 @param StartBit The ordinal of the least significant bit in the bit field.
418 @param EndBit The ordinal of the most significant bit in the bit field.
420 @param OrData The value to OR with the PCI configuration register.
422 @return The value written back to the PCI configuration register.
427 PciSegmentBitFieldOr8 (
434 return PciSegmentWrite8 (
436 BitFieldOr8 (PciSegmentRead8 (Address
), StartBit
, EndBit
, OrData
)
441 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
442 AND, and writes the result back to the bit field in the 8-bit register.
444 Reads the 8-bit PCI configuration register specified by Address, performs a
445 bitwise AND between the read result and the value specified by AndData, and
446 writes the result to the 8-bit PCI configuration register specified by
447 Address. The value written to the PCI configuration register is returned.
448 This function must guarantee that all PCI read and write operations are
449 serialized. Extra left bits in AndData are stripped.
451 If any reserved bits in Address are set, then ASSERT().
452 If StartBit is greater than 7, then ASSERT().
453 If EndBit is greater than 7, then ASSERT().
454 If EndBit is less than StartBit, then ASSERT().
455 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
457 @param Address PCI configuration register to write.
458 @param StartBit The ordinal of the least significant bit in the bit field.
460 @param EndBit The ordinal of the most significant bit in the bit field.
462 @param AndData The value to AND with the PCI configuration register.
464 @return The value written back to the PCI configuration register.
469 PciSegmentBitFieldAnd8 (
476 return PciSegmentWrite8 (
478 BitFieldAnd8 (PciSegmentRead8 (Address
), StartBit
, EndBit
, AndData
)
483 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
484 bitwise OR, and writes the result back to the bit field in the 8-bit port.
486 Reads the 8-bit PCI configuration register specified by Address, performs a
487 bitwise AND followed by a bitwise OR between the read result and
488 the value specified by AndData, and writes the result to the 8-bit PCI
489 configuration register specified by Address. The value written to the PCI
490 configuration register is returned. This function must guarantee that all PCI
491 read and write operations are serialized. Extra left bits in both AndData and
494 If any reserved bits in Address are set, then ASSERT().
495 If StartBit is greater than 7, then ASSERT().
496 If EndBit is greater than 7, then ASSERT().
497 If EndBit is less than StartBit, then ASSERT().
498 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
499 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
501 @param Address PCI configuration register to write.
502 @param StartBit The ordinal of the least significant bit in the bit field.
504 @param EndBit The ordinal of the most significant bit in the bit field.
506 @param AndData The value to AND with the PCI configuration register.
507 @param OrData The value to OR with the result of the AND operation.
509 @return The value written back to the PCI configuration register.
514 PciSegmentBitFieldAndThenOr8 (
522 return PciSegmentWrite8 (
524 BitFieldAndThenOr8 (PciSegmentRead8 (Address
), StartBit
, EndBit
, AndData
, OrData
)
529 Reads a 16-bit PCI configuration register.
531 Reads and returns the 16-bit PCI configuration register specified by Address.
532 This function must guarantee that all PCI read and write operations are serialized.
534 If any reserved bits in Address are set, then ASSERT().
535 If Address is not aligned on a 16-bit boundary, then ASSERT().
537 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
539 @return The 16-bit PCI configuration register specified by Address.
548 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address
, 1);
550 return (UINT16
) PeiPciSegmentLibPciCfg2ReadWorker (Address
, EfiPeiPciCfgWidthUint16
);
554 Writes a 16-bit PCI configuration register.
556 Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
557 Value is returned. This function must guarantee that all PCI read and write operations are serialized.
559 If any reserved bits in Address are set, then ASSERT().
560 If Address is not aligned on a 16-bit boundary, then ASSERT().
562 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
563 @param Value The value to write.
565 @return The parameter of Value.
575 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address
, 1);
577 return (UINT16
) PeiPciSegmentLibPciCfg2WriteWorker (Address
, EfiPeiPciCfgWidthUint16
, Value
);
581 Performs a bitwise OR of a 16-bit PCI configuration register with
584 Reads the 16-bit PCI configuration register specified by Address, performs a
585 bitwise OR between the read result and the value specified by OrData, and
586 writes the result to the 16-bit PCI configuration register specified by Address.
587 The value written to the PCI configuration register is returned. This function
588 must guarantee that all PCI read and write operations are serialized.
590 If any reserved bits in Address are set, then ASSERT().
591 If Address is not aligned on a 16-bit boundary, then ASSERT().
593 @param Address Address that encodes the PCI Segment, Bus, Device, Function and
595 @param OrData The value to OR with the PCI configuration register.
597 @return The value written back to the PCI configuration register.
607 return PciSegmentWrite16 (Address
, (UINT16
) (PciSegmentRead16 (Address
) | OrData
));
611 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
613 Reads the 16-bit PCI configuration register specified by Address,
614 performs a bitwise AND between the read result and the value specified by AndData,
615 and writes the result to the 16-bit PCI configuration register specified by Address.
616 The value written to the PCI configuration register is returned.
617 This function must guarantee that all PCI read and write operations are serialized.
619 If any reserved bits in Address are set, then ASSERT().
620 If Address is not aligned on a 16-bit boundary, then ASSERT().
622 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
623 @param AndData The value to AND with the PCI configuration register.
625 @return The value written to the PCI configuration register.
635 return PciSegmentWrite16 (Address
, (UINT16
) (PciSegmentRead16 (Address
) & AndData
));
639 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
640 followed a bitwise OR with another 16-bit value.
642 Reads the 16-bit PCI configuration register specified by Address,
643 performs a bitwise AND between the read result and the value specified by AndData,
644 performs a bitwise OR between the result of the AND operation and the value specified by OrData,
645 and writes the result to the 16-bit PCI configuration register specified by Address.
646 The value written to the PCI configuration register is returned.
647 This function must guarantee that all PCI read and write operations are serialized.
649 If any reserved bits in Address are set, then ASSERT().
650 If Address is not aligned on a 16-bit boundary, then ASSERT().
652 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
653 @param AndData The value to AND with the PCI configuration register.
654 @param OrData The value to OR with the PCI configuration register.
656 @return The value written to the PCI configuration register.
661 PciSegmentAndThenOr16 (
667 return PciSegmentWrite16 (Address
, (UINT16
) ((PciSegmentRead16 (Address
) & AndData
) | OrData
));
671 Reads a bit field of a PCI configuration register.
673 Reads the bit field in a 16-bit PCI configuration register. The bit field is
674 specified by the StartBit and the EndBit. The value of the bit field is
677 If any reserved bits in Address are set, then ASSERT().
678 If Address is not aligned on a 16-bit boundary, then ASSERT().
679 If StartBit is greater than 15, then ASSERT().
680 If EndBit is greater than 15, then ASSERT().
681 If EndBit is less than StartBit, then ASSERT().
683 @param Address PCI configuration register to read.
684 @param StartBit The ordinal of the least significant bit in the bit field.
686 @param EndBit The ordinal of the most significant bit in the bit field.
689 @return The value of the bit field read from the PCI configuration register.
694 PciSegmentBitFieldRead16 (
700 return BitFieldRead16 (PciSegmentRead16 (Address
), StartBit
, EndBit
);
704 Writes a bit field to a PCI configuration register.
706 Writes Value to the bit field of the PCI configuration register. The bit
707 field is specified by the StartBit and the EndBit. All other bits in the
708 destination PCI configuration register are preserved. The new value of the
709 16-bit register is returned.
711 If any reserved bits in Address are set, then ASSERT().
712 If Address is not aligned on a 16-bit boundary, then ASSERT().
713 If StartBit is greater than 15, then ASSERT().
714 If EndBit is greater than 15, then ASSERT().
715 If EndBit is less than StartBit, then ASSERT().
716 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
718 @param Address PCI configuration register to write.
719 @param StartBit The ordinal of the least significant bit in the bit field.
721 @param EndBit The ordinal of the most significant bit in the bit field.
723 @param Value New value of the bit field.
725 @return The value written back to the PCI configuration register.
730 PciSegmentBitFieldWrite16 (
737 return PciSegmentWrite16 (
739 BitFieldWrite16 (PciSegmentRead16 (Address
), StartBit
, EndBit
, Value
)
744 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes
745 the result back to the bit field in the 16-bit port.
747 Reads the 16-bit PCI configuration register specified by Address, performs a
748 bitwise OR between the read result and the value specified by
749 OrData, and writes the result to the 16-bit PCI configuration register
750 specified by Address. The value written to the PCI configuration register is
751 returned. This function must guarantee that all PCI read and write operations
752 are serialized. Extra left bits in OrData are stripped.
754 If any reserved bits in Address are set, then ASSERT().
755 If Address is not aligned on a 16-bit boundary, then ASSERT().
756 If StartBit is greater than 15, then ASSERT().
757 If EndBit is greater than 15, then ASSERT().
758 If EndBit is less than StartBit, then ASSERT().
759 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
761 @param Address PCI configuration register to write.
762 @param StartBit The ordinal of the least significant bit in the bit field.
764 @param EndBit The ordinal of the most significant bit in the bit field.
766 @param OrData The value to OR with the PCI configuration register.
768 @return The value written back to the PCI configuration register.
773 PciSegmentBitFieldOr16 (
780 return PciSegmentWrite16 (
782 BitFieldOr16 (PciSegmentRead16 (Address
), StartBit
, EndBit
, OrData
)
787 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
788 AND, writes the result back to the bit field in the 16-bit register.
790 Reads the 16-bit PCI configuration register specified by Address, performs a
791 bitwise AND between the read result and the value specified by AndData, and
792 writes the result to the 16-bit PCI configuration register specified by
793 Address. The value written to the PCI configuration register is returned.
794 This function must guarantee that all PCI read and write operations are
795 serialized. Extra left bits in AndData are stripped.
797 If any reserved bits in Address are set, then ASSERT().
798 If Address is not aligned on a 16-bit boundary, then ASSERT().
799 If StartBit is greater than 15, then ASSERT().
800 If EndBit is greater than 15, then ASSERT().
801 If EndBit is less than StartBit, then ASSERT().
802 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
804 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
805 @param StartBit The ordinal of the least significant bit in the bit field.
807 @param EndBit The ordinal of the most significant bit in the bit field.
809 @param AndData The value to AND with the PCI configuration register.
811 @return The value written back to the PCI configuration register.
816 PciSegmentBitFieldAnd16 (
823 return PciSegmentWrite16 (
825 BitFieldAnd16 (PciSegmentRead16 (Address
), StartBit
, EndBit
, AndData
)
830 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
831 bitwise OR, and writes the result back to the bit field in the
834 Reads the 16-bit PCI configuration register specified by Address, performs a
835 bitwise AND followed by a bitwise OR between the read result and
836 the value specified by AndData, and writes the result to the 16-bit PCI
837 configuration register specified by Address. The value written to the PCI
838 configuration register is returned. This function must guarantee that all PCI
839 read and write operations are serialized. Extra left bits in both AndData and
842 If any reserved bits in Address are set, then ASSERT().
843 If StartBit is greater than 15, then ASSERT().
844 If EndBit is greater than 15, then ASSERT().
845 If EndBit is less than StartBit, then ASSERT().
846 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
847 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
849 @param Address PCI configuration register to write.
850 @param StartBit The ordinal of the least significant bit in the bit field.
852 @param EndBit The ordinal of the most significant bit in the bit field.
854 @param AndData The value to AND with the PCI configuration register.
855 @param OrData The value to OR with the result of the AND operation.
857 @return The value written back to the PCI configuration register.
862 PciSegmentBitFieldAndThenOr16 (
870 return PciSegmentWrite16 (
872 BitFieldAndThenOr16 (PciSegmentRead16 (Address
), StartBit
, EndBit
, AndData
, OrData
)
877 Reads a 32-bit PCI configuration register.
879 Reads and returns the 32-bit PCI configuration register specified by Address.
880 This function must guarantee that all PCI read and write operations are serialized.
882 If any reserved bits in Address are set, then ASSERT().
883 If Address is not aligned on a 32-bit boundary, then ASSERT().
885 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
887 @return The 32-bit PCI configuration register specified by Address.
896 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address
, 3);
898 return PeiPciSegmentLibPciCfg2ReadWorker (Address
, EfiPeiPciCfgWidthUint32
);
902 Writes a 32-bit PCI configuration register.
904 Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
905 Value is returned. This function must guarantee that all PCI read and write operations are serialized.
907 If any reserved bits in Address are set, then ASSERT().
908 If Address is not aligned on a 32-bit boundary, then ASSERT().
910 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
911 @param Value The value to write.
913 @return The parameter of Value.
923 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address
, 3);
925 return PeiPciSegmentLibPciCfg2WriteWorker (Address
, EfiPeiPciCfgWidthUint32
, Value
);
929 Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
931 Reads the 32-bit PCI configuration register specified by Address,
932 performs a bitwise OR between the read result and the value specified by OrData,
933 and writes the result to the 32-bit PCI configuration register specified by Address.
934 The value written to the PCI configuration register is returned.
935 This function must guarantee that all PCI read and write operations are serialized.
937 If any reserved bits in Address are set, then ASSERT().
938 If Address is not aligned on a 32-bit boundary, then ASSERT().
940 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
941 @param OrData The value to OR with the PCI configuration register.
943 @return The value written to the PCI configuration register.
953 return PciSegmentWrite32 (Address
, PciSegmentRead32 (Address
) | OrData
);
957 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
959 Reads the 32-bit PCI configuration register specified by Address,
960 performs a bitwise AND between the read result and the value specified by AndData,
961 and writes the result to the 32-bit PCI configuration register specified by Address.
962 The value written to the PCI configuration register is returned.
963 This function must guarantee that all PCI read and write operations are serialized.
965 If any reserved bits in Address are set, then ASSERT().
966 If Address is not aligned on a 32-bit boundary, then ASSERT().
968 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
969 @param AndData The value to AND with the PCI configuration register.
971 @return The value written to the PCI configuration register.
981 return PciSegmentWrite32 (Address
, PciSegmentRead32 (Address
) & AndData
);
985 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
986 followed a bitwise OR with another 32-bit value.
988 Reads the 32-bit PCI configuration register specified by Address,
989 performs a bitwise AND between the read result and the value specified by AndData,
990 performs a bitwise OR between the result of the AND operation and the value specified by OrData,
991 and writes the result to the 32-bit PCI configuration register specified by Address.
992 The value written to the PCI configuration register is returned.
993 This function must guarantee that all PCI read and write operations are serialized.
995 If any reserved bits in Address are set, then ASSERT().
996 If Address is not aligned on a 32-bit boundary, then ASSERT().
998 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
999 @param AndData The value to AND with the PCI configuration register.
1000 @param OrData The value to OR with the PCI configuration register.
1002 @return The value written to the PCI configuration register.
1007 PciSegmentAndThenOr32 (
1013 return PciSegmentWrite32 (Address
, (PciSegmentRead32 (Address
) & AndData
) | OrData
);
1017 Reads a bit field of a PCI configuration register.
1019 Reads the bit field in a 32-bit PCI configuration register. The bit field is
1020 specified by the StartBit and the EndBit. The value of the bit field is
1023 If any reserved bits in Address are set, then ASSERT().
1024 If Address is not aligned on a 32-bit boundary, then ASSERT().
1025 If StartBit is greater than 31, then ASSERT().
1026 If EndBit is greater than 31, then ASSERT().
1027 If EndBit is less than StartBit, then ASSERT().
1029 @param Address PCI configuration register to read.
1030 @param StartBit The ordinal of the least significant bit in the bit field.
1032 @param EndBit The ordinal of the most significant bit in the bit field.
1035 @return The value of the bit field read from the PCI configuration register.
1040 PciSegmentBitFieldRead32 (
1046 return BitFieldRead32 (PciSegmentRead32 (Address
), StartBit
, EndBit
);
1050 Writes a bit field to a PCI configuration register.
1052 Writes Value to the bit field of the PCI configuration register. The bit
1053 field is specified by the StartBit and the EndBit. All other bits in the
1054 destination PCI configuration register are preserved. The new value of the
1055 32-bit register is returned.
1057 If any reserved bits in Address are set, then ASSERT().
1058 If Address is not aligned on a 32-bit boundary, then ASSERT().
1059 If StartBit is greater than 31, then ASSERT().
1060 If EndBit is greater than 31, then ASSERT().
1061 If EndBit is less than StartBit, then ASSERT().
1062 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1064 @param Address PCI configuration register to write.
1065 @param StartBit The ordinal of the least significant bit in the bit field.
1067 @param EndBit The ordinal of the most significant bit in the bit field.
1069 @param Value New value of the bit field.
1071 @return The value written back to the PCI configuration register.
1076 PciSegmentBitFieldWrite32 (
1083 return PciSegmentWrite32 (
1085 BitFieldWrite32 (PciSegmentRead32 (Address
), StartBit
, EndBit
, Value
)
1090 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1091 writes the result back to the bit field in the 32-bit port.
1093 Reads the 32-bit PCI configuration register specified by Address, performs a
1094 bitwise OR between the read result and the value specified by
1095 OrData, and writes the result to the 32-bit PCI configuration register
1096 specified by Address. The value written to the PCI configuration register is
1097 returned. This function must guarantee that all PCI read and write operations
1098 are serialized. Extra left bits in OrData are stripped.
1100 If any reserved bits in Address are set, then ASSERT().
1101 If StartBit is greater than 31, then ASSERT().
1102 If EndBit is greater than 31, then ASSERT().
1103 If EndBit is less than StartBit, then ASSERT().
1104 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1106 @param Address PCI configuration register to write.
1107 @param StartBit The ordinal of the least significant bit in the bit field.
1109 @param EndBit The ordinal of the most significant bit in the bit field.
1111 @param OrData The value to OR with the PCI configuration register.
1113 @return The value written back to the PCI configuration register.
1118 PciSegmentBitFieldOr32 (
1125 return PciSegmentWrite32 (
1127 BitFieldOr32 (PciSegmentRead32 (Address
), StartBit
, EndBit
, OrData
)
1132 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1133 AND, and writes the result back to the bit field in the 32-bit register.
1136 Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
1137 AND between the read result and the value specified by AndData, and writes the result
1138 to the 32-bit PCI configuration register specified by Address. The value written to
1139 the PCI configuration register is returned. This function must guarantee that all PCI
1140 read and write operations are serialized. Extra left bits in AndData are stripped.
1141 If any reserved bits in Address are set, then ASSERT().
1142 If Address is not aligned on a 32-bit boundary, then ASSERT().
1143 If StartBit is greater than 31, then ASSERT().
1144 If EndBit is greater than 31, then ASSERT().
1145 If EndBit is less than StartBit, then ASSERT().
1146 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1148 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
1149 @param StartBit The ordinal of the least significant bit in the bit field.
1151 @param EndBit The ordinal of the most significant bit in the bit field.
1153 @param AndData The value to AND with the PCI configuration register.
1155 @return The value written back to the PCI configuration register.
1160 PciSegmentBitFieldAnd32 (
1167 return PciSegmentWrite32 (
1169 BitFieldAnd32 (PciSegmentRead32 (Address
), StartBit
, EndBit
, AndData
)
1174 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1175 bitwise OR, and writes the result back to the bit field in the
1178 Reads the 32-bit PCI configuration register specified by Address, performs a
1179 bitwise AND followed by a bitwise OR between the read result and
1180 the value specified by AndData, and writes the result to the 32-bit PCI
1181 configuration register specified by Address. The value written to the PCI
1182 configuration register is returned. This function must guarantee that all PCI
1183 read and write operations are serialized. Extra left bits in both AndData and
1184 OrData are stripped.
1186 If any reserved bits in Address are set, then ASSERT().
1187 If StartBit is greater than 31, then ASSERT().
1188 If EndBit is greater than 31, then ASSERT().
1189 If EndBit is less than StartBit, then ASSERT().
1190 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1191 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1193 @param Address PCI configuration register to write.
1194 @param StartBit The ordinal of the least significant bit in the bit field.
1196 @param EndBit The ordinal of the most significant bit in the bit field.
1198 @param AndData The value to AND with the PCI configuration register.
1199 @param OrData The value to OR with the result of the AND operation.
1201 @return The value written back to the PCI configuration register.
1206 PciSegmentBitFieldAndThenOr32 (
1214 return PciSegmentWrite32 (
1216 BitFieldAndThenOr32 (PciSegmentRead32 (Address
), StartBit
, EndBit
, AndData
, OrData
)
1221 Reads a range of PCI configuration registers into a caller supplied buffer.
1223 Reads the range of PCI configuration registers specified by StartAddress and
1224 Size into the buffer specified by Buffer. This function only allows the PCI
1225 configuration registers from a single PCI function to be read. Size is
1226 returned. When possible 32-bit PCI configuration read cycles are used to read
1227 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1228 and 16-bit PCI configuration read cycles may be used at the beginning and the
1231 If any reserved bits in StartAddress are set, then ASSERT().
1232 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1233 If Size > 0 and Buffer is NULL, then ASSERT().
1235 @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
1236 Function and Register.
1237 @param Size Size in bytes of the transfer.
1238 @param Buffer Pointer to a buffer receiving the data read.
1245 PciSegmentReadBuffer (
1246 IN UINT64 StartAddress
,
1253 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress
, 0);
1254 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1260 ASSERT (Buffer
!= NULL
);
1263 // Save Size for return
1267 if ((StartAddress
& BIT0
) != 0) {
1269 // Read a byte if StartAddress is byte aligned
1271 *(volatile UINT8
*)Buffer
= PciSegmentRead8 (StartAddress
);
1272 StartAddress
+= sizeof (UINT8
);
1273 Size
-= sizeof (UINT8
);
1274 Buffer
= (UINT8
*)Buffer
+ 1;
1277 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1279 // Read a word if StartAddress is word aligned
1281 WriteUnaligned16 (Buffer
, PciSegmentRead16 (StartAddress
));
1282 StartAddress
+= sizeof (UINT16
);
1283 Size
-= sizeof (UINT16
);
1284 Buffer
= (UINT16
*)Buffer
+ 1;
1287 while (Size
>= sizeof (UINT32
)) {
1289 // Read as many double words as possible
1291 WriteUnaligned32 (Buffer
, PciSegmentRead32 (StartAddress
));
1292 StartAddress
+= sizeof (UINT32
);
1293 Size
-= sizeof (UINT32
);
1294 Buffer
= (UINT32
*)Buffer
+ 1;
1297 if (Size
>= sizeof (UINT16
)) {
1299 // Read the last remaining word if exist
1301 WriteUnaligned16 (Buffer
, PciSegmentRead16 (StartAddress
));
1302 StartAddress
+= sizeof (UINT16
);
1303 Size
-= sizeof (UINT16
);
1304 Buffer
= (UINT16
*)Buffer
+ 1;
1307 if (Size
>= sizeof (UINT8
)) {
1309 // Read the last remaining byte if exist
1311 *(volatile UINT8
*)Buffer
= PciSegmentRead8 (StartAddress
);
1319 Copies the data in a caller supplied buffer to a specified range of PCI
1320 configuration space.
1322 Writes the range of PCI configuration registers specified by StartAddress and
1323 Size from the buffer specified by Buffer. This function only allows the PCI
1324 configuration registers from a single PCI function to be written. Size is
1325 returned. When possible 32-bit PCI configuration write cycles are used to
1326 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1327 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1328 and the end of the range.
1330 If any reserved bits in StartAddress are set, then ASSERT().
1331 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1332 If Size > 0 and Buffer is NULL, then ASSERT().
1334 @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
1335 Function and Register.
1336 @param Size Size in bytes of the transfer.
1337 @param Buffer Pointer to a buffer containing the data to write.
1339 @return The parameter of Size.
1344 PciSegmentWriteBuffer (
1345 IN UINT64 StartAddress
,
1352 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress
, 0);
1353 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1359 ASSERT (Buffer
!= NULL
);
1362 // Save Size for return
1366 if ((StartAddress
& BIT0
) != 0) {
1368 // Write a byte if StartAddress is byte aligned
1370 PciSegmentWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1371 StartAddress
+= sizeof (UINT8
);
1372 Size
-= sizeof (UINT8
);
1373 Buffer
= (UINT8
*)Buffer
+ 1;
1376 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1378 // Write a word if StartAddress is word aligned
1380 PciSegmentWrite16 (StartAddress
, ReadUnaligned16 (Buffer
));
1381 StartAddress
+= sizeof (UINT16
);
1382 Size
-= sizeof (UINT16
);
1383 Buffer
= (UINT16
*)Buffer
+ 1;
1386 while (Size
>= sizeof (UINT32
)) {
1388 // Write as many double words as possible
1390 PciSegmentWrite32 (StartAddress
, ReadUnaligned32 (Buffer
));
1391 StartAddress
+= sizeof (UINT32
);
1392 Size
-= sizeof (UINT32
);
1393 Buffer
= (UINT32
*)Buffer
+ 1;
1396 if (Size
>= sizeof (UINT16
)) {
1398 // Write the last remaining word if exist
1400 PciSegmentWrite16 (StartAddress
, ReadUnaligned16 (Buffer
));
1401 StartAddress
+= sizeof (UINT16
);
1402 Size
-= sizeof (UINT16
);
1403 Buffer
= (UINT16
*)Buffer
+ 1;
1406 if (Size
>= sizeof (UINT8
)) {
1408 // Write the last remaining byte if exist
1410 PciSegmentWrite8 (StartAddress
, *(UINT8
*)Buffer
);