2 Functions in this library instance make use of MMIO functions in IoLib to
3 access memory mapped PCI configuration space.
5 All assertions for I/O operations are handled in MMIO functions in the IoLib
8 Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.
9 Portions copyright (c) 2016, American Megatrends, Inc. All rights reserved.
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php.
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
22 #include <Library/BaseLib.h>
23 #include <Library/PciExpressLib.h>
24 #include <Library/IoLib.h>
25 #include <Library/DebugLib.h>
26 #include <Library/PcdLib.h>
29 /// Module global that contains the base physical address of the PCI Express MMIO range.
31 UINTN mSmmPciExpressLibPciExpressBaseAddress
= 0;
34 The constructor function caches the PCI Express Base Address
36 @param ImageHandle The firmware allocated handle for the EFI image.
37 @param SystemTable A pointer to the EFI System Table.
39 @retval EFI_SUCCESS The constructor completed successfully.
43 SmmPciExpressLibConstructor (
44 IN EFI_HANDLE ImageHandle
,
45 IN EFI_SYSTEM_TABLE
*SystemTable
49 // Cache the physical address of the PCI Express MMIO range into a module global variable
51 mSmmPciExpressLibPciExpressBaseAddress
= (UINTN
) PcdGet64 (PcdPciExpressBaseAddress
);
57 Assert the validity of a PCI address. A valid PCI address should contain 1's
58 only in the low 28 bits.
60 @param A The address to validate.
63 #define ASSERT_INVALID_PCI_ADDRESS(A) \
64 ASSERT (((A) & ~0xfffffff) == 0)
67 Registers a PCI device so PCI configuration registers may be accessed after
68 SetVirtualAddressMap().
70 Registers the PCI device specified by Address so all the PCI configuration
71 registers associated with that PCI device may be accessed after SetVirtualAddressMap()
74 If Address > 0x0FFFFFFF, then ASSERT().
76 @param Address The address that encodes the PCI Bus, Device, Function and
79 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
80 @retval RETURN_UNSUPPORTED An attempt was made to call this function
81 after ExitBootServices().
82 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
83 at runtime could not be mapped.
84 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
85 complete the registration.
90 PciExpressRegisterForRuntimeAccess (
94 ASSERT_INVALID_PCI_ADDRESS (Address
);
95 return RETURN_UNSUPPORTED
;
99 Gets MMIO address that can be used to access PCI Express location defined by Address.
101 This internal functions converts PCI Express address to a CPU MMIO address by adding
102 PCI Express Base Address stored in a global variable mSmmPciExpressLibPciExpressBaseAddress.
103 mSmmPciExpressLibPciExpressBaseAddress is initialized in the library constructor from PCD entry
104 PcdPciExpressBaseAddress.
106 @param Address The address that encodes the PCI Bus, Device, Function and Register.
107 @return MMIO address corresponding to Address.
111 GetPciExpressAddress (
116 // Make sure Address is valid
118 ASSERT_INVALID_PCI_ADDRESS (Address
);
119 return mSmmPciExpressLibPciExpressBaseAddress
+ Address
;
123 Reads an 8-bit PCI configuration register.
125 Reads and returns the 8-bit PCI configuration register specified by Address.
126 This function must guarantee that all PCI read and write operations are
129 If Address > 0x0FFFFFFF, then ASSERT().
131 @param Address The address that encodes the PCI Bus, Device, Function and
134 @return The read value from the PCI configuration register.
143 return MmioRead8 (GetPciExpressAddress (Address
));
147 Writes an 8-bit PCI configuration register.
149 Writes the 8-bit PCI configuration register specified by Address with the
150 value specified by Value. Value is returned. This function must guarantee
151 that all PCI read and write operations are serialized.
153 If Address > 0x0FFFFFFF, then ASSERT().
155 @param Address The address that encodes the PCI Bus, Device, Function and
157 @param Value The value to write.
159 @return The value written to the PCI configuration register.
169 return MmioWrite8 (GetPciExpressAddress (Address
), Value
);
173 Performs a bitwise OR of an 8-bit PCI configuration register with
176 Reads the 8-bit PCI configuration register specified by Address, performs a
177 bitwise OR between the read result and the value specified by
178 OrData, and writes the result to the 8-bit PCI configuration register
179 specified by Address. The value written to the PCI configuration register is
180 returned. This function must guarantee that all PCI read and write operations
183 If Address > 0x0FFFFFFF, then ASSERT().
185 @param Address The address that encodes the PCI Bus, Device, Function and
187 @param OrData The value to OR with the PCI configuration register.
189 @return The value written back to the PCI configuration register.
199 return MmioOr8 (GetPciExpressAddress (Address
), OrData
);
203 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
206 Reads the 8-bit PCI configuration register specified by Address, performs a
207 bitwise AND between the read result and the value specified by AndData, and
208 writes the result to the 8-bit PCI configuration register specified by
209 Address. The value written to the PCI configuration register is returned.
210 This function must guarantee that all PCI read and write operations are
213 If Address > 0x0FFFFFFF, then ASSERT().
215 @param Address The address that encodes the PCI Bus, Device, Function and
217 @param AndData The value to AND with the PCI configuration register.
219 @return The value written back to the PCI configuration register.
229 return MmioAnd8 (GetPciExpressAddress (Address
), AndData
);
233 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
234 value, followed a bitwise OR with another 8-bit value.
236 Reads the 8-bit PCI configuration register specified by Address, performs a
237 bitwise AND between the read result and the value specified by AndData,
238 performs a bitwise OR between the result of the AND operation and
239 the value specified by OrData, and writes the result to the 8-bit PCI
240 configuration register specified by Address. The value written to the PCI
241 configuration register is returned. This function must guarantee that all PCI
242 read and write operations are serialized.
244 If Address > 0x0FFFFFFF, then ASSERT().
246 @param Address The address that encodes the PCI Bus, Device, Function and
248 @param AndData The value to AND with the PCI configuration register.
249 @param OrData The value to OR with the result of the AND operation.
251 @return The value written back to the PCI configuration register.
256 PciExpressAndThenOr8 (
262 return MmioAndThenOr8 (
263 GetPciExpressAddress (Address
),
270 Reads a bit field of a PCI configuration register.
272 Reads the bit field in an 8-bit PCI configuration register. The bit field is
273 specified by the StartBit and the EndBit. The value of the bit field is
276 If Address > 0x0FFFFFFF, then ASSERT().
277 If StartBit is greater than 7, then ASSERT().
278 If EndBit is greater than 7, then ASSERT().
279 If EndBit is less than StartBit, then ASSERT().
281 @param Address The PCI configuration register to read.
282 @param StartBit The ordinal of the least significant bit in the bit field.
284 @param EndBit The ordinal of the most significant bit in the bit field.
287 @return The value of the bit field read from the PCI configuration register.
292 PciExpressBitFieldRead8 (
298 return MmioBitFieldRead8 (
299 GetPciExpressAddress (Address
),
306 Writes a bit field to a PCI configuration register.
308 Writes Value to the bit field of the PCI configuration register. The bit
309 field is specified by the StartBit and the EndBit. All other bits in the
310 destination PCI configuration register are preserved. The new value of the
311 8-bit register is returned.
313 If Address > 0x0FFFFFFF, then ASSERT().
314 If StartBit is greater than 7, then ASSERT().
315 If EndBit is greater than 7, then ASSERT().
316 If EndBit is less than StartBit, then ASSERT().
317 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
319 @param Address The PCI configuration register to write.
320 @param StartBit The ordinal of the least significant bit in the bit field.
322 @param EndBit The ordinal of the most significant bit in the bit field.
324 @param Value The new value of the bit field.
326 @return The value written back to the PCI configuration register.
331 PciExpressBitFieldWrite8 (
338 return MmioBitFieldWrite8 (
339 GetPciExpressAddress (Address
),
347 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
348 writes the result back to the bit field in the 8-bit port.
350 Reads the 8-bit PCI configuration register specified by Address, performs a
351 bitwise OR between the read result and the value specified by
352 OrData, and writes the result to the 8-bit PCI configuration register
353 specified by Address. The value written to the PCI configuration register is
354 returned. This function must guarantee that all PCI read and write operations
355 are serialized. Extra left bits in OrData are stripped.
357 If Address > 0x0FFFFFFF, then ASSERT().
358 If StartBit is greater than 7, then ASSERT().
359 If EndBit is greater than 7, then ASSERT().
360 If EndBit is less than StartBit, then ASSERT().
361 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
363 @param Address The PCI configuration register to write.
364 @param StartBit The ordinal of the least significant bit in the bit field.
366 @param EndBit The ordinal of the most significant bit in the bit field.
368 @param OrData The value to OR with the PCI configuration register.
370 @return The value written back to the PCI configuration register.
375 PciExpressBitFieldOr8 (
382 return MmioBitFieldOr8 (
383 GetPciExpressAddress (Address
),
391 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
392 AND, and writes the result back to the bit field in the 8-bit register.
394 Reads the 8-bit PCI configuration register specified by Address, performs a
395 bitwise AND between the read result and the value specified by AndData, and
396 writes the result to the 8-bit PCI configuration register specified by
397 Address. The value written to the PCI configuration register is returned.
398 This function must guarantee that all PCI read and write operations are
399 serialized. Extra left bits in AndData are stripped.
401 If Address > 0x0FFFFFFF, then ASSERT().
402 If StartBit is greater than 7, then ASSERT().
403 If EndBit is greater than 7, then ASSERT().
404 If EndBit is less than StartBit, then ASSERT().
405 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
407 @param Address The PCI configuration register to write.
408 @param StartBit The ordinal of the least significant bit in the bit field.
410 @param EndBit The ordinal of the most significant bit in the bit field.
412 @param AndData The value to AND with the PCI configuration register.
414 @return The value written back to the PCI configuration register.
419 PciExpressBitFieldAnd8 (
426 return MmioBitFieldAnd8 (
427 GetPciExpressAddress (Address
),
435 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
436 bitwise OR, and writes the result back to the bit field in the
439 Reads the 8-bit PCI configuration register specified by Address, performs a
440 bitwise AND followed by a bitwise OR between the read result and
441 the value specified by AndData, and writes the result to the 8-bit PCI
442 configuration register specified by Address. The value written to the PCI
443 configuration register is returned. This function must guarantee that all PCI
444 read and write operations are serialized. Extra left bits in both AndData and
447 If Address > 0x0FFFFFFF, then ASSERT().
448 If StartBit is greater than 7, then ASSERT().
449 If EndBit is greater than 7, then ASSERT().
450 If EndBit is less than StartBit, then ASSERT().
451 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
452 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
454 @param Address The PCI configuration register to write.
455 @param StartBit The ordinal of the least significant bit in the bit field.
457 @param EndBit The ordinal of the most significant bit in the bit field.
459 @param AndData The value to AND with the PCI configuration register.
460 @param OrData The value to OR with the result of the AND operation.
462 @return The value written back to the PCI configuration register.
467 PciExpressBitFieldAndThenOr8 (
475 return MmioBitFieldAndThenOr8 (
476 GetPciExpressAddress (Address
),
485 Reads a 16-bit PCI configuration register.
487 Reads and returns the 16-bit PCI configuration register specified by Address.
488 This function must guarantee that all PCI read and write operations are
491 If Address > 0x0FFFFFFF, then ASSERT().
492 If Address is not aligned on a 16-bit boundary, then ASSERT().
494 @param Address The address that encodes the PCI Bus, Device, Function and
497 @return The read value from the PCI configuration register.
506 return MmioRead16 (GetPciExpressAddress (Address
));
510 Writes a 16-bit PCI configuration register.
512 Writes the 16-bit PCI configuration register specified by Address with the
513 value specified by Value. Value is returned. This function must guarantee
514 that all PCI read and write operations are serialized.
516 If Address > 0x0FFFFFFF, then ASSERT().
517 If Address is not aligned on a 16-bit boundary, then ASSERT().
519 @param Address The address that encodes the PCI Bus, Device, Function and
521 @param Value The value to write.
523 @return The value written to the PCI configuration register.
533 return MmioWrite16 (GetPciExpressAddress (Address
), Value
);
537 Performs a bitwise OR of a 16-bit PCI configuration register with
540 Reads the 16-bit PCI configuration register specified by Address, performs a
541 bitwise OR between the read result and the value specified by
542 OrData, and writes the result to the 16-bit PCI configuration register
543 specified by Address. The value written to the PCI configuration register is
544 returned. This function must guarantee that all PCI read and write operations
547 If Address > 0x0FFFFFFF, then ASSERT().
548 If Address is not aligned on a 16-bit boundary, then ASSERT().
550 @param Address The address that encodes the PCI Bus, Device, Function and
552 @param OrData The value to OR with the PCI configuration register.
554 @return The value written back to the PCI configuration register.
564 return MmioOr16 (GetPciExpressAddress (Address
), OrData
);
568 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
571 Reads the 16-bit PCI configuration register specified by Address, performs a
572 bitwise AND between the read result and the value specified by AndData, and
573 writes the result to the 16-bit PCI configuration register specified by
574 Address. The value written to the PCI configuration register is returned.
575 This function must guarantee that all PCI read and write operations are
578 If Address > 0x0FFFFFFF, then ASSERT().
579 If Address is not aligned on a 16-bit boundary, then ASSERT().
581 @param Address The address that encodes the PCI Bus, Device, Function and
583 @param AndData The value to AND with the PCI configuration register.
585 @return The value written back to the PCI configuration register.
595 return MmioAnd16 (GetPciExpressAddress (Address
), AndData
);
599 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
600 value, followed a bitwise OR with another 16-bit value.
602 Reads the 16-bit PCI configuration register specified by Address, performs a
603 bitwise AND between the read result and the value specified by AndData,
604 performs a bitwise OR between the result of the AND operation and
605 the value specified by OrData, and writes the result to the 16-bit PCI
606 configuration register specified by Address. The value written to the PCI
607 configuration register is returned. This function must guarantee that all PCI
608 read and write operations are serialized.
610 If Address > 0x0FFFFFFF, then ASSERT().
611 If Address is not aligned on a 16-bit boundary, then ASSERT().
613 @param Address The address that encodes the PCI Bus, Device, Function and
615 @param AndData The value to AND with the PCI configuration register.
616 @param OrData The value to OR with the result of the AND operation.
618 @return The value written back to the PCI configuration register.
623 PciExpressAndThenOr16 (
629 return MmioAndThenOr16 (
630 GetPciExpressAddress (Address
),
637 Reads a bit field of a PCI configuration register.
639 Reads the bit field in a 16-bit PCI configuration register. The bit field is
640 specified by the StartBit and the EndBit. The value of the bit field is
643 If Address > 0x0FFFFFFF, then ASSERT().
644 If Address is not aligned on a 16-bit boundary, then ASSERT().
645 If StartBit is greater than 15, then ASSERT().
646 If EndBit is greater than 15, then ASSERT().
647 If EndBit is less than StartBit, then ASSERT().
649 @param Address The PCI configuration register to read.
650 @param StartBit The ordinal of the least significant bit in the bit field.
652 @param EndBit The ordinal of the most significant bit in the bit field.
655 @return The value of the bit field read from the PCI configuration register.
660 PciExpressBitFieldRead16 (
666 return MmioBitFieldRead16 (
667 GetPciExpressAddress (Address
),
674 Writes a bit field to a PCI configuration register.
676 Writes Value to the bit field of the PCI configuration register. The bit
677 field is specified by the StartBit and the EndBit. All other bits in the
678 destination PCI configuration register are preserved. The new value of the
679 16-bit register is returned.
681 If Address > 0x0FFFFFFF, then ASSERT().
682 If Address is not aligned on a 16-bit boundary, then ASSERT().
683 If StartBit is greater than 15, then ASSERT().
684 If EndBit is greater than 15, then ASSERT().
685 If EndBit is less than StartBit, then ASSERT().
686 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
688 @param Address The PCI configuration register to write.
689 @param StartBit The ordinal of the least significant bit in the bit field.
691 @param EndBit The ordinal of the most significant bit in the bit field.
693 @param Value The new value of the bit field.
695 @return The value written back to the PCI configuration register.
700 PciExpressBitFieldWrite16 (
707 return MmioBitFieldWrite16 (
708 GetPciExpressAddress (Address
),
716 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
717 writes the result back to the bit field in the 16-bit port.
719 Reads the 16-bit PCI configuration register specified by Address, performs a
720 bitwise OR between the read result and the value specified by
721 OrData, and writes the result to the 16-bit PCI configuration register
722 specified by Address. The value written to the PCI configuration register is
723 returned. This function must guarantee that all PCI read and write operations
724 are serialized. Extra left bits in OrData are stripped.
726 If Address > 0x0FFFFFFF, then ASSERT().
727 If Address is not aligned on a 16-bit boundary, then ASSERT().
728 If StartBit is greater than 15, then ASSERT().
729 If EndBit is greater than 15, then ASSERT().
730 If EndBit is less than StartBit, then ASSERT().
731 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
733 @param Address The PCI configuration register to write.
734 @param StartBit The ordinal of the least significant bit in the bit field.
736 @param EndBit The ordinal of the most significant bit in the bit field.
738 @param OrData The value to OR with the PCI configuration register.
740 @return The value written back to the PCI configuration register.
745 PciExpressBitFieldOr16 (
752 return MmioBitFieldOr16 (
753 GetPciExpressAddress (Address
),
761 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
762 AND, and writes the result back to the bit field in the 16-bit register.
764 Reads the 16-bit PCI configuration register specified by Address, performs a
765 bitwise AND between the read result and the value specified by AndData, and
766 writes the result to the 16-bit PCI configuration register specified by
767 Address. The value written to the PCI configuration register is returned.
768 This function must guarantee that all PCI read and write operations are
769 serialized. Extra left bits in AndData are stripped.
771 If Address > 0x0FFFFFFF, then ASSERT().
772 If Address is not aligned on a 16-bit boundary, then ASSERT().
773 If StartBit is greater than 15, then ASSERT().
774 If EndBit is greater than 15, then ASSERT().
775 If EndBit is less than StartBit, then ASSERT().
776 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
778 @param Address The PCI configuration register to write.
779 @param StartBit The ordinal of the least significant bit in the bit field.
781 @param EndBit The ordinal of the most significant bit in the bit field.
783 @param AndData The value to AND with the PCI configuration register.
785 @return The value written back to the PCI configuration register.
790 PciExpressBitFieldAnd16 (
797 return MmioBitFieldAnd16 (
798 GetPciExpressAddress (Address
),
806 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
807 bitwise OR, and writes the result back to the bit field in the
810 Reads the 16-bit PCI configuration register specified by Address, performs a
811 bitwise AND followed by a bitwise OR between the read result and
812 the value specified by AndData, and writes the result to the 16-bit PCI
813 configuration register specified by Address. The value written to the PCI
814 configuration register is returned. This function must guarantee that all PCI
815 read and write operations are serialized. Extra left bits in both AndData and
818 If Address > 0x0FFFFFFF, then ASSERT().
819 If Address is not aligned on a 16-bit boundary, then ASSERT().
820 If StartBit is greater than 15, then ASSERT().
821 If EndBit is greater than 15, then ASSERT().
822 If EndBit is less than StartBit, then ASSERT().
823 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
824 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
826 @param Address The PCI configuration register to write.
827 @param StartBit The ordinal of the least significant bit in the bit field.
829 @param EndBit The ordinal of the most significant bit in the bit field.
831 @param AndData The value to AND with the PCI configuration register.
832 @param OrData The value to OR with the result of the AND operation.
834 @return The value written back to the PCI configuration register.
839 PciExpressBitFieldAndThenOr16 (
847 return MmioBitFieldAndThenOr16 (
848 GetPciExpressAddress (Address
),
857 Reads a 32-bit PCI configuration register.
859 Reads and returns the 32-bit PCI configuration register specified by Address.
860 This function must guarantee that all PCI read and write operations are
863 If Address > 0x0FFFFFFF, then ASSERT().
864 If Address is not aligned on a 32-bit boundary, then ASSERT().
866 @param Address The address that encodes the PCI Bus, Device, Function and
869 @return The read value from the PCI configuration register.
878 return MmioRead32 (GetPciExpressAddress (Address
));
882 Writes a 32-bit PCI configuration register.
884 Writes the 32-bit PCI configuration register specified by Address with the
885 value specified by Value. Value is returned. This function must guarantee
886 that all PCI read and write operations are serialized.
888 If Address > 0x0FFFFFFF, then ASSERT().
889 If Address is not aligned on a 32-bit boundary, then ASSERT().
891 @param Address The address that encodes the PCI Bus, Device, Function and
893 @param Value The value to write.
895 @return The value written to the PCI configuration register.
905 return MmioWrite32 (GetPciExpressAddress (Address
), Value
);
909 Performs a bitwise OR of a 32-bit PCI configuration register with
912 Reads the 32-bit PCI configuration register specified by Address, performs a
913 bitwise OR between the read result and the value specified by
914 OrData, and writes the result to the 32-bit PCI configuration register
915 specified by Address. The value written to the PCI configuration register is
916 returned. This function must guarantee that all PCI read and write operations
919 If Address > 0x0FFFFFFF, then ASSERT().
920 If Address is not aligned on a 32-bit boundary, then ASSERT().
922 @param Address The address that encodes the PCI Bus, Device, Function and
924 @param OrData The value to OR with the PCI configuration register.
926 @return The value written back to the PCI configuration register.
936 return MmioOr32 (GetPciExpressAddress (Address
), OrData
);
940 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
943 Reads the 32-bit PCI configuration register specified by Address, performs a
944 bitwise AND between the read result and the value specified by AndData, and
945 writes the result to the 32-bit PCI configuration register specified by
946 Address. The value written to the PCI configuration register is returned.
947 This function must guarantee that all PCI read and write operations are
950 If Address > 0x0FFFFFFF, then ASSERT().
951 If Address is not aligned on a 32-bit boundary, then ASSERT().
953 @param Address The address that encodes the PCI Bus, Device, Function and
955 @param AndData The value to AND with the PCI configuration register.
957 @return The value written back to the PCI configuration register.
967 return MmioAnd32 (GetPciExpressAddress (Address
), AndData
);
971 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
972 value, followed a bitwise OR with another 32-bit value.
974 Reads the 32-bit PCI configuration register specified by Address, performs a
975 bitwise AND between the read result and the value specified by AndData,
976 performs a bitwise OR between the result of the AND operation and
977 the value specified by OrData, and writes the result to the 32-bit PCI
978 configuration register specified by Address. The value written to the PCI
979 configuration register is returned. This function must guarantee that all PCI
980 read and write operations are serialized.
982 If Address > 0x0FFFFFFF, then ASSERT().
983 If Address is not aligned on a 32-bit boundary, then ASSERT().
985 @param Address The address that encodes the PCI Bus, Device, Function and
987 @param AndData The value to AND with the PCI configuration register.
988 @param OrData The value to OR with the result of the AND operation.
990 @return The value written back to the PCI configuration register.
995 PciExpressAndThenOr32 (
1001 return MmioAndThenOr32 (
1002 GetPciExpressAddress (Address
),
1009 Reads a bit field of a PCI configuration register.
1011 Reads the bit field in a 32-bit PCI configuration register. The bit field is
1012 specified by the StartBit and the EndBit. The value of the bit field is
1015 If Address > 0x0FFFFFFF, then ASSERT().
1016 If Address is not aligned on a 32-bit boundary, then ASSERT().
1017 If StartBit is greater than 31, then ASSERT().
1018 If EndBit is greater than 31, then ASSERT().
1019 If EndBit is less than StartBit, then ASSERT().
1021 @param Address The PCI configuration register to read.
1022 @param StartBit The ordinal of the least significant bit in the bit field.
1024 @param EndBit The ordinal of the most significant bit in the bit field.
1027 @return The value of the bit field read from the PCI configuration register.
1032 PciExpressBitFieldRead32 (
1038 return MmioBitFieldRead32 (
1039 GetPciExpressAddress (Address
),
1046 Writes a bit field to a PCI configuration register.
1048 Writes Value to the bit field of the PCI configuration register. The bit
1049 field is specified by the StartBit and the EndBit. All other bits in the
1050 destination PCI configuration register are preserved. The new value of the
1051 32-bit register is returned.
1053 If Address > 0x0FFFFFFF, then ASSERT().
1054 If Address is not aligned on a 32-bit boundary, then ASSERT().
1055 If StartBit is greater than 31, then ASSERT().
1056 If EndBit is greater than 31, then ASSERT().
1057 If EndBit is less than StartBit, then ASSERT().
1058 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1060 @param Address The PCI configuration register to write.
1061 @param StartBit The ordinal of the least significant bit in the bit field.
1063 @param EndBit The ordinal of the most significant bit in the bit field.
1065 @param Value The new value of the bit field.
1067 @return The value written back to the PCI configuration register.
1072 PciExpressBitFieldWrite32 (
1079 return MmioBitFieldWrite32 (
1080 GetPciExpressAddress (Address
),
1088 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1089 writes the result back to the bit field in the 32-bit port.
1091 Reads the 32-bit PCI configuration register specified by Address, performs a
1092 bitwise OR between the read result and the value specified by
1093 OrData, and writes the result to the 32-bit PCI configuration register
1094 specified by Address. The value written to the PCI configuration register is
1095 returned. This function must guarantee that all PCI read and write operations
1096 are serialized. Extra left bits in OrData are stripped.
1098 If Address > 0x0FFFFFFF, then ASSERT().
1099 If Address is not aligned on a 32-bit boundary, then ASSERT().
1100 If StartBit is greater than 31, then ASSERT().
1101 If EndBit is greater than 31, then ASSERT().
1102 If EndBit is less than StartBit, then ASSERT().
1103 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1105 @param Address The PCI configuration register to write.
1106 @param StartBit The ordinal of the least significant bit in the bit field.
1108 @param EndBit The ordinal of the most significant bit in the bit field.
1110 @param OrData The value to OR with the PCI configuration register.
1112 @return The value written back to the PCI configuration register.
1117 PciExpressBitFieldOr32 (
1124 return MmioBitFieldOr32 (
1125 GetPciExpressAddress (Address
),
1133 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1134 AND, and writes the result back to the bit field in the 32-bit register.
1136 Reads the 32-bit PCI configuration register specified by Address, performs a
1137 bitwise AND between the read result and the value specified by AndData, and
1138 writes the result to the 32-bit PCI configuration register specified by
1139 Address. The value written to the PCI configuration register is returned.
1140 This function must guarantee that all PCI read and write operations are
1141 serialized. Extra left bits in AndData are stripped.
1143 If Address > 0x0FFFFFFF, then ASSERT().
1144 If Address is not aligned on a 32-bit boundary, then ASSERT().
1145 If StartBit is greater than 31, then ASSERT().
1146 If EndBit is greater than 31, then ASSERT().
1147 If EndBit is less than StartBit, then ASSERT().
1148 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1150 @param Address The PCI configuration register to write.
1151 @param StartBit The ordinal of the least significant bit in the bit field.
1153 @param EndBit The ordinal of the most significant bit in the bit field.
1155 @param AndData The value to AND with the PCI configuration register.
1157 @return The value written back to the PCI configuration register.
1162 PciExpressBitFieldAnd32 (
1169 return MmioBitFieldAnd32 (
1170 GetPciExpressAddress (Address
),
1178 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1179 bitwise OR, and writes the result back to the bit field in the
1182 Reads the 32-bit PCI configuration register specified by Address, performs a
1183 bitwise AND followed by a bitwise OR between the read result and
1184 the value specified by AndData, and writes the result to the 32-bit PCI
1185 configuration register specified by Address. The value written to the PCI
1186 configuration register is returned. This function must guarantee that all PCI
1187 read and write operations are serialized. Extra left bits in both AndData and
1188 OrData are stripped.
1190 If Address > 0x0FFFFFFF, then ASSERT().
1191 If Address is not aligned on a 32-bit boundary, then ASSERT().
1192 If StartBit is greater than 31, then ASSERT().
1193 If EndBit is greater than 31, then ASSERT().
1194 If EndBit is less than StartBit, then ASSERT().
1195 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1196 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1198 @param Address The PCI configuration register to write.
1199 @param StartBit The ordinal of the least significant bit in the bit field.
1201 @param EndBit The ordinal of the most significant bit in the bit field.
1203 @param AndData The value to AND with the PCI configuration register.
1204 @param OrData The value to OR with the result of the AND operation.
1206 @return The value written back to the PCI configuration register.
1211 PciExpressBitFieldAndThenOr32 (
1219 return MmioBitFieldAndThenOr32 (
1220 GetPciExpressAddress (Address
),
1229 Reads a range of PCI configuration registers into a caller supplied buffer.
1231 Reads the range of PCI configuration registers specified by StartAddress and
1232 Size into the buffer specified by Buffer. This function only allows the PCI
1233 configuration registers from a single PCI function to be read. Size is
1234 returned. When possible 32-bit PCI configuration read cycles are used to read
1235 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1236 and 16-bit PCI configuration read cycles may be used at the beginning and the
1239 If StartAddress > 0x0FFFFFFF, then ASSERT().
1240 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1241 If Size > 0 and Buffer is NULL, then ASSERT().
1243 @param StartAddress The starting address that encodes the PCI Bus, Device,
1244 Function and Register.
1245 @param Size The size in bytes of the transfer.
1246 @param Buffer The pointer to a buffer receiving the data read.
1248 @return Size read data from StartAddress.
1253 PciExpressReadBuffer (
1254 IN UINTN StartAddress
,
1262 // Make sure Address is valid
1264 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1265 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1271 ASSERT (Buffer
!= NULL
);
1274 // Save Size for return
1278 if ((StartAddress
& 1) != 0) {
1280 // Read a byte if StartAddress is byte aligned
1282 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1283 StartAddress
+= sizeof (UINT8
);
1284 Size
-= sizeof (UINT8
);
1285 Buffer
= (UINT8
*)Buffer
+ 1;
1288 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1290 // Read a word if StartAddress is word aligned
1292 WriteUnaligned16 ((UINT16
*) Buffer
, (UINT16
) PciExpressRead16 (StartAddress
));
1294 StartAddress
+= sizeof (UINT16
);
1295 Size
-= sizeof (UINT16
);
1296 Buffer
= (UINT16
*)Buffer
+ 1;
1299 while (Size
>= sizeof (UINT32
)) {
1301 // Read as many double words as possible
1303 WriteUnaligned32 ((UINT32
*) Buffer
, (UINT32
) PciExpressRead32 (StartAddress
));
1305 StartAddress
+= sizeof (UINT32
);
1306 Size
-= sizeof (UINT32
);
1307 Buffer
= (UINT32
*)Buffer
+ 1;
1310 if (Size
>= sizeof (UINT16
)) {
1312 // Read the last remaining word if exist
1314 WriteUnaligned16 ((UINT16
*) Buffer
, (UINT16
) PciExpressRead16 (StartAddress
));
1315 StartAddress
+= sizeof (UINT16
);
1316 Size
-= sizeof (UINT16
);
1317 Buffer
= (UINT16
*)Buffer
+ 1;
1320 if (Size
>= sizeof (UINT8
)) {
1322 // Read the last remaining byte if exist
1324 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1331 Copies the data in a caller supplied buffer to a specified range of PCI
1332 configuration space.
1334 Writes the range of PCI configuration registers specified by StartAddress and
1335 Size from the buffer specified by Buffer. This function only allows the PCI
1336 configuration registers from a single PCI function to be written. Size is
1337 returned. When possible 32-bit PCI configuration write cycles are used to
1338 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1339 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1340 and the end of the range.
1342 If StartAddress > 0x0FFFFFFF, then ASSERT().
1343 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1344 If Size > 0 and Buffer is NULL, then ASSERT().
1346 @param StartAddress The starting address that encodes the PCI Bus, Device,
1347 Function and Register.
1348 @param Size The size in bytes of the transfer.
1349 @param Buffer The pointer to a buffer containing the data to write.
1351 @return Size written to StartAddress.
1356 PciExpressWriteBuffer (
1357 IN UINTN StartAddress
,
1365 // Make sure Address is valid
1367 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1368 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1375 ASSERT (Buffer
!= NULL
);
1378 // Save Size for return
1382 if ((StartAddress
& 1) != 0) {
1384 // Write a byte if StartAddress is byte aligned
1386 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1387 StartAddress
+= sizeof (UINT8
);
1388 Size
-= sizeof (UINT8
);
1389 Buffer
= (UINT8
*)Buffer
+ 1;
1392 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1394 // Write a word if StartAddress is word aligned
1396 PciExpressWrite16 (StartAddress
, ReadUnaligned16 ((UINT16
*)Buffer
));
1397 StartAddress
+= sizeof (UINT16
);
1398 Size
-= sizeof (UINT16
);
1399 Buffer
= (UINT16
*)Buffer
+ 1;
1402 while (Size
>= sizeof (UINT32
)) {
1404 // Write as many double words as possible
1406 PciExpressWrite32 (StartAddress
, ReadUnaligned32 ((UINT32
*)Buffer
));
1407 StartAddress
+= sizeof (UINT32
);
1408 Size
-= sizeof (UINT32
);
1409 Buffer
= (UINT32
*)Buffer
+ 1;
1412 if (Size
>= sizeof (UINT16
)) {
1414 // Write the last remaining word if exist
1416 PciExpressWrite16 (StartAddress
, ReadUnaligned16 ((UINT16
*)Buffer
));
1417 StartAddress
+= sizeof (UINT16
);
1418 Size
-= sizeof (UINT16
);
1419 Buffer
= (UINT16
*)Buffer
+ 1;
1422 if (Size
>= sizeof (UINT8
)) {
1424 // Write the last remaining byte if exist
1426 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);