2 PCI Library using PCI Root Bridge I/O Protocol.
4 Copyright (c) 2007 - 2009, Intel Corporation All rights
5 reserved. This program and the accompanying materials are
6 licensed and made available under the terms and conditions of
7 the BSD License which accompanies this distribution. The full
8 text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #include <Protocol/PciRootBridgeIo.h>
20 #include <Library/PciLib.h>
21 #include <Library/BaseLib.h>
22 #include <Library/UefiBootServicesTableLib.h>
23 #include <Library/DebugLib.h>
26 Assert the validity of a PCI address. A valid PCI address should contain 1's
27 only in the low 28 bits.
29 @param A The address to validate.
30 @param M Additional bits to assert to be zero.
33 #define ASSERT_INVALID_PCI_ADDRESS(A,M) \
34 ASSERT (((A) & (~0xfffffff | (M))) == 0)
37 Translate PCI Lib address into format of PCI Root Bridge I/O Protocol.
39 @param A Address that encodes the PCI Bus, Device, Function and
43 #define PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS(A) \
44 ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))
47 // Global varible to cache pointer to PCI Root Bridge I/O protocol.
49 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*mPciRootBridgeIo
= NULL
;
52 The constructor function caches the pointer to PCI Root Bridge I/O protocol.
54 The constructor function locates PCI Root Bridge I/O protocol from protocol database.
55 It will ASSERT() if that operation fails and it will always return EFI_SUCCESS.
57 @param ImageHandle The firmware allocated handle for the EFI image.
58 @param SystemTable A pointer to the EFI System Table.
60 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
66 IN EFI_HANDLE ImageHandle
,
67 IN EFI_SYSTEM_TABLE
*SystemTable
72 Status
= gBS
->LocateProtocol (&gEfiPciRootBridgeIoProtocolGuid
, NULL
, (VOID
**) &mPciRootBridgeIo
);
73 ASSERT_EFI_ERROR (Status
);
74 ASSERT (mPciRootBridgeIo
!= NULL
);
80 Internal worker function to read a PCI configuration register.
82 This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Read() service.
83 It reads and returns the PCI configuration register specified by Address,
84 the width of data is specified by Width.
86 @param Address Address that encodes the PCI Bus, Device, Function and
88 @param Width Width of data to read
90 @return The value read from the PCI configuration register.
94 DxePciLibPciRootBridgeIoReadWorker (
96 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
101 mPciRootBridgeIo
->Pci
.Read (
104 PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address
),
113 Internal worker function to writes a PCI configuration register.
115 This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Write() service.
116 It writes the PCI configuration register specified by Address with the
117 value specified by Data. The width of data is specifed by Width.
120 @param Address Address that encodes the PCI Bus, Device, Function and
122 @param Width Width of data to write
123 @param Data The value to write.
125 @return The value written to the PCI configuration register.
129 DxePciLibPciRootBridgeIoWriteWorker (
131 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
135 mPciRootBridgeIo
->Pci
.Write (
138 PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address
),
146 Registers a PCI device so PCI configuration registers may be accessed after
147 SetVirtualAddressMap().
149 Registers the PCI device specified by Address so all the PCI configuration registers
150 associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
152 If Address > 0x0FFFFFFF, then ASSERT().
154 @param Address Address that encodes the PCI Bus, Device, Function and
157 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
158 @retval RETURN_UNSUPPORTED An attempt was made to call this function
159 after ExitBootServices().
160 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
161 at runtime could not be mapped.
162 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
163 complete the registration.
168 PciRegisterForRuntimeAccess (
172 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
173 return RETURN_UNSUPPORTED
;
177 Reads an 8-bit PCI configuration register.
179 Reads and returns the 8-bit PCI configuration register specified by Address.
180 This function must guarantee that all PCI read and write operations are
183 If Address > 0x0FFFFFFF, then ASSERT().
185 @param Address Address that encodes the PCI Bus, Device, Function and
188 @return The read value from the PCI configuration register.
197 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
199 return (UINT8
) DxePciLibPciRootBridgeIoReadWorker (Address
, EfiPciWidthUint8
);
203 Writes an 8-bit PCI configuration register.
205 Writes the 8-bit PCI configuration register specified by Address with the
206 value specified by Value. Value is returned. This function must guarantee
207 that all PCI read and write operations are serialized.
209 If Address > 0x0FFFFFFF, then ASSERT().
211 @param Address Address that encodes the PCI Bus, Device, Function and
213 @param Value The value to write.
215 @return The value written to the PCI configuration register.
225 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
227 return (UINT8
) DxePciLibPciRootBridgeIoWriteWorker (Address
, EfiPciWidthUint8
, Value
);
231 Performs a bitwise OR of an 8-bit PCI configuration register with
234 Reads the 8-bit PCI configuration register specified by Address, performs a
235 bitwise OR between the read result and the value specified by
236 OrData, and writes the result to the 8-bit PCI configuration register
237 specified by Address. The value written to the PCI configuration register is
238 returned. This function must guarantee that all PCI read and write operations
241 If Address > 0x0FFFFFFF, then ASSERT().
243 @param Address Address that encodes the PCI Bus, Device, Function and
245 @param OrData The value to OR with the PCI configuration register.
247 @return The value written back to the PCI configuration register.
257 return PciWrite8 (Address
, (UINT8
) (PciRead8 (Address
) | OrData
));
261 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
264 Reads the 8-bit PCI configuration register specified by Address, performs a
265 bitwise AND between the read result and the value specified by AndData, and
266 writes the result to the 8-bit PCI configuration register specified by
267 Address. The value written to the PCI configuration register is returned.
268 This function must guarantee that all PCI read and write operations are
271 If Address > 0x0FFFFFFF, then ASSERT().
273 @param Address Address that encodes the PCI Bus, Device, Function and
275 @param AndData The value to AND with the PCI configuration register.
277 @return The value written back to the PCI configuration register.
287 return PciWrite8 (Address
, (UINT8
) (PciRead8 (Address
) & AndData
));
291 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
292 value, followed a bitwise OR with another 8-bit value.
294 Reads the 8-bit PCI configuration register specified by Address, performs a
295 bitwise AND between the read result and the value specified by AndData,
296 performs a bitwise OR between the result of the AND operation and
297 the value specified by OrData, and writes the result to the 8-bit PCI
298 configuration register specified by Address. The value written to the PCI
299 configuration register is returned. This function must guarantee that all PCI
300 read and write operations are serialized.
302 If Address > 0x0FFFFFFF, then ASSERT().
304 @param Address Address that encodes the PCI Bus, Device, Function and
306 @param AndData The value to AND with the PCI configuration register.
307 @param OrData The value to OR with the result of the AND operation.
309 @return The value written back to the PCI configuration register.
320 return PciWrite8 (Address
, (UINT8
) ((PciRead8 (Address
) & AndData
) | OrData
));
324 Reads a bit field of a PCI configuration register.
326 Reads the bit field in an 8-bit PCI configuration register. The bit field is
327 specified by the StartBit and the EndBit. The value of the bit field is
330 If Address > 0x0FFFFFFF, then ASSERT().
331 If StartBit is greater than 7, then ASSERT().
332 If EndBit is greater than 7, then ASSERT().
333 If EndBit is less than StartBit, then ASSERT().
335 @param Address PCI configuration register to read.
336 @param StartBit The ordinal of the least significant bit in the bit field.
338 @param EndBit The ordinal of the most significant bit in the bit field.
341 @return The value of the bit field read from the PCI configuration register.
352 return BitFieldRead8 (PciRead8 (Address
), StartBit
, EndBit
);
356 Writes a bit field to a PCI configuration register.
358 Writes Value to the bit field of the PCI configuration register. The bit
359 field is specified by the StartBit and the EndBit. All other bits in the
360 destination PCI configuration register are preserved. The new value of the
361 8-bit register is returned.
363 If Address > 0x0FFFFFFF, then ASSERT().
364 If StartBit is greater than 7, then ASSERT().
365 If EndBit is greater than 7, then ASSERT().
366 If EndBit is less than StartBit, then ASSERT().
368 @param Address PCI configuration register to write.
369 @param StartBit The ordinal of the least significant bit in the bit field.
371 @param EndBit The ordinal of the most significant bit in the bit field.
373 @param Value New value of the bit field.
375 @return The value written back to the PCI configuration register.
389 BitFieldWrite8 (PciRead8 (Address
), StartBit
, EndBit
, Value
)
394 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
395 writes the result back to the bit field in the 8-bit port.
397 Reads the 8-bit PCI configuration register specified by Address, performs a
398 bitwise OR between the read result and the value specified by
399 OrData, and writes the result to the 8-bit PCI configuration register
400 specified by Address. The value written to the PCI configuration register is
401 returned. This function must guarantee that all PCI read and write operations
402 are serialized. Extra left bits in OrData are stripped.
404 If Address > 0x0FFFFFFF, then ASSERT().
405 If StartBit is greater than 7, then ASSERT().
406 If EndBit is greater than 7, then ASSERT().
407 If EndBit is less than StartBit, then ASSERT().
409 @param Address PCI configuration register to write.
410 @param StartBit The ordinal of the least significant bit in the bit field.
412 @param EndBit The ordinal of the most significant bit in the bit field.
414 @param OrData The value to OR with the PCI configuration register.
416 @return The value written back to the PCI configuration register.
430 BitFieldOr8 (PciRead8 (Address
), StartBit
, EndBit
, OrData
)
435 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
436 AND, and writes the result back to the bit field in the 8-bit register.
438 Reads the 8-bit PCI configuration register specified by Address, performs a
439 bitwise AND between the read result and the value specified by AndData, and
440 writes the result to the 8-bit PCI configuration register specified by
441 Address. The value written to the PCI configuration register is returned.
442 This function must guarantee that all PCI read and write operations are
443 serialized. Extra left bits in AndData are stripped.
445 If Address > 0x0FFFFFFF, then ASSERT().
446 If StartBit is greater than 7, then ASSERT().
447 If EndBit is greater than 7, then ASSERT().
448 If EndBit is less than StartBit, then ASSERT().
450 @param Address PCI configuration register to write.
451 @param StartBit The ordinal of the least significant bit in the bit field.
453 @param EndBit The ordinal of the most significant bit in the bit field.
455 @param AndData The value to AND with the PCI configuration register.
457 @return The value written back to the PCI configuration register.
471 BitFieldAnd8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
)
476 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
477 bitwise OR, and writes the result back to the bit field in the
480 Reads the 8-bit PCI configuration register specified by Address, performs a
481 bitwise AND followed by a bitwise OR between the read result and
482 the value specified by AndData, and writes the result to the 8-bit PCI
483 configuration register specified by Address. The value written to the PCI
484 configuration register is returned. This function must guarantee that all PCI
485 read and write operations are serialized. Extra left bits in both AndData and
488 If Address > 0x0FFFFFFF, then ASSERT().
489 If StartBit is greater than 7, then ASSERT().
490 If EndBit is greater than 7, then ASSERT().
491 If EndBit is less than StartBit, then ASSERT().
493 @param Address PCI configuration register to write.
494 @param StartBit The ordinal of the least significant bit in the bit field.
496 @param EndBit The ordinal of the most significant bit in the bit field.
498 @param AndData The value to AND with the PCI configuration register.
499 @param OrData The value to OR with the result of the AND operation.
501 @return The value written back to the PCI configuration register.
506 PciBitFieldAndThenOr8 (
516 BitFieldAndThenOr8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
, OrData
)
521 Reads a 16-bit PCI configuration register.
523 Reads and returns the 16-bit PCI configuration register specified by Address.
524 This function must guarantee that all PCI read and write operations are
527 If Address > 0x0FFFFFFF, then ASSERT().
528 If Address is not aligned on a 16-bit boundary, then ASSERT().
530 @param Address Address that encodes the PCI Bus, Device, Function and
533 @return The read value from the PCI configuration register.
542 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
544 return (UINT16
) DxePciLibPciRootBridgeIoReadWorker (Address
, EfiPciWidthUint16
);
548 Writes a 16-bit PCI configuration register.
550 Writes the 16-bit PCI configuration register specified by Address with the
551 value specified by Value. Value is returned. This function must guarantee
552 that all PCI read and write operations are serialized.
554 If Address > 0x0FFFFFFF, then ASSERT().
555 If Address is not aligned on a 16-bit boundary, then ASSERT().
557 @param Address Address that encodes the PCI Bus, Device, Function and
559 @param Value The value to write.
561 @return The value written to the PCI configuration register.
571 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
573 return (UINT16
) DxePciLibPciRootBridgeIoWriteWorker (Address
, EfiPciWidthUint16
, Value
);
577 Performs a bitwise OR of a 16-bit PCI configuration register with
580 Reads the 16-bit PCI configuration register specified by Address, performs a
581 bitwise OR between the read result and the value specified by
582 OrData, and writes the result to the 16-bit PCI configuration register
583 specified by Address. The value written to the PCI configuration register is
584 returned. This function must guarantee that all PCI read and write operations
587 If Address > 0x0FFFFFFF, then ASSERT().
588 If Address is not aligned on a 16-bit boundary, then ASSERT().
590 @param Address Address that encodes the PCI Bus, Device, Function and
592 @param OrData The value to OR with the PCI configuration register.
594 @return The value written back to the PCI configuration register.
604 return PciWrite16 (Address
, (UINT16
) (PciRead16 (Address
) | OrData
));
608 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
611 Reads the 16-bit PCI configuration register specified by Address, performs a
612 bitwise AND between the read result and the value specified by AndData, and
613 writes the result to the 16-bit PCI configuration register specified by
614 Address. The value written to the PCI configuration register is returned.
615 This function must guarantee that all PCI read and write operations are
618 If Address > 0x0FFFFFFF, then ASSERT().
619 If Address is not aligned on a 16-bit boundary, then ASSERT().
621 @param Address Address that encodes the PCI Bus, Device, Function and
623 @param AndData The value to AND with the PCI configuration register.
625 @return The value written back to the PCI configuration register.
635 return PciWrite16 (Address
, (UINT16
) (PciRead16 (Address
) & AndData
));
639 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
640 value, followed a bitwise OR with another 16-bit value.
642 Reads the 16-bit PCI configuration register specified by Address, performs a
643 bitwise AND between the read result and the value specified by AndData,
644 performs a bitwise OR between the result of the AND operation and
645 the value specified by OrData, and writes the result to the 16-bit PCI
646 configuration register specified by Address. The value written to the PCI
647 configuration register is returned. This function must guarantee that all PCI
648 read and write operations are serialized.
650 If Address > 0x0FFFFFFF, then ASSERT().
651 If Address is not aligned on a 16-bit boundary, then ASSERT().
653 @param Address Address that encodes the PCI Bus, Device, Function and
655 @param AndData The value to AND with the PCI configuration register.
656 @param OrData The value to OR with the result of the AND operation.
658 @return The value written back to the PCI configuration register.
669 return PciWrite16 (Address
, (UINT16
) ((PciRead16 (Address
) & AndData
) | OrData
));
673 Reads a bit field of a PCI configuration register.
675 Reads the bit field in a 16-bit PCI configuration register. The bit field is
676 specified by the StartBit and the EndBit. The value of the bit field is
679 If Address > 0x0FFFFFFF, then ASSERT().
680 If Address is not aligned on a 16-bit boundary, then ASSERT().
681 If StartBit is greater than 15, then ASSERT().
682 If EndBit is greater than 15, then ASSERT().
683 If EndBit is less than StartBit, then ASSERT().
685 @param Address PCI configuration register to read.
686 @param StartBit The ordinal of the least significant bit in the bit field.
688 @param EndBit The ordinal of the most significant bit in the bit field.
691 @return The value of the bit field read from the PCI configuration register.
702 return BitFieldRead16 (PciRead16 (Address
), StartBit
, EndBit
);
706 Writes a bit field to a PCI configuration register.
708 Writes Value to the bit field of the PCI configuration register. The bit
709 field is specified by the StartBit and the EndBit. All other bits in the
710 destination PCI configuration register are preserved. The new value of the
711 16-bit register is returned.
713 If Address > 0x0FFFFFFF, then ASSERT().
714 If Address is not aligned on a 16-bit boundary, then ASSERT().
715 If StartBit is greater than 15, then ASSERT().
716 If EndBit is greater than 15, then ASSERT().
717 If EndBit is less than StartBit, then ASSERT().
719 @param Address PCI configuration register to write.
720 @param StartBit The ordinal of the least significant bit in the bit field.
722 @param EndBit The ordinal of the most significant bit in the bit field.
724 @param Value New value of the bit field.
726 @return The value written back to the PCI configuration register.
740 BitFieldWrite16 (PciRead16 (Address
), StartBit
, EndBit
, Value
)
745 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
746 writes the result back to the bit field in the 16-bit port.
748 Reads the 16-bit PCI configuration register specified by Address, performs a
749 bitwise OR between the read result and the value specified by
750 OrData, and writes the result to the 16-bit PCI configuration register
751 specified by Address. The value written to the PCI configuration register is
752 returned. This function must guarantee that all PCI read and write operations
753 are serialized. Extra left bits in OrData are stripped.
755 If Address > 0x0FFFFFFF, then ASSERT().
756 If Address is not aligned on a 16-bit boundary, then ASSERT().
757 If StartBit is greater than 15, then ASSERT().
758 If EndBit is greater than 15, then ASSERT().
759 If EndBit is less than StartBit, then ASSERT().
761 @param Address PCI configuration register to write.
762 @param StartBit The ordinal of the least significant bit in the bit field.
764 @param EndBit The ordinal of the most significant bit in the bit field.
766 @param OrData The value to OR with the PCI configuration register.
768 @return The value written back to the PCI configuration register.
782 BitFieldOr16 (PciRead16 (Address
), StartBit
, EndBit
, OrData
)
787 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
788 AND, and writes the result back to the bit field in the 16-bit register.
790 Reads the 16-bit PCI configuration register specified by Address, performs a
791 bitwise AND between the read result and the value specified by AndData, and
792 writes the result to the 16-bit PCI configuration register specified by
793 Address. The value written to the PCI configuration register is returned.
794 This function must guarantee that all PCI read and write operations are
795 serialized. Extra left bits in AndData are stripped.
797 If Address > 0x0FFFFFFF, then ASSERT().
798 If Address is not aligned on a 16-bit boundary, then ASSERT().
799 If StartBit is greater than 15, then ASSERT().
800 If EndBit is greater than 15, then ASSERT().
801 If EndBit is less than StartBit, then ASSERT().
803 @param Address PCI configuration register to write.
804 @param StartBit The ordinal of the least significant bit in the bit field.
806 @param EndBit The ordinal of the most significant bit in the bit field.
808 @param AndData The value to AND with the PCI configuration register.
810 @return The value written back to the PCI configuration register.
824 BitFieldAnd16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
)
829 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
830 bitwise OR, and writes the result back to the bit field in the
833 Reads the 16-bit PCI configuration register specified by Address, performs a
834 bitwise AND followed by a bitwise OR between the read result and
835 the value specified by AndData, and writes the result to the 16-bit PCI
836 configuration register specified by Address. The value written to the PCI
837 configuration register is returned. This function must guarantee that all PCI
838 read and write operations are serialized. Extra left bits in both AndData and
841 If Address > 0x0FFFFFFF, then ASSERT().
842 If Address is not aligned on a 16-bit boundary, then ASSERT().
843 If StartBit is greater than 15, then ASSERT().
844 If EndBit is greater than 15, then ASSERT().
845 If EndBit is less than StartBit, then ASSERT().
847 @param Address PCI configuration register to write.
848 @param StartBit The ordinal of the least significant bit in the bit field.
850 @param EndBit The ordinal of the most significant bit in the bit field.
852 @param AndData The value to AND with the PCI configuration register.
853 @param OrData The value to OR with the result of the AND operation.
855 @return The value written back to the PCI configuration register.
860 PciBitFieldAndThenOr16 (
870 BitFieldAndThenOr16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
, OrData
)
875 Reads a 32-bit PCI configuration register.
877 Reads and returns the 32-bit PCI configuration register specified by Address.
878 This function must guarantee that all PCI read and write operations are
881 If Address > 0x0FFFFFFF, then ASSERT().
882 If Address is not aligned on a 32-bit boundary, then ASSERT().
884 @param Address Address that encodes the PCI Bus, Device, Function and
887 @return The read value from the PCI configuration register.
896 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
898 return DxePciLibPciRootBridgeIoReadWorker (Address
, EfiPciWidthUint32
);
902 Writes a 32-bit PCI configuration register.
904 Writes the 32-bit PCI configuration register specified by Address with the
905 value specified by Value. Value is returned. This function must guarantee
906 that all PCI read and write operations are serialized.
908 If Address > 0x0FFFFFFF, then ASSERT().
909 If Address is not aligned on a 32-bit boundary, then ASSERT().
911 @param Address Address that encodes the PCI Bus, Device, Function and
913 @param Value The value to write.
915 @return The value written to the PCI configuration register.
925 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
927 return DxePciLibPciRootBridgeIoWriteWorker (Address
, EfiPciWidthUint32
, Value
);
931 Performs a bitwise OR of a 32-bit PCI configuration register with
934 Reads the 32-bit PCI configuration register specified by Address, performs a
935 bitwise OR between the read result and the value specified by
936 OrData, and writes the result to the 32-bit PCI configuration register
937 specified by Address. The value written to the PCI configuration register is
938 returned. This function must guarantee that all PCI read and write operations
941 If Address > 0x0FFFFFFF, then ASSERT().
942 If Address is not aligned on a 32-bit boundary, then ASSERT().
944 @param Address Address that encodes the PCI Bus, Device, Function and
946 @param OrData The value to OR with the PCI configuration register.
948 @return The value written back to the PCI configuration register.
958 return PciWrite32 (Address
, PciRead32 (Address
) | OrData
);
962 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
965 Reads the 32-bit PCI configuration register specified by Address, performs a
966 bitwise AND between the read result and the value specified by AndData, and
967 writes the result to the 32-bit PCI configuration register specified by
968 Address. The value written to the PCI configuration register is returned.
969 This function must guarantee that all PCI read and write operations are
972 If Address > 0x0FFFFFFF, then ASSERT().
973 If Address is not aligned on a 32-bit boundary, then ASSERT().
975 @param Address Address that encodes the PCI Bus, Device, Function and
977 @param AndData The value to AND with the PCI configuration register.
979 @return The value written back to the PCI configuration register.
989 return PciWrite32 (Address
, PciRead32 (Address
) & AndData
);
993 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
994 value, followed a bitwise OR with another 32-bit value.
996 Reads the 32-bit PCI configuration register specified by Address, performs a
997 bitwise AND between the read result and the value specified by AndData,
998 performs a bitwise OR between the result of the AND operation and
999 the value specified by OrData, and writes the result to the 32-bit PCI
1000 configuration register specified by Address. The value written to the PCI
1001 configuration register is returned. This function must guarantee that all PCI
1002 read and write operations are serialized.
1004 If Address > 0x0FFFFFFF, then ASSERT().
1005 If Address is not aligned on a 32-bit boundary, then ASSERT().
1007 @param Address Address that encodes the PCI Bus, Device, Function and
1009 @param AndData The value to AND with the PCI configuration register.
1010 @param OrData The value to OR with the result of the AND operation.
1012 @return The value written back to the PCI configuration register.
1023 return PciWrite32 (Address
, (PciRead32 (Address
) & AndData
) | OrData
);
1027 Reads a bit field of a PCI configuration register.
1029 Reads the bit field in a 32-bit PCI configuration register. The bit field is
1030 specified by the StartBit and the EndBit. The value of the bit field is
1033 If Address > 0x0FFFFFFF, then ASSERT().
1034 If Address is not aligned on a 32-bit boundary, then ASSERT().
1035 If StartBit is greater than 31, then ASSERT().
1036 If EndBit is greater than 31, then ASSERT().
1037 If EndBit is less than StartBit, then ASSERT().
1039 @param Address PCI configuration register to read.
1040 @param StartBit The ordinal of the least significant bit in the bit field.
1042 @param EndBit The ordinal of the most significant bit in the bit field.
1045 @return The value of the bit field read from the PCI configuration register.
1056 return BitFieldRead32 (PciRead32 (Address
), StartBit
, EndBit
);
1060 Writes a bit field to a PCI configuration register.
1062 Writes Value to the bit field of the PCI configuration register. The bit
1063 field is specified by the StartBit and the EndBit. All other bits in the
1064 destination PCI configuration register are preserved. The new value of the
1065 32-bit register is returned.
1067 If Address > 0x0FFFFFFF, then ASSERT().
1068 If Address is not aligned on a 32-bit boundary, then ASSERT().
1069 If StartBit is greater than 31, then ASSERT().
1070 If EndBit is greater than 31, then ASSERT().
1071 If EndBit is less than StartBit, then ASSERT().
1073 @param Address PCI configuration register to write.
1074 @param StartBit The ordinal of the least significant bit in the bit field.
1076 @param EndBit The ordinal of the most significant bit in the bit field.
1078 @param Value New value of the bit field.
1080 @return The value written back to the PCI configuration register.
1085 PciBitFieldWrite32 (
1094 BitFieldWrite32 (PciRead32 (Address
), StartBit
, EndBit
, Value
)
1099 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1100 writes the result back to the bit field in the 32-bit port.
1102 Reads the 32-bit PCI configuration register specified by Address, performs a
1103 bitwise OR between the read result and the value specified by
1104 OrData, and writes the result to the 32-bit PCI configuration register
1105 specified by Address. The value written to the PCI configuration register is
1106 returned. This function must guarantee that all PCI read and write operations
1107 are serialized. Extra left bits in OrData are stripped.
1109 If Address > 0x0FFFFFFF, then ASSERT().
1110 If Address is not aligned on a 32-bit boundary, then ASSERT().
1111 If StartBit is greater than 31, then ASSERT().
1112 If EndBit is greater than 31, then ASSERT().
1113 If EndBit is less than StartBit, then ASSERT().
1115 @param Address PCI configuration register to write.
1116 @param StartBit The ordinal of the least significant bit in the bit field.
1118 @param EndBit The ordinal of the most significant bit in the bit field.
1120 @param OrData The value to OR with the PCI configuration register.
1122 @return The value written back to the PCI configuration register.
1136 BitFieldOr32 (PciRead32 (Address
), StartBit
, EndBit
, OrData
)
1141 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1142 AND, and writes the result back to the bit field in the 32-bit register.
1144 Reads the 32-bit PCI configuration register specified by Address, performs a
1145 bitwise AND between the read result and the value specified by AndData, and
1146 writes the result to the 32-bit PCI configuration register specified by
1147 Address. The value written to the PCI configuration register is returned.
1148 This function must guarantee that all PCI read and write operations are
1149 serialized. Extra left bits in AndData are stripped.
1151 If Address > 0x0FFFFFFF, then ASSERT().
1152 If Address is not aligned on a 32-bit boundary, then ASSERT().
1153 If StartBit is greater than 31, then ASSERT().
1154 If EndBit is greater than 31, then ASSERT().
1155 If EndBit is less than StartBit, then ASSERT().
1157 @param Address PCI configuration register to write.
1158 @param StartBit The ordinal of the least significant bit in the bit field.
1160 @param EndBit The ordinal of the most significant bit in the bit field.
1162 @param AndData The value to AND with the PCI configuration register.
1164 @return The value written back to the PCI configuration register.
1178 BitFieldAnd32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
)
1183 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1184 bitwise OR, and writes the result back to the bit field in the
1187 Reads the 32-bit PCI configuration register specified by Address, performs a
1188 bitwise AND followed by a bitwise OR between the read result and
1189 the value specified by AndData, and writes the result to the 32-bit PCI
1190 configuration register specified by Address. The value written to the PCI
1191 configuration register is returned. This function must guarantee that all PCI
1192 read and write operations are serialized. Extra left bits in both AndData and
1193 OrData are stripped.
1195 If Address > 0x0FFFFFFF, then ASSERT().
1196 If Address is not aligned on a 32-bit boundary, then ASSERT().
1197 If StartBit is greater than 31, then ASSERT().
1198 If EndBit is greater than 31, then ASSERT().
1199 If EndBit is less than StartBit, then ASSERT().
1201 @param Address PCI configuration register to write.
1202 @param StartBit The ordinal of the least significant bit in the bit field.
1204 @param EndBit The ordinal of the most significant bit in the bit field.
1206 @param AndData The value to AND with the PCI configuration register.
1207 @param OrData The value to OR with the result of the AND operation.
1209 @return The value written back to the PCI configuration register.
1214 PciBitFieldAndThenOr32 (
1224 BitFieldAndThenOr32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
, OrData
)
1229 Reads a range of PCI configuration registers into a caller supplied buffer.
1231 Reads the range of PCI configuration registers specified by StartAddress and
1232 Size into the buffer specified by Buffer. This function only allows the PCI
1233 configuration registers from a single PCI function to be read. Size is
1234 returned. When possible 32-bit PCI configuration read cycles are used to read
1235 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1236 and 16-bit PCI configuration read cycles may be used at the beginning and the
1239 If StartAddress > 0x0FFFFFFF, then ASSERT().
1240 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1241 If Size > 0 and Buffer is NULL, then ASSERT().
1243 @param StartAddress Starting address that encodes the PCI Bus, Device,
1244 Function and Register.
1245 @param Size Size in bytes of the transfer.
1246 @param Buffer Pointer to a buffer receiving the data read.
1254 IN UINTN StartAddress
,
1261 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1262 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1268 ASSERT (Buffer
!= NULL
);
1271 // Save Size for return
1275 if ((StartAddress
& BIT0
) != 0) {
1277 // Read a byte if StartAddress is byte aligned
1279 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1280 StartAddress
+= sizeof (UINT8
);
1281 Size
-= sizeof (UINT8
);
1282 Buffer
= (UINT8
*)Buffer
+ 1;
1285 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1287 // Read a word if StartAddress is word aligned
1289 WriteUnaligned16 (Buffer
, PciRead16 (StartAddress
));
1290 StartAddress
+= sizeof (UINT16
);
1291 Size
-= sizeof (UINT16
);
1292 Buffer
= (UINT16
*)Buffer
+ 1;
1295 while (Size
>= sizeof (UINT32
)) {
1297 // Read as many double words as possible
1299 WriteUnaligned32 (Buffer
, PciRead32 (StartAddress
));
1300 StartAddress
+= sizeof (UINT32
);
1301 Size
-= sizeof (UINT32
);
1302 Buffer
= (UINT32
*)Buffer
+ 1;
1305 if (Size
>= sizeof (UINT16
)) {
1307 // Read the last remaining word if exist
1309 WriteUnaligned16 (Buffer
, PciRead16 (StartAddress
));
1310 StartAddress
+= sizeof (UINT16
);
1311 Size
-= sizeof (UINT16
);
1312 Buffer
= (UINT16
*)Buffer
+ 1;
1315 if (Size
>= sizeof (UINT8
)) {
1317 // Read the last remaining byte if exist
1319 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1326 Copies the data in a caller supplied buffer to a specified range of PCI
1327 configuration space.
1329 Writes the range of PCI configuration registers specified by StartAddress and
1330 Size from the buffer specified by Buffer. This function only allows the PCI
1331 configuration registers from a single PCI function to be written. Size is
1332 returned. When possible 32-bit PCI configuration write cycles are used to
1333 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1334 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1335 and the end of the range.
1337 If StartAddress > 0x0FFFFFFF, then ASSERT().
1338 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1339 If Size > 0 and Buffer is NULL, then ASSERT().
1341 @param StartAddress Starting address that encodes the PCI Bus, Device,
1342 Function and Register.
1343 @param Size Size in bytes of the transfer.
1344 @param Buffer Pointer to a buffer containing the data to write.
1346 @return Size written to StartAddress.
1352 IN UINTN StartAddress
,
1359 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1360 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1366 ASSERT (Buffer
!= NULL
);
1369 // Save Size for return
1373 if ((StartAddress
& BIT0
) != 0) {
1375 // Write a byte if StartAddress is byte aligned
1377 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1378 StartAddress
+= sizeof (UINT8
);
1379 Size
-= sizeof (UINT8
);
1380 Buffer
= (UINT8
*)Buffer
+ 1;
1383 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1385 // Write a word if StartAddress is word aligned
1387 PciWrite16 (StartAddress
, ReadUnaligned16 (Buffer
));
1388 StartAddress
+= sizeof (UINT16
);
1389 Size
-= sizeof (UINT16
);
1390 Buffer
= (UINT16
*)Buffer
+ 1;
1393 while (Size
>= sizeof (UINT32
)) {
1395 // Write as many double words as possible
1397 PciWrite32 (StartAddress
, ReadUnaligned32 (Buffer
));
1398 StartAddress
+= sizeof (UINT32
);
1399 Size
-= sizeof (UINT32
);
1400 Buffer
= (UINT32
*)Buffer
+ 1;
1403 if (Size
>= sizeof (UINT16
)) {
1405 // Write the last remaining word if exist
1407 PciWrite16 (StartAddress
, ReadUnaligned16 (Buffer
));
1408 StartAddress
+= sizeof (UINT16
);
1409 Size
-= sizeof (UINT16
);
1410 Buffer
= (UINT16
*)Buffer
+ 1;
1413 if (Size
>= sizeof (UINT8
)) {
1415 // Write the last remaining byte if exist
1417 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);