2 PCI Library using PCI Root Bridge I/O Protocol.
4 Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials are
6 licensed and made available under the terms and conditions of
7 the BSD License which accompanies this distribution. The full
8 text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php.
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #include <Protocol/PciRootBridgeIo.h>
18 #include <Library/PciLib.h>
19 #include <Library/BaseLib.h>
20 #include <Library/UefiBootServicesTableLib.h>
21 #include <Library/DebugLib.h>
24 Assert the validity of a PCI address. A valid PCI address should contain 1's
25 only in the low 28 bits.
27 @param A The address to validate.
28 @param M Additional bits to assert to be zero.
31 #define ASSERT_INVALID_PCI_ADDRESS(A,M) \
32 ASSERT (((A) & (~0xfffffff | (M))) == 0)
35 Translate PCI Lib address into format of PCI Root Bridge I/O Protocol.
37 @param A The address that encodes the PCI Bus, Device, Function and
41 #define PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS(A) \
42 ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))
45 // Global varible to cache pointer to PCI Root Bridge I/O protocol.
47 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*mPciRootBridgeIo
= NULL
;
50 The constructor function caches the pointer to PCI Root Bridge I/O protocol.
52 The constructor function locates PCI Root Bridge I/O protocol from protocol database.
53 It will ASSERT() if that operation fails and it will always return EFI_SUCCESS.
55 @param ImageHandle The firmware allocated handle for the EFI image.
56 @param SystemTable A pointer to the EFI System Table.
58 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
64 IN EFI_HANDLE ImageHandle
,
65 IN EFI_SYSTEM_TABLE
*SystemTable
70 Status
= gBS
->LocateProtocol (&gEfiPciRootBridgeIoProtocolGuid
, NULL
, (VOID
**) &mPciRootBridgeIo
);
71 ASSERT_EFI_ERROR (Status
);
72 ASSERT (mPciRootBridgeIo
!= NULL
);
78 Internal worker function to read a PCI configuration register.
80 This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Read() service.
81 It reads and returns the PCI configuration register specified by Address,
82 the width of data is specified by Width.
84 @param Address The address that encodes the PCI Bus, Device, Function and
86 @param Width The width of data to read
88 @return The value read from the PCI configuration register.
92 DxePciLibPciRootBridgeIoReadWorker (
94 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
99 mPciRootBridgeIo
->Pci
.Read (
102 PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address
),
111 Internal worker function to writes a PCI configuration register.
113 This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Write() service.
114 It writes the PCI configuration register specified by Address with the
115 value specified by Data. The width of data is specified by Width.
118 @param Address The address that encodes the PCI Bus, Device, Function and
120 @param Width The width of data to write
121 @param Data The value to write.
123 @return The value written to the PCI configuration register.
127 DxePciLibPciRootBridgeIoWriteWorker (
129 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
133 mPciRootBridgeIo
->Pci
.Write (
136 PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address
),
144 Registers a PCI device so PCI configuration registers may be accessed after
145 SetVirtualAddressMap().
147 Registers the PCI device specified by Address so all the PCI configuration registers
148 associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
150 If Address > 0x0FFFFFFF, then ASSERT().
152 @param Address The address that encodes the PCI Bus, Device, Function and
155 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
156 @retval RETURN_UNSUPPORTED An attempt was made to call this function
157 after ExitBootServices().
158 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
159 at runtime could not be mapped.
160 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
161 complete the registration.
166 PciRegisterForRuntimeAccess (
170 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
171 return RETURN_UNSUPPORTED
;
175 Reads an 8-bit PCI configuration register.
177 Reads and returns the 8-bit PCI configuration register specified by Address.
178 This function must guarantee that all PCI read and write operations are
181 If Address > 0x0FFFFFFF, then ASSERT().
183 @param Address The address that encodes the PCI Bus, Device, Function and
186 @return The read value from the PCI configuration register.
195 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
197 return (UINT8
) DxePciLibPciRootBridgeIoReadWorker (Address
, EfiPciWidthUint8
);
201 Writes an 8-bit PCI configuration register.
203 Writes the 8-bit PCI configuration register specified by Address with the
204 value specified by Value. Value is returned. This function must guarantee
205 that all PCI read and write operations are serialized.
207 If Address > 0x0FFFFFFF, then ASSERT().
209 @param Address The address that encodes the PCI Bus, Device, Function and
211 @param Value The value to write.
213 @return The value written to the PCI configuration register.
223 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
225 return (UINT8
) DxePciLibPciRootBridgeIoWriteWorker (Address
, EfiPciWidthUint8
, Value
);
229 Performs a bitwise OR of an 8-bit PCI configuration register with
232 Reads the 8-bit PCI configuration register specified by Address, performs a
233 bitwise OR between the read result and the value specified by
234 OrData, and writes the result to the 8-bit PCI configuration register
235 specified by Address. The value written to the PCI configuration register is
236 returned. This function must guarantee that all PCI read and write operations
239 If Address > 0x0FFFFFFF, then ASSERT().
241 @param Address The address that encodes the PCI Bus, Device, Function and
243 @param OrData The value to OR with the PCI configuration register.
245 @return The value written back to the PCI configuration register.
255 return PciWrite8 (Address
, (UINT8
) (PciRead8 (Address
) | OrData
));
259 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
262 Reads the 8-bit PCI configuration register specified by Address, performs a
263 bitwise AND between the read result and the value specified by AndData, and
264 writes the result to the 8-bit PCI configuration register specified by
265 Address. The value written to the PCI configuration register is returned.
266 This function must guarantee that all PCI read and write operations are
269 If Address > 0x0FFFFFFF, then ASSERT().
271 @param Address The address that encodes the PCI Bus, Device, Function and
273 @param AndData The value to AND with the PCI configuration register.
275 @return The value written back to the PCI configuration register.
285 return PciWrite8 (Address
, (UINT8
) (PciRead8 (Address
) & AndData
));
289 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
290 value, followed a bitwise OR with another 8-bit value.
292 Reads the 8-bit PCI configuration register specified by Address, performs a
293 bitwise AND between the read result and the value specified by AndData,
294 performs a bitwise OR between the result of the AND operation and
295 the value specified by OrData, and writes the result to the 8-bit PCI
296 configuration register specified by Address. The value written to the PCI
297 configuration register is returned. This function must guarantee that all PCI
298 read and write operations are serialized.
300 If Address > 0x0FFFFFFF, then ASSERT().
302 @param Address The address that encodes the PCI Bus, Device, Function and
304 @param AndData The value to AND with the PCI configuration register.
305 @param OrData The value to OR with the result of the AND operation.
307 @return The value written back to the PCI configuration register.
318 return PciWrite8 (Address
, (UINT8
) ((PciRead8 (Address
) & AndData
) | OrData
));
322 Reads a bit field of a PCI configuration register.
324 Reads the bit field in an 8-bit PCI configuration register. The bit field is
325 specified by the StartBit and the EndBit. The value of the bit field is
328 If Address > 0x0FFFFFFF, then ASSERT().
329 If StartBit is greater than 7, then ASSERT().
330 If EndBit is greater than 7, then ASSERT().
331 If EndBit is less than StartBit, then ASSERT().
333 @param Address The PCI configuration register to read.
334 @param StartBit The ordinal of the least significant bit in the bit field.
336 @param EndBit The ordinal of the most significant bit in the bit field.
339 @return The value of the bit field read from the PCI configuration register.
350 return BitFieldRead8 (PciRead8 (Address
), StartBit
, EndBit
);
354 Writes a bit field to a PCI configuration register.
356 Writes Value to the bit field of the PCI configuration register. The bit
357 field is specified by the StartBit and the EndBit. All other bits in the
358 destination PCI configuration register are preserved. The new value of the
359 8-bit register is returned.
361 If Address > 0x0FFFFFFF, then ASSERT().
362 If StartBit is greater than 7, then ASSERT().
363 If EndBit is greater than 7, then ASSERT().
364 If EndBit is less than StartBit, then ASSERT().
365 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
367 @param Address The PCI configuration register to write.
368 @param StartBit The ordinal of the least significant bit in the bit field.
370 @param EndBit The ordinal of the most significant bit in the bit field.
372 @param Value The new value of the bit field.
374 @return The value written back to the PCI configuration register.
388 BitFieldWrite8 (PciRead8 (Address
), StartBit
, EndBit
, Value
)
393 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
394 writes the result back to the bit field in the 8-bit port.
396 Reads the 8-bit PCI configuration register specified by Address, performs a
397 bitwise OR between the read result and the value specified by
398 OrData, and writes the result to the 8-bit PCI configuration register
399 specified by Address. The value written to the PCI configuration register is
400 returned. This function must guarantee that all PCI read and write operations
401 are serialized. Extra left bits in OrData are stripped.
403 If Address > 0x0FFFFFFF, then ASSERT().
404 If StartBit is greater than 7, then ASSERT().
405 If EndBit is greater than 7, then ASSERT().
406 If EndBit is less than StartBit, then ASSERT().
407 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
409 @param Address The PCI configuration register to write.
410 @param StartBit The ordinal of the least significant bit in the bit field.
412 @param EndBit The ordinal of the most significant bit in the bit field.
414 @param OrData The value to OR with the PCI configuration register.
416 @return The value written back to the PCI configuration register.
430 BitFieldOr8 (PciRead8 (Address
), StartBit
, EndBit
, OrData
)
435 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
436 AND, and writes the result back to the bit field in the 8-bit register.
438 Reads the 8-bit PCI configuration register specified by Address, performs a
439 bitwise AND between the read result and the value specified by AndData, and
440 writes the result to the 8-bit PCI configuration register specified by
441 Address. The value written to the PCI configuration register is returned.
442 This function must guarantee that all PCI read and write operations are
443 serialized. Extra left bits in AndData are stripped.
445 If Address > 0x0FFFFFFF, then ASSERT().
446 If StartBit is greater than 7, then ASSERT().
447 If EndBit is greater than 7, then ASSERT().
448 If EndBit is less than StartBit, then ASSERT().
449 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
451 @param Address The PCI configuration register to write.
452 @param StartBit The ordinal of the least significant bit in the bit field.
454 @param EndBit The ordinal of the most significant bit in the bit field.
456 @param AndData The value to AND with the PCI configuration register.
458 @return The value written back to the PCI configuration register.
472 BitFieldAnd8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
)
477 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
478 bitwise OR, and writes the result back to the bit field in the
481 Reads the 8-bit PCI configuration register specified by Address, performs a
482 bitwise AND followed by a bitwise OR between the read result and
483 the value specified by AndData, and writes the result to the 8-bit PCI
484 configuration register specified by Address. The value written to the PCI
485 configuration register is returned. This function must guarantee that all PCI
486 read and write operations are serialized. Extra left bits in both AndData and
489 If Address > 0x0FFFFFFF, then ASSERT().
490 If StartBit is greater than 7, then ASSERT().
491 If EndBit is greater than 7, then ASSERT().
492 If EndBit is less than StartBit, then ASSERT().
493 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
494 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
496 @param Address The PCI configuration register to write.
497 @param StartBit The ordinal of the least significant bit in the bit field.
499 @param EndBit The ordinal of the most significant bit in the bit field.
501 @param AndData The value to AND with the PCI configuration register.
502 @param OrData The value to OR with the result of the AND operation.
504 @return The value written back to the PCI configuration register.
509 PciBitFieldAndThenOr8 (
519 BitFieldAndThenOr8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
, OrData
)
524 Reads a 16-bit PCI configuration register.
526 Reads and returns the 16-bit PCI configuration register specified by Address.
527 This function must guarantee that all PCI read and write operations are
530 If Address > 0x0FFFFFFF, then ASSERT().
531 If Address is not aligned on a 16-bit boundary, then ASSERT().
533 @param Address The address that encodes the PCI Bus, Device, Function and
536 @return The read value from the PCI configuration register.
545 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
547 return (UINT16
) DxePciLibPciRootBridgeIoReadWorker (Address
, EfiPciWidthUint16
);
551 Writes a 16-bit PCI configuration register.
553 Writes the 16-bit PCI configuration register specified by Address with the
554 value specified by Value. Value is returned. This function must guarantee
555 that all PCI read and write operations are serialized.
557 If Address > 0x0FFFFFFF, then ASSERT().
558 If Address is not aligned on a 16-bit boundary, then ASSERT().
560 @param Address The address that encodes the PCI Bus, Device, Function and
562 @param Value The value to write.
564 @return The value written to the PCI configuration register.
574 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
576 return (UINT16
) DxePciLibPciRootBridgeIoWriteWorker (Address
, EfiPciWidthUint16
, Value
);
580 Performs a bitwise OR of a 16-bit PCI configuration register with
583 Reads the 16-bit PCI configuration register specified by Address, performs a
584 bitwise OR between the read result and the value specified by
585 OrData, and writes the result to the 16-bit PCI configuration register
586 specified by Address. The value written to the PCI configuration register is
587 returned. This function must guarantee that all PCI read and write operations
590 If Address > 0x0FFFFFFF, then ASSERT().
591 If Address is not aligned on a 16-bit boundary, then ASSERT().
593 @param Address The address that encodes the PCI Bus, Device, Function and
595 @param OrData The value to OR with the PCI configuration register.
597 @return The value written back to the PCI configuration register.
607 return PciWrite16 (Address
, (UINT16
) (PciRead16 (Address
) | OrData
));
611 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
614 Reads the 16-bit PCI configuration register specified by Address, performs a
615 bitwise AND between the read result and the value specified by AndData, and
616 writes the result to the 16-bit PCI configuration register specified by
617 Address. The value written to the PCI configuration register is returned.
618 This function must guarantee that all PCI read and write operations are
621 If Address > 0x0FFFFFFF, then ASSERT().
622 If Address is not aligned on a 16-bit boundary, then ASSERT().
624 @param Address The address that encodes the PCI Bus, Device, Function and
626 @param AndData The value to AND with the PCI configuration register.
628 @return The value written back to the PCI configuration register.
638 return PciWrite16 (Address
, (UINT16
) (PciRead16 (Address
) & AndData
));
642 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
643 value, followed a bitwise OR with another 16-bit value.
645 Reads the 16-bit PCI configuration register specified by Address, performs a
646 bitwise AND between the read result and the value specified by AndData,
647 performs a bitwise OR between the result of the AND operation and
648 the value specified by OrData, and writes the result to the 16-bit PCI
649 configuration register specified by Address. The value written to the PCI
650 configuration register is returned. This function must guarantee that all PCI
651 read and write operations are serialized.
653 If Address > 0x0FFFFFFF, then ASSERT().
654 If Address is not aligned on a 16-bit boundary, then ASSERT().
656 @param Address The address that encodes the PCI Bus, Device, Function and
658 @param AndData The value to AND with the PCI configuration register.
659 @param OrData The value to OR with the result of the AND operation.
661 @return The value written back to the PCI configuration register.
672 return PciWrite16 (Address
, (UINT16
) ((PciRead16 (Address
) & AndData
) | OrData
));
676 Reads a bit field of a PCI configuration register.
678 Reads the bit field in a 16-bit PCI configuration register. The bit field is
679 specified by the StartBit and the EndBit. The value of the bit field is
682 If Address > 0x0FFFFFFF, then ASSERT().
683 If Address is not aligned on a 16-bit boundary, then ASSERT().
684 If StartBit is greater than 15, then ASSERT().
685 If EndBit is greater than 15, then ASSERT().
686 If EndBit is less than StartBit, then ASSERT().
688 @param Address The PCI configuration register to read.
689 @param StartBit The ordinal of the least significant bit in the bit field.
691 @param EndBit The ordinal of the most significant bit in the bit field.
694 @return The value of the bit field read from the PCI configuration register.
705 return BitFieldRead16 (PciRead16 (Address
), StartBit
, EndBit
);
709 Writes a bit field to a PCI configuration register.
711 Writes Value to the bit field of the PCI configuration register. The bit
712 field is specified by the StartBit and the EndBit. All other bits in the
713 destination PCI configuration register are preserved. The new value of the
714 16-bit register is returned.
716 If Address > 0x0FFFFFFF, then ASSERT().
717 If Address is not aligned on a 16-bit boundary, then ASSERT().
718 If StartBit is greater than 15, then ASSERT().
719 If EndBit is greater than 15, then ASSERT().
720 If EndBit is less than StartBit, then ASSERT().
721 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
723 @param Address The PCI configuration register to write.
724 @param StartBit The ordinal of the least significant bit in the bit field.
726 @param EndBit The ordinal of the most significant bit in the bit field.
728 @param Value The new value of the bit field.
730 @return The value written back to the PCI configuration register.
744 BitFieldWrite16 (PciRead16 (Address
), StartBit
, EndBit
, Value
)
749 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
750 writes the result back to the bit field in the 16-bit port.
752 Reads the 16-bit PCI configuration register specified by Address, performs a
753 bitwise OR between the read result and the value specified by
754 OrData, and writes the result to the 16-bit PCI configuration register
755 specified by Address. The value written to the PCI configuration register is
756 returned. This function must guarantee that all PCI read and write operations
757 are serialized. Extra left bits in OrData are stripped.
759 If Address > 0x0FFFFFFF, then ASSERT().
760 If Address is not aligned on a 16-bit boundary, then ASSERT().
761 If StartBit is greater than 15, then ASSERT().
762 If EndBit is greater than 15, then ASSERT().
763 If EndBit is less than StartBit, then ASSERT().
764 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
766 @param Address The PCI configuration register to write.
767 @param StartBit The ordinal of the least significant bit in the bit field.
769 @param EndBit The ordinal of the most significant bit in the bit field.
771 @param OrData The value to OR with the PCI configuration register.
773 @return The value written back to the PCI configuration register.
787 BitFieldOr16 (PciRead16 (Address
), StartBit
, EndBit
, OrData
)
792 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
793 AND, and writes the result back to the bit field in the 16-bit register.
795 Reads the 16-bit PCI configuration register specified by Address, performs a
796 bitwise AND between the read result and the value specified by AndData, and
797 writes the result to the 16-bit PCI configuration register specified by
798 Address. The value written to the PCI configuration register is returned.
799 This function must guarantee that all PCI read and write operations are
800 serialized. Extra left bits in AndData are stripped.
802 If Address > 0x0FFFFFFF, then ASSERT().
803 If Address is not aligned on a 16-bit boundary, then ASSERT().
804 If StartBit is greater than 15, then ASSERT().
805 If EndBit is greater than 15, then ASSERT().
806 If EndBit is less than StartBit, then ASSERT().
807 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
809 @param Address The PCI configuration register to write.
810 @param StartBit The ordinal of the least significant bit in the bit field.
812 @param EndBit The ordinal of the most significant bit in the bit field.
814 @param AndData The value to AND with the PCI configuration register.
816 @return The value written back to the PCI configuration register.
830 BitFieldAnd16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
)
835 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
836 bitwise OR, and writes the result back to the bit field in the
839 Reads the 16-bit PCI configuration register specified by Address, performs a
840 bitwise AND followed by a bitwise OR between the read result and
841 the value specified by AndData, and writes the result to the 16-bit PCI
842 configuration register specified by Address. The value written to the PCI
843 configuration register is returned. This function must guarantee that all PCI
844 read and write operations are serialized. Extra left bits in both AndData and
847 If Address > 0x0FFFFFFF, then ASSERT().
848 If Address is not aligned on a 16-bit boundary, then ASSERT().
849 If StartBit is greater than 15, then ASSERT().
850 If EndBit is greater than 15, then ASSERT().
851 If EndBit is less than StartBit, then ASSERT().
852 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
853 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
855 @param Address The PCI configuration register to write.
856 @param StartBit The ordinal of the least significant bit in the bit field.
858 @param EndBit The ordinal of the most significant bit in the bit field.
860 @param AndData The value to AND with the PCI configuration register.
861 @param OrData The value to OR with the result of the AND operation.
863 @return The value written back to the PCI configuration register.
868 PciBitFieldAndThenOr16 (
878 BitFieldAndThenOr16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
, OrData
)
883 Reads a 32-bit PCI configuration register.
885 Reads and returns the 32-bit PCI configuration register specified by Address.
886 This function must guarantee that all PCI read and write operations are
889 If Address > 0x0FFFFFFF, then ASSERT().
890 If Address is not aligned on a 32-bit boundary, then ASSERT().
892 @param Address The address that encodes the PCI Bus, Device, Function and
895 @return The read value from the PCI configuration register.
904 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
906 return DxePciLibPciRootBridgeIoReadWorker (Address
, EfiPciWidthUint32
);
910 Writes a 32-bit PCI configuration register.
912 Writes the 32-bit PCI configuration register specified by Address with the
913 value specified by Value. Value is returned. This function must guarantee
914 that all PCI read and write operations are serialized.
916 If Address > 0x0FFFFFFF, then ASSERT().
917 If Address is not aligned on a 32-bit boundary, then ASSERT().
919 @param Address The address that encodes the PCI Bus, Device, Function and
921 @param Value The value to write.
923 @return The value written to the PCI configuration register.
933 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
935 return DxePciLibPciRootBridgeIoWriteWorker (Address
, EfiPciWidthUint32
, Value
);
939 Performs a bitwise OR of a 32-bit PCI configuration register with
942 Reads the 32-bit PCI configuration register specified by Address, performs a
943 bitwise OR between the read result and the value specified by
944 OrData, and writes the result to the 32-bit PCI configuration register
945 specified by Address. The value written to the PCI configuration register is
946 returned. This function must guarantee that all PCI read and write operations
949 If Address > 0x0FFFFFFF, then ASSERT().
950 If Address is not aligned on a 32-bit boundary, then ASSERT().
952 @param Address The address that encodes the PCI Bus, Device, Function and
954 @param OrData The value to OR with the PCI configuration register.
956 @return The value written back to the PCI configuration register.
966 return PciWrite32 (Address
, PciRead32 (Address
) | OrData
);
970 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
973 Reads the 32-bit PCI configuration register specified by Address, performs a
974 bitwise AND between the read result and the value specified by AndData, and
975 writes the result to the 32-bit PCI configuration register specified by
976 Address. The value written to the PCI configuration register is returned.
977 This function must guarantee that all PCI read and write operations are
980 If Address > 0x0FFFFFFF, then ASSERT().
981 If Address is not aligned on a 32-bit boundary, then ASSERT().
983 @param Address The address that encodes the PCI Bus, Device, Function and
985 @param AndData The value to AND with the PCI configuration register.
987 @return The value written back to the PCI configuration register.
997 return PciWrite32 (Address
, PciRead32 (Address
) & AndData
);
1001 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
1002 value, followed a bitwise OR with another 32-bit value.
1004 Reads the 32-bit PCI configuration register specified by Address, performs a
1005 bitwise AND between the read result and the value specified by AndData,
1006 performs a bitwise OR between the result of the AND operation and
1007 the value specified by OrData, and writes the result to the 32-bit PCI
1008 configuration register specified by Address. The value written to the PCI
1009 configuration register is returned. This function must guarantee that all PCI
1010 read and write operations are serialized.
1012 If Address > 0x0FFFFFFF, then ASSERT().
1013 If Address is not aligned on a 32-bit boundary, then ASSERT().
1015 @param Address The address that encodes the PCI Bus, Device, Function and
1017 @param AndData The value to AND with the PCI configuration register.
1018 @param OrData The value to OR with the result of the AND operation.
1020 @return The value written back to the PCI configuration register.
1031 return PciWrite32 (Address
, (PciRead32 (Address
) & AndData
) | OrData
);
1035 Reads a bit field of a PCI configuration register.
1037 Reads the bit field in a 32-bit PCI configuration register. The bit field is
1038 specified by the StartBit and the EndBit. The value of the bit field is
1041 If Address > 0x0FFFFFFF, then ASSERT().
1042 If Address is not aligned on a 32-bit boundary, then ASSERT().
1043 If StartBit is greater than 31, then ASSERT().
1044 If EndBit is greater than 31, then ASSERT().
1045 If EndBit is less than StartBit, then ASSERT().
1047 @param Address The PCI configuration register to read.
1048 @param StartBit The ordinal of the least significant bit in the bit field.
1050 @param EndBit The ordinal of the most significant bit in the bit field.
1053 @return The value of the bit field read from the PCI configuration register.
1064 return BitFieldRead32 (PciRead32 (Address
), StartBit
, EndBit
);
1068 Writes a bit field to a PCI configuration register.
1070 Writes Value to the bit field of the PCI configuration register. The bit
1071 field is specified by the StartBit and the EndBit. All other bits in the
1072 destination PCI configuration register are preserved. The new value of the
1073 32-bit register is returned.
1075 If Address > 0x0FFFFFFF, then ASSERT().
1076 If Address is not aligned on a 32-bit boundary, then ASSERT().
1077 If StartBit is greater than 31, then ASSERT().
1078 If EndBit is greater than 31, then ASSERT().
1079 If EndBit is less than StartBit, then ASSERT().
1080 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1082 @param Address The PCI configuration register to write.
1083 @param StartBit The ordinal of the least significant bit in the bit field.
1085 @param EndBit The ordinal of the most significant bit in the bit field.
1087 @param Value The new value of the bit field.
1089 @return The value written back to the PCI configuration register.
1094 PciBitFieldWrite32 (
1103 BitFieldWrite32 (PciRead32 (Address
), StartBit
, EndBit
, Value
)
1108 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1109 writes the result back to the bit field in the 32-bit port.
1111 Reads the 32-bit PCI configuration register specified by Address, performs a
1112 bitwise OR between the read result and the value specified by
1113 OrData, and writes the result to the 32-bit PCI configuration register
1114 specified by Address. The value written to the PCI configuration register is
1115 returned. This function must guarantee that all PCI read and write operations
1116 are serialized. Extra left bits in OrData are stripped.
1118 If Address > 0x0FFFFFFF, then ASSERT().
1119 If Address is not aligned on a 32-bit boundary, then ASSERT().
1120 If StartBit is greater than 31, then ASSERT().
1121 If EndBit is greater than 31, then ASSERT().
1122 If EndBit is less than StartBit, then ASSERT().
1123 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1125 @param Address The PCI configuration register to write.
1126 @param StartBit The ordinal of the least significant bit in the bit field.
1128 @param EndBit The ordinal of the most significant bit in the bit field.
1130 @param OrData The value to OR with the PCI configuration register.
1132 @return The value written back to the PCI configuration register.
1146 BitFieldOr32 (PciRead32 (Address
), StartBit
, EndBit
, OrData
)
1151 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1152 AND, and writes the result back to the bit field in the 32-bit register.
1154 Reads the 32-bit PCI configuration register specified by Address, performs a
1155 bitwise AND between the read result and the value specified by AndData, and
1156 writes the result to the 32-bit PCI configuration register specified by
1157 Address. The value written to the PCI configuration register is returned.
1158 This function must guarantee that all PCI read and write operations are
1159 serialized. Extra left bits in AndData are stripped.
1161 If Address > 0x0FFFFFFF, then ASSERT().
1162 If Address is not aligned on a 32-bit boundary, then ASSERT().
1163 If StartBit is greater than 31, then ASSERT().
1164 If EndBit is greater than 31, then ASSERT().
1165 If EndBit is less than StartBit, then ASSERT().
1166 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1168 @param Address The PCI configuration register to write.
1169 @param StartBit The ordinal of the least significant bit in the bit field.
1171 @param EndBit The ordinal of the most significant bit in the bit field.
1173 @param AndData The value to AND with the PCI configuration register.
1175 @return The value written back to the PCI configuration register.
1189 BitFieldAnd32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
)
1194 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1195 bitwise OR, and writes the result back to the bit field in the
1198 Reads the 32-bit PCI configuration register specified by Address, performs a
1199 bitwise AND followed by a bitwise OR between the read result and
1200 the value specified by AndData, and writes the result to the 32-bit PCI
1201 configuration register specified by Address. The value written to the PCI
1202 configuration register is returned. This function must guarantee that all PCI
1203 read and write operations are serialized. Extra left bits in both AndData and
1204 OrData are stripped.
1206 If Address > 0x0FFFFFFF, then ASSERT().
1207 If Address is not aligned on a 32-bit boundary, then ASSERT().
1208 If StartBit is greater than 31, then ASSERT().
1209 If EndBit is greater than 31, then ASSERT().
1210 If EndBit is less than StartBit, then ASSERT().
1211 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1212 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1214 @param Address The PCI configuration register to write.
1215 @param StartBit The ordinal of the least significant bit in the bit field.
1217 @param EndBit The ordinal of the most significant bit in the bit field.
1219 @param AndData The value to AND with the PCI configuration register.
1220 @param OrData The value to OR with the result of the AND operation.
1222 @return The value written back to the PCI configuration register.
1227 PciBitFieldAndThenOr32 (
1237 BitFieldAndThenOr32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
, OrData
)
1242 Reads a range of PCI configuration registers into a caller supplied buffer.
1244 Reads the range of PCI configuration registers specified by StartAddress and
1245 Size into the buffer specified by Buffer. This function only allows the PCI
1246 configuration registers from a single PCI function to be read. Size is
1247 returned. When possible 32-bit PCI configuration read cycles are used to read
1248 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1249 and 16-bit PCI configuration read cycles may be used at the beginning and the
1252 If StartAddress > 0x0FFFFFFF, then ASSERT().
1253 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1254 If Size > 0 and Buffer is NULL, then ASSERT().
1256 @param StartAddress The starting address that encodes the PCI Bus, Device,
1257 Function and Register.
1258 @param Size The size in bytes of the transfer.
1259 @param Buffer The pointer to a buffer receiving the data read.
1267 IN UINTN StartAddress
,
1274 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1275 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1281 ASSERT (Buffer
!= NULL
);
1284 // Save Size for return
1288 if ((StartAddress
& BIT0
) != 0) {
1290 // Read a byte if StartAddress is byte aligned
1292 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1293 StartAddress
+= sizeof (UINT8
);
1294 Size
-= sizeof (UINT8
);
1295 Buffer
= (UINT8
*)Buffer
+ 1;
1298 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1300 // Read a word if StartAddress is word aligned
1302 WriteUnaligned16 (Buffer
, PciRead16 (StartAddress
));
1303 StartAddress
+= sizeof (UINT16
);
1304 Size
-= sizeof (UINT16
);
1305 Buffer
= (UINT16
*)Buffer
+ 1;
1308 while (Size
>= sizeof (UINT32
)) {
1310 // Read as many double words as possible
1312 WriteUnaligned32 (Buffer
, PciRead32 (StartAddress
));
1313 StartAddress
+= sizeof (UINT32
);
1314 Size
-= sizeof (UINT32
);
1315 Buffer
= (UINT32
*)Buffer
+ 1;
1318 if (Size
>= sizeof (UINT16
)) {
1320 // Read the last remaining word if exist
1322 WriteUnaligned16 (Buffer
, PciRead16 (StartAddress
));
1323 StartAddress
+= sizeof (UINT16
);
1324 Size
-= sizeof (UINT16
);
1325 Buffer
= (UINT16
*)Buffer
+ 1;
1328 if (Size
>= sizeof (UINT8
)) {
1330 // Read the last remaining byte if exist
1332 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1339 Copies the data in a caller supplied buffer to a specified range of PCI
1340 configuration space.
1342 Writes the range of PCI configuration registers specified by StartAddress and
1343 Size from the buffer specified by Buffer. This function only allows the PCI
1344 configuration registers from a single PCI function to be written. Size is
1345 returned. When possible 32-bit PCI configuration write cycles are used to
1346 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1347 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1348 and the end of the range.
1350 If StartAddress > 0x0FFFFFFF, then ASSERT().
1351 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1352 If Size > 0 and Buffer is NULL, then ASSERT().
1354 @param StartAddress The starting address that encodes the PCI Bus, Device,
1355 Function and Register.
1356 @param Size The size in bytes of the transfer.
1357 @param Buffer The pointer to a buffer containing the data to write.
1359 @return Size written to StartAddress.
1365 IN UINTN StartAddress
,
1372 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1373 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1379 ASSERT (Buffer
!= NULL
);
1382 // Save Size for return
1386 if ((StartAddress
& BIT0
) != 0) {
1388 // Write a byte if StartAddress is byte aligned
1390 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1391 StartAddress
+= sizeof (UINT8
);
1392 Size
-= sizeof (UINT8
);
1393 Buffer
= (UINT8
*)Buffer
+ 1;
1396 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1398 // Write a word if StartAddress is word aligned
1400 PciWrite16 (StartAddress
, ReadUnaligned16 (Buffer
));
1401 StartAddress
+= sizeof (UINT16
);
1402 Size
-= sizeof (UINT16
);
1403 Buffer
= (UINT16
*)Buffer
+ 1;
1406 while (Size
>= sizeof (UINT32
)) {
1408 // Write as many double words as possible
1410 PciWrite32 (StartAddress
, ReadUnaligned32 (Buffer
));
1411 StartAddress
+= sizeof (UINT32
);
1412 Size
-= sizeof (UINT32
);
1413 Buffer
= (UINT32
*)Buffer
+ 1;
1416 if (Size
>= sizeof (UINT16
)) {
1418 // Write the last remaining word if exist
1420 PciWrite16 (StartAddress
, ReadUnaligned16 (Buffer
));
1421 StartAddress
+= sizeof (UINT16
);
1422 Size
-= sizeof (UINT16
);
1423 Buffer
= (UINT16
*)Buffer
+ 1;
1426 if (Size
>= sizeof (UINT8
)) {
1428 // Write the last remaining byte if exist
1430 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);