2 PCI Segment Library implementation using PCI Root Bridge I/O Protocol.
4 Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials are
6 licensed and made available under the terms and conditions of
7 the BSD License which accompanies this distribution. The full
8 text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php.
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #include "PciSegmentLib.h"
19 // Global variable to record data of PCI Root Bridge I/O Protocol instances
21 PCI_ROOT_BRIDGE_DATA
*mPciRootBridgeData
= NULL
;
22 UINTN mNumberOfPciRootBridges
= 0;
25 The constructor function caches data of PCI Root Bridge I/O Protocol instances.
27 The constructor function locates PCI Root Bridge I/O protocol instances,
28 and caches the protocol instances, together with their segment numbers and bus ranges.
29 It will ASSERT() if that related operation fails and it will always return EFI_SUCCESS.
31 @param ImageHandle The firmware allocated handle for the EFI image.
32 @param SystemTable A pointer to the EFI System Table.
34 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
39 PciSegmentLibConstructor (
40 IN EFI_HANDLE ImageHandle
,
41 IN EFI_SYSTEM_TABLE
*SystemTable
47 EFI_HANDLE
*HandleBuffer
;
48 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
49 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
53 PciRootBridgeIo
= NULL
;
56 Status
= gBS
->LocateHandleBuffer (
58 &gEfiPciRootBridgeIoProtocolGuid
,
63 ASSERT_EFI_ERROR (Status
);
65 mNumberOfPciRootBridges
= HandleCount
;
67 mPciRootBridgeData
= AllocatePool (HandleCount
* sizeof (PCI_ROOT_BRIDGE_DATA
));
68 ASSERT (mPciRootBridgeData
!= NULL
);
71 // Traverse all PCI Root Bridge I/O Protocol instances, and record the protocol
72 // instances, together with their segment numbers and bus ranges.
74 for (Index
= 0; Index
< HandleCount
; Index
++) {
75 Status
= gBS
->HandleProtocol (
77 &gEfiPciRootBridgeIoProtocolGuid
,
78 (VOID
**) &PciRootBridgeIo
80 ASSERT_EFI_ERROR (Status
);
82 mPciRootBridgeData
[Index
].PciRootBridgeIo
= PciRootBridgeIo
;
83 mPciRootBridgeData
[Index
].SegmentNumber
= PciRootBridgeIo
->SegmentNumber
;
85 Status
= PciRootBridgeIo
->Configuration (PciRootBridgeIo
, (VOID
**) &Descriptors
);
86 ASSERT_EFI_ERROR (Status
);
88 while (Descriptors
->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
89 if (Descriptors
->ResType
== ACPI_ADDRESS_SPACE_TYPE_BUS
) {
90 mPciRootBridgeData
[Index
].MinBusNumber
= Descriptors
->AddrRangeMin
;
91 mPciRootBridgeData
[Index
].MaxBusNumber
= Descriptors
->AddrRangeMax
;
96 ASSERT (Descriptors
->Desc
!= ACPI_END_TAG_DESCRIPTOR
);
99 FreePool(HandleBuffer
);
105 The destructor function frees memory allocated by constructor.
107 The destructor function frees memory for data of protocol instances allocated by constructor.
108 It will ASSERT() if that related operation fails and it will always return EFI_SUCCESS.
110 @param ImageHandle The firmware allocated handle for the EFI image.
111 @param SystemTable A pointer to the EFI System Table.
113 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
118 PciSegmentLibDestructor (
119 IN EFI_HANDLE ImageHandle
,
120 IN EFI_SYSTEM_TABLE
*SystemTable
123 FreePool (mPciRootBridgeData
);
129 According to address, search for the corresponding PCI Root Bridge I/O Protocol instance.
131 This internal function extracts segment number and bus number data from address, and
132 retrieves the corresponding PCI Root Bridge I/O Protocol instance.
134 @param Address The address that encodes the Segment, PCI Bus, Device, Function and
137 @return The address for PCI Root Bridge I/O Protocol.
140 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*
141 PciSegmentLibSearchForRootBridge (
146 UINT64 SegmentNumber
;
149 for (Index
= 0; Index
< mNumberOfPciRootBridges
; Index
++) {
151 // Matches segment number of address with the segment number of protocol instance.
153 SegmentNumber
= BitFieldRead64 (Address
, 32, 63);
154 if (SegmentNumber
== mPciRootBridgeData
[Index
].SegmentNumber
) {
156 // Matches the bus number of address with bus number range of protocol instance.
158 BusNumber
= BitFieldRead64 (Address
, 20, 27);
159 if (BusNumber
>= mPciRootBridgeData
[Index
].MinBusNumber
&& BusNumber
<= mPciRootBridgeData
[Index
].MaxBusNumber
) {
160 return mPciRootBridgeData
[Index
].PciRootBridgeIo
;
168 Internal worker function to read a PCI configuration register.
170 This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Read() service.
171 It reads and returns the PCI configuration register specified by Address,
172 the width of data is specified by Width.
174 @param Address The address that encodes the PCI Bus, Device, Function and
176 @param Width Width of data to read
178 @return The value read from the PCI configuration register.
182 DxePciSegmentLibPciRootBridgeIoReadWorker (
184 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
188 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
190 PciRootBridgeIo
= PciSegmentLibSearchForRootBridge (Address
);
191 ASSERT (PciRootBridgeIo
!= NULL
);
193 PciRootBridgeIo
->Pci
.Read (
196 PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address
),
205 Internal worker function to writes a PCI configuration register.
207 This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Write() service.
208 It writes the PCI configuration register specified by Address with the
209 value specified by Data. The width of data is specifed by Width.
212 @param Address The address that encodes the PCI Bus, Device, Function and
214 @param Width Width of data to write
215 @param Data The value to write.
217 @return The value written to the PCI configuration register.
221 DxePciSegmentLibPciRootBridgeIoWriteWorker (
223 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
227 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
229 PciRootBridgeIo
= PciSegmentLibSearchForRootBridge (Address
);
230 ASSERT (PciRootBridgeIo
!= NULL
);
232 PciRootBridgeIo
->Pci
.Write (
235 PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address
),
244 Register a PCI device so PCI configuration registers may be accessed after
245 SetVirtualAddressMap().
247 If any reserved bits in Address are set, then ASSERT().
249 @param Address The address that encodes the PCI Bus, Device, Function and
252 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
253 @retval RETURN_UNSUPPORTED An attempt was made to call this function
254 after ExitBootServices().
255 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
256 at runtime could not be mapped.
257 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
258 complete the registration.
263 PciSegmentRegisterForRuntimeAccess (
267 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address
, 0);
268 return RETURN_UNSUPPORTED
;
272 Reads an 8-bit PCI configuration register.
274 Reads and returns the 8-bit PCI configuration register specified by Address.
275 This function must guarantee that all PCI read and write operations are serialized.
277 If any reserved bits in Address are set, then ASSERT().
279 @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
281 @return The 8-bit PCI configuration register specified by Address.
290 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address
, 0);
292 return (UINT8
) DxePciSegmentLibPciRootBridgeIoReadWorker (Address
, EfiPciWidthUint8
);
296 Writes an 8-bit PCI configuration register.
298 Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
299 Value is returned. This function must guarantee that all PCI read and write operations are serialized.
301 If any reserved bits in Address are set, then ASSERT().
303 @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
304 @param Value The value to write.
306 @return The value written to the PCI configuration register.
316 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address
, 0);
318 return (UINT8
) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address
, EfiPciWidthUint8
, Value
);
322 Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
324 Reads the 8-bit PCI configuration register specified by Address,
325 performs a bitwise OR between the read result and the value specified by OrData,
326 and writes the result to the 8-bit PCI configuration register specified by Address.
327 The value written to the PCI configuration register is returned.
328 This function must guarantee that all PCI read and write operations are serialized.
330 If any reserved bits in Address are set, then ASSERT().
332 @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
333 @param OrData The value to OR with the PCI configuration register.
335 @return The value written to the PCI configuration register.
345 return PciSegmentWrite8 (Address
, (UINT8
) (PciSegmentRead8 (Address
) | OrData
));
349 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
351 Reads the 8-bit PCI configuration register specified by Address,
352 performs a bitwise AND between the read result and the value specified by AndData,
353 and writes the result to the 8-bit PCI configuration register specified by Address.
354 The value written to the PCI configuration register is returned.
355 This function must guarantee that all PCI read and write operations are serialized.
356 If any reserved bits in Address are set, then ASSERT().
358 @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
359 @param AndData The value to AND with the PCI configuration register.
361 @return The value written to the PCI configuration register.
371 return PciSegmentWrite8 (Address
, (UINT8
) (PciSegmentRead8 (Address
) & AndData
));
375 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
376 followed a bitwise OR with another 8-bit value.
378 Reads the 8-bit PCI configuration register specified by Address,
379 performs a bitwise AND between the read result and the value specified by AndData,
380 performs a bitwise OR between the result of the AND operation and the value specified by OrData,
381 and writes the result to the 8-bit PCI configuration register specified by Address.
382 The value written to the PCI configuration register is returned.
383 This function must guarantee that all PCI read and write operations are serialized.
385 If any reserved bits in Address are set, then ASSERT().
387 @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
388 @param AndData The value to AND with the PCI configuration register.
389 @param OrData The value to OR with the PCI configuration register.
391 @return The value written to the PCI configuration register.
396 PciSegmentAndThenOr8 (
402 return PciSegmentWrite8 (Address
, (UINT8
) ((PciSegmentRead8 (Address
) & AndData
) | OrData
));
406 Reads a bit field of a PCI configuration register.
408 Reads the bit field in an 8-bit PCI configuration register. The bit field is
409 specified by the StartBit and the EndBit. The value of the bit field is
412 If any reserved bits in Address are set, then ASSERT().
413 If StartBit is greater than 7, then ASSERT().
414 If EndBit is greater than 7, then ASSERT().
415 If EndBit is less than StartBit, then ASSERT().
417 @param Address The PCI configuration register to read.
418 @param StartBit The ordinal of the least significant bit in the bit field.
420 @param EndBit The ordinal of the most significant bit in the bit field.
423 @return The value of the bit field read from the PCI configuration register.
428 PciSegmentBitFieldRead8 (
434 return BitFieldRead8 (PciSegmentRead8 (Address
), StartBit
, EndBit
);
438 Writes a bit field to a PCI configuration register.
440 Writes Value to the bit field of the PCI configuration register. The bit
441 field is specified by the StartBit and the EndBit. All other bits in the
442 destination PCI configuration register are preserved. The new value of the
443 8-bit register is returned.
445 If any reserved bits in Address are set, then ASSERT().
446 If StartBit is greater than 7, then ASSERT().
447 If EndBit is greater than 7, then ASSERT().
448 If EndBit is less than StartBit, then ASSERT().
449 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
451 @param Address The PCI configuration register to write.
452 @param StartBit The ordinal of the least significant bit in the bit field.
454 @param EndBit The ordinal of the most significant bit in the bit field.
456 @param Value The new value of the bit field.
458 @return The value written back to the PCI configuration register.
463 PciSegmentBitFieldWrite8 (
470 return PciSegmentWrite8 (
472 BitFieldWrite8 (PciSegmentRead8 (Address
), StartBit
, EndBit
, Value
)
477 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
478 writes the result back to the bit field in the 8-bit port.
480 Reads the 8-bit PCI configuration register specified by Address, performs a
481 bitwise OR between the read result and the value specified by
482 OrData, and writes the result to the 8-bit PCI configuration register
483 specified by Address. The value written to the PCI configuration register is
484 returned. This function must guarantee that all PCI read and write operations
485 are serialized. Extra left bits in OrData are stripped.
487 If any reserved bits in Address are set, then ASSERT().
488 If StartBit is greater than 7, then ASSERT().
489 If EndBit is greater than 7, then ASSERT().
490 If EndBit is less than StartBit, then ASSERT().
491 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
493 @param Address The PCI configuration register to write.
494 @param StartBit The ordinal of the least significant bit in the bit field.
496 @param EndBit The ordinal of the most significant bit in the bit field.
498 @param OrData The value to OR with the PCI configuration register.
500 @return The value written back to the PCI configuration register.
505 PciSegmentBitFieldOr8 (
512 return PciSegmentWrite8 (
514 BitFieldOr8 (PciSegmentRead8 (Address
), StartBit
, EndBit
, OrData
)
519 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
520 AND, and writes the result back to the bit field in the 8-bit register.
522 Reads the 8-bit PCI configuration register specified by Address, performs a
523 bitwise AND between the read result and the value specified by AndData, and
524 writes the result to the 8-bit PCI configuration register specified by
525 Address. The value written to the PCI configuration register is returned.
526 This function must guarantee that all PCI read and write operations are
527 serialized. Extra left bits in AndData are stripped.
529 If any reserved bits in Address are set, then ASSERT().
530 If StartBit is greater than 7, then ASSERT().
531 If EndBit is greater than 7, then ASSERT().
532 If EndBit is less than StartBit, then ASSERT().
533 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
535 @param Address The PCI configuration register to write.
536 @param StartBit The ordinal of the least significant bit in the bit field.
538 @param EndBit The ordinal of the most significant bit in the bit field.
540 @param AndData The value to AND with the PCI configuration register.
542 @return The value written back to the PCI configuration register.
547 PciSegmentBitFieldAnd8 (
554 return PciSegmentWrite8 (
556 BitFieldAnd8 (PciSegmentRead8 (Address
), StartBit
, EndBit
, AndData
)
561 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
562 bitwise OR, and writes the result back to the bit field in the
565 Reads the 8-bit PCI configuration register specified by Address, performs a
566 bitwise AND followed by a bitwise OR between the read result and
567 the value specified by AndData, and writes the result to the 8-bit PCI
568 configuration register specified by Address. The value written to the PCI
569 configuration register is returned. This function must guarantee that all PCI
570 read and write operations are serialized. Extra left bits in both AndData and
573 If any reserved bits in Address are set, then ASSERT().
574 If StartBit is greater than 7, then ASSERT().
575 If EndBit is greater than 7, then ASSERT().
576 If EndBit is less than StartBit, then ASSERT().
577 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
578 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
580 @param Address The PCI configuration register to write.
581 @param StartBit The ordinal of the least significant bit in the bit field.
583 @param EndBit The ordinal of the most significant bit in the bit field.
585 @param AndData The value to AND with the PCI configuration register.
586 @param OrData The value to OR with the result of the AND operation.
588 @return The value written back to the PCI configuration register.
593 PciSegmentBitFieldAndThenOr8 (
601 return PciSegmentWrite8 (
603 BitFieldAndThenOr8 (PciSegmentRead8 (Address
), StartBit
, EndBit
, AndData
, OrData
)
608 Reads a 16-bit PCI configuration register.
610 Reads and returns the 16-bit PCI configuration register specified by Address.
611 This function must guarantee that all PCI read and write operations are serialized.
613 If any reserved bits in Address are set, then ASSERT().
614 If Address is not aligned on a 16-bit boundary, then ASSERT().
616 @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
618 @return The 16-bit PCI configuration register specified by Address.
627 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address
, 1);
629 return (UINT16
) DxePciSegmentLibPciRootBridgeIoReadWorker (Address
, EfiPciWidthUint16
);
633 Writes a 16-bit PCI configuration register.
635 Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
636 Value is returned. This function must guarantee that all PCI read and write operations are serialized.
638 If any reserved bits in Address are set, then ASSERT().
639 If Address is not aligned on a 16-bit boundary, then ASSERT().
641 @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
642 @param Value The value to write.
644 @return The parameter of Value.
654 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address
, 1);
656 return (UINT16
) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address
, EfiPciWidthUint16
, Value
);
660 Performs a bitwise OR of a 16-bit PCI configuration register with
663 Reads the 16-bit PCI configuration register specified by Address, performs a
664 bitwise OR between the read result and the value specified by
665 OrData, and writes the result to the 16-bit PCI configuration register
666 specified by Address. The value written to the PCI configuration register is
667 returned. This function must guarantee that all PCI read and write operations
670 If any reserved bits in Address are set, then ASSERT().
671 If Address is not aligned on a 16-bit boundary, then ASSERT().
673 @param Address The address that encodes the PCI Segment, Bus, Device, Function and
675 @param OrData The value to OR with the PCI configuration register.
677 @return The value written back to the PCI configuration register.
687 return PciSegmentWrite16 (Address
, (UINT16
) (PciSegmentRead16 (Address
) | OrData
));
691 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
693 Reads the 16-bit PCI configuration register specified by Address,
694 performs a bitwise AND between the read result and the value specified by AndData,
695 and writes the result to the 16-bit PCI configuration register specified by Address.
696 The value written to the PCI configuration register is returned.
697 This function must guarantee that all PCI read and write operations are serialized.
699 If any reserved bits in Address are set, then ASSERT().
700 If Address is not aligned on a 16-bit boundary, then ASSERT().
702 @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
703 @param AndData The value to AND with the PCI configuration register.
705 @return The value written to the PCI configuration register.
715 return PciSegmentWrite16 (Address
, (UINT16
) (PciSegmentRead16 (Address
) & AndData
));
719 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
720 followed a bitwise OR with another 16-bit value.
722 Reads the 16-bit PCI configuration register specified by Address,
723 performs a bitwise AND between the read result and the value specified by AndData,
724 performs a bitwise OR between the result of the AND operation and the value specified by OrData,
725 and writes the result to the 16-bit PCI configuration register specified by Address.
726 The value written to the PCI configuration register is returned.
727 This function must guarantee that all PCI read and write operations are serialized.
729 If any reserved bits in Address are set, then ASSERT().
730 If Address is not aligned on a 16-bit boundary, then ASSERT().
732 @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
733 @param AndData The value to AND with the PCI configuration register.
734 @param OrData The value to OR with the PCI configuration register.
736 @return The value written to the PCI configuration register.
741 PciSegmentAndThenOr16 (
747 return PciSegmentWrite16 (Address
, (UINT16
) ((PciSegmentRead16 (Address
) & AndData
) | OrData
));
751 Reads a bit field of a PCI configuration register.
753 Reads the bit field in a 16-bit PCI configuration register. The bit field is
754 specified by the StartBit and the EndBit. The value of the bit field is
757 If any reserved bits in Address are set, then ASSERT().
758 If Address is not aligned on a 16-bit boundary, then ASSERT().
759 If StartBit is greater than 15, then ASSERT().
760 If EndBit is greater than 15, then ASSERT().
761 If EndBit is less than StartBit, then ASSERT().
763 @param Address The PCI configuration register to read.
764 @param StartBit The ordinal of the least significant bit in the bit field.
766 @param EndBit The ordinal of the most significant bit in the bit field.
769 @return The value of the bit field read from the PCI configuration register.
774 PciSegmentBitFieldRead16 (
780 return BitFieldRead16 (PciSegmentRead16 (Address
), StartBit
, EndBit
);
784 Writes a bit field to a PCI configuration register.
786 Writes Value to the bit field of the PCI configuration register. The bit
787 field is specified by the StartBit and the EndBit. All other bits in the
788 destination PCI configuration register are preserved. The new value of the
789 16-bit register is returned.
791 If any reserved bits in Address are set, then ASSERT().
792 If Address is not aligned on a 16-bit boundary, then ASSERT().
793 If StartBit is greater than 15, then ASSERT().
794 If EndBit is greater than 15, then ASSERT().
795 If EndBit is less than StartBit, then ASSERT().
796 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
798 @param Address The PCI configuration register to write.
799 @param StartBit The ordinal of the least significant bit in the bit field.
801 @param EndBit The ordinal of the most significant bit in the bit field.
803 @param Value The new value of the bit field.
805 @return The value written back to the PCI configuration register.
810 PciSegmentBitFieldWrite16 (
817 return PciSegmentWrite16 (
819 BitFieldWrite16 (PciSegmentRead16 (Address
), StartBit
, EndBit
, Value
)
824 Reads the 16-bit PCI configuration register specified by Address,
825 performs a bitwise OR between the read result and the value specified by OrData,
826 and writes the result to the 16-bit PCI configuration register specified by Address.
828 If any reserved bits in Address are set, then ASSERT().
829 If Address is not aligned on a 16-bit boundary, then ASSERT().
830 If StartBit is greater than 15, then ASSERT().
831 If EndBit is greater than 15, then ASSERT().
832 If EndBit is less than StartBit, then ASSERT().
833 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
835 @param Address The PCI configuration register to write.
836 @param StartBit The ordinal of the least significant bit in the bit field.
838 @param EndBit The ordinal of the most significant bit in the bit field.
840 @param OrData The value to OR with the PCI configuration register.
842 @return The value written back to the PCI configuration register.
847 PciSegmentBitFieldOr16 (
854 return PciSegmentWrite16 (
856 BitFieldOr16 (PciSegmentRead16 (Address
), StartBit
, EndBit
, OrData
)
861 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,
862 and writes the result back to the bit field in the 16-bit port.
864 Reads the 16-bit PCI configuration register specified by Address,
865 performs a bitwise OR between the read result and the value specified by OrData,
866 and writes the result to the 16-bit PCI configuration register specified by Address.
867 The value written to the PCI configuration register is returned.
868 This function must guarantee that all PCI read and write operations are serialized.
869 Extra left bits in OrData are stripped.
871 If any reserved bits in Address are set, then ASSERT().
872 If Address is not aligned on a 16-bit boundary, then ASSERT().
873 If StartBit is greater than 7, then ASSERT().
874 If EndBit is greater than 7, then ASSERT().
875 If EndBit is less than StartBit, then ASSERT().
876 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
878 @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
879 @param StartBit The ordinal of the least significant bit in the bit field.
880 The ordinal of the least significant bit in a byte is bit 0.
881 @param EndBit The ordinal of the most significant bit in the bit field.
882 The ordinal of the most significant bit in a byte is bit 7.
883 @param AndData The value to AND with the read value from the PCI configuration register.
885 @return The value written to the PCI configuration register.
890 PciSegmentBitFieldAnd16 (
897 return PciSegmentWrite16 (
899 BitFieldAnd16 (PciSegmentRead16 (Address
), StartBit
, EndBit
, AndData
)
904 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
905 bitwise OR, and writes the result back to the bit field in the
908 Reads the 16-bit PCI configuration register specified by Address, performs a
909 bitwise AND followed by a bitwise OR between the read result and
910 the value specified by AndData, and writes the result to the 16-bit PCI
911 configuration register specified by Address. The value written to the PCI
912 configuration register is returned. This function must guarantee that all PCI
913 read and write operations are serialized. Extra left bits in both AndData and
916 If any reserved bits in Address are set, then ASSERT().
917 If StartBit is greater than 15, then ASSERT().
918 If EndBit is greater than 15, then ASSERT().
919 If EndBit is less than StartBit, then ASSERT().
920 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
921 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
923 @param Address The PCI configuration register to write.
924 @param StartBit The ordinal of the least significant bit in the bit field.
926 @param EndBit The ordinal of the most significant bit in the bit field.
928 @param AndData The value to AND with the PCI configuration register.
929 @param OrData The value to OR with the result of the AND operation.
931 @return The value written back to the PCI configuration register.
936 PciSegmentBitFieldAndThenOr16 (
944 return PciSegmentWrite16 (
946 BitFieldAndThenOr16 (PciSegmentRead16 (Address
), StartBit
, EndBit
, AndData
, OrData
)
951 Reads a 32-bit PCI configuration register.
953 Reads and returns the 32-bit PCI configuration register specified by Address.
954 This function must guarantee that all PCI read and write operations are serialized.
956 If any reserved bits in Address are set, then ASSERT().
957 If Address is not aligned on a 32-bit boundary, then ASSERT().
959 @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
961 @return The 32-bit PCI configuration register specified by Address.
970 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address
, 3);
972 return DxePciSegmentLibPciRootBridgeIoReadWorker (Address
, EfiPciWidthUint32
);
976 Writes a 32-bit PCI configuration register.
978 Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
979 Value is returned. This function must guarantee that all PCI read and write operations are serialized.
981 If any reserved bits in Address are set, then ASSERT().
982 If Address is not aligned on a 32-bit boundary, then ASSERT().
984 @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
985 @param Value The value to write.
987 @return The parameter of Value.
997 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address
, 3);
999 return DxePciSegmentLibPciRootBridgeIoWriteWorker (Address
, EfiPciWidthUint32
, Value
);
1003 Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
1005 Reads the 32-bit PCI configuration register specified by Address,
1006 performs a bitwise OR between the read result and the value specified by OrData,
1007 and writes the result to the 32-bit PCI configuration register specified by Address.
1008 The value written to the PCI configuration register is returned.
1009 This function must guarantee that all PCI read and write operations are serialized.
1011 If any reserved bits in Address are set, then ASSERT().
1012 If Address is not aligned on a 32-bit boundary, then ASSERT().
1014 @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
1015 @param OrData The value to OR with the PCI configuration register.
1017 @return The value written to the PCI configuration register.
1027 return PciSegmentWrite32 (Address
, PciSegmentRead32 (Address
) | OrData
);
1031 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
1033 Reads the 32-bit PCI configuration register specified by Address,
1034 performs a bitwise AND between the read result and the value specified by AndData,
1035 and writes the result to the 32-bit PCI configuration register specified by Address.
1036 The value written to the PCI configuration register is returned.
1037 This function must guarantee that all PCI read and write operations are serialized.
1039 If any reserved bits in Address are set, then ASSERT().
1040 If Address is not aligned on a 32-bit boundary, then ASSERT().
1042 @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
1043 @param AndData The value to AND with the PCI configuration register.
1045 @return The value written to the PCI configuration register.
1055 return PciSegmentWrite32 (Address
, PciSegmentRead32 (Address
) & AndData
);
1059 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
1060 followed a bitwise OR with another 32-bit value.
1062 Reads the 32-bit PCI configuration register specified by Address,
1063 performs a bitwise AND between the read result and the value specified by AndData,
1064 performs a bitwise OR between the result of the AND operation and the value specified by OrData,
1065 and writes the result to the 32-bit PCI configuration register specified by Address.
1066 The value written to the PCI configuration register is returned.
1067 This function must guarantee that all PCI read and write operations are serialized.
1069 If any reserved bits in Address are set, then ASSERT().
1070 If Address is not aligned on a 32-bit boundary, then ASSERT().
1072 @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
1073 @param AndData The value to AND with the PCI configuration register.
1074 @param OrData The value to OR with the PCI configuration register.
1076 @return The value written to the PCI configuration register.
1081 PciSegmentAndThenOr32 (
1087 return PciSegmentWrite32 (Address
, (PciSegmentRead32 (Address
) & AndData
) | OrData
);
1091 Reads a bit field of a PCI configuration register.
1093 Reads the bit field in a 32-bit PCI configuration register. The bit field is
1094 specified by the StartBit and the EndBit. The value of the bit field is
1097 If any reserved bits in Address are set, then ASSERT().
1098 If Address is not aligned on a 32-bit boundary, then ASSERT().
1099 If StartBit is greater than 31, then ASSERT().
1100 If EndBit is greater than 31, then ASSERT().
1101 If EndBit is less than StartBit, then ASSERT().
1103 @param Address The PCI configuration register to read.
1104 @param StartBit The ordinal of the least significant bit in the bit field.
1106 @param EndBit The ordinal of the most significant bit in the bit field.
1109 @return The value of the bit field read from the PCI configuration register.
1114 PciSegmentBitFieldRead32 (
1120 return BitFieldRead32 (PciSegmentRead32 (Address
), StartBit
, EndBit
);
1124 Writes a bit field to a PCI configuration register.
1126 Writes Value to the bit field of the PCI configuration register. The bit
1127 field is specified by the StartBit and the EndBit. All other bits in the
1128 destination PCI configuration register are preserved. The new value of the
1129 32-bit register is returned.
1131 If any reserved bits in Address are set, then ASSERT().
1132 If Address is not aligned on a 32-bit boundary, then ASSERT().
1133 If StartBit is greater than 31, then ASSERT().
1134 If EndBit is greater than 31, then ASSERT().
1135 If EndBit is less than StartBit, then ASSERT().
1136 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1138 @param Address The PCI configuration register to write.
1139 @param StartBit The ordinal of the least significant bit in the bit field.
1141 @param EndBit The ordinal of the most significant bit in the bit field.
1143 @param Value The new value of the bit field.
1145 @return The value written back to the PCI configuration register.
1150 PciSegmentBitFieldWrite32 (
1157 return PciSegmentWrite32 (
1159 BitFieldWrite32 (PciSegmentRead32 (Address
), StartBit
, EndBit
, Value
)
1164 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1165 writes the result back to the bit field in the 32-bit port.
1167 Reads the 32-bit PCI configuration register specified by Address, performs a
1168 bitwise OR between the read result and the value specified by
1169 OrData, and writes the result to the 32-bit PCI configuration register
1170 specified by Address. The value written to the PCI configuration register is
1171 returned. This function must guarantee that all PCI read and write operations
1172 are serialized. Extra left bits in OrData are stripped.
1174 If any reserved bits in Address are set, then ASSERT().
1175 If StartBit is greater than 31, then ASSERT().
1176 If EndBit is greater than 31, then ASSERT().
1177 If EndBit is less than StartBit, then ASSERT().
1178 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1180 @param Address The PCI configuration register to write.
1181 @param StartBit The ordinal of the least significant bit in the bit field.
1183 @param EndBit The ordinal of the most significant bit in the bit field.
1185 @param OrData The value to OR with the PCI configuration register.
1187 @return The value written back to the PCI configuration register.
1192 PciSegmentBitFieldOr32 (
1199 return PciSegmentWrite32 (
1201 BitFieldOr32 (PciSegmentRead32 (Address
), StartBit
, EndBit
, OrData
)
1206 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1207 AND, and writes the result back to the bit field in the 32-bit register.
1210 Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
1211 AND between the read result and the value specified by AndData, and writes the result
1212 to the 32-bit PCI configuration register specified by Address. The value written to
1213 the PCI configuration register is returned. This function must guarantee that all PCI
1214 read and write operations are serialized. Extra left bits in AndData are stripped.
1215 If any reserved bits in Address are set, then ASSERT().
1216 If Address is not aligned on a 32-bit boundary, then ASSERT().
1217 If StartBit is greater than 31, then ASSERT().
1218 If EndBit is greater than 31, then ASSERT().
1219 If EndBit is less than StartBit, then ASSERT().
1220 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1222 @param Address The PCI configuration register to write.
1223 @param StartBit The ordinal of the least significant bit in the bit field.
1225 @param EndBit The ordinal of the most significant bit in the bit field.
1227 @param AndData The value to AND with the PCI configuration register.
1229 @return The value written back to the PCI configuration register.
1234 PciSegmentBitFieldAnd32 (
1241 return PciSegmentWrite32 (
1243 BitFieldAnd32 (PciSegmentRead32 (Address
), StartBit
, EndBit
, AndData
)
1248 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1249 bitwise OR, and writes the result back to the bit field in the
1252 Reads the 32-bit PCI configuration register specified by Address, performs a
1253 bitwise AND followed by a bitwise OR between the read result and
1254 the value specified by AndData, and writes the result to the 32-bit PCI
1255 configuration register specified by Address. The value written to the PCI
1256 configuration register is returned. This function must guarantee that all PCI
1257 read and write operations are serialized. Extra left bits in both AndData and
1258 OrData are stripped.
1260 If any reserved bits in Address are set, then ASSERT().
1261 If StartBit is greater than 31, then ASSERT().
1262 If EndBit is greater than 31, then ASSERT().
1263 If EndBit is less than StartBit, then ASSERT().
1264 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1265 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1267 @param Address The PCI configuration register to write.
1268 @param StartBit The ordinal of the least significant bit in the bit field.
1270 @param EndBit The ordinal of the most significant bit in the bit field.
1272 @param AndData The value to AND with the PCI configuration register.
1273 @param OrData The value to OR with the result of the AND operation.
1275 @return The value written back to the PCI configuration register.
1280 PciSegmentBitFieldAndThenOr32 (
1288 return PciSegmentWrite32 (
1290 BitFieldAndThenOr32 (PciSegmentRead32 (Address
), StartBit
, EndBit
, AndData
, OrData
)
1295 Reads a range of PCI configuration registers into a caller supplied buffer.
1297 Reads the range of PCI configuration registers specified by StartAddress and
1298 Size into the buffer specified by Buffer. This function only allows the PCI
1299 configuration registers from a single PCI function to be read. Size is
1300 returned. When possible 32-bit PCI configuration read cycles are used to read
1301 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1302 and 16-bit PCI configuration read cycles may be used at the beginning and the
1305 If any reserved bits in StartAddress are set, then ASSERT().
1306 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1307 If Size > 0 and Buffer is NULL, then ASSERT().
1309 @param StartAddress The starting address that encodes the PCI Segment, Bus, Device,
1310 Function and Register.
1311 @param Size The size in bytes of the transfer.
1312 @param Buffer The pointer to a buffer receiving the data read.
1319 PciSegmentReadBuffer (
1320 IN UINT64 StartAddress
,
1327 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress
, 0);
1328 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1334 ASSERT (Buffer
!= NULL
);
1337 // Save Size for return
1341 if ((StartAddress
& BIT0
) != 0) {
1343 // Read a byte if StartAddress is byte aligned
1345 *(volatile UINT8
*)Buffer
= PciSegmentRead8 (StartAddress
);
1346 StartAddress
+= sizeof (UINT8
);
1347 Size
-= sizeof (UINT8
);
1348 Buffer
= (UINT8
*)Buffer
+ 1;
1351 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1353 // Read a word if StartAddress is word aligned
1355 WriteUnaligned16 (Buffer
, PciSegmentRead16 (StartAddress
));
1356 StartAddress
+= sizeof (UINT16
);
1357 Size
-= sizeof (UINT16
);
1358 Buffer
= (UINT16
*)Buffer
+ 1;
1361 while (Size
>= sizeof (UINT32
)) {
1363 // Read as many double words as possible
1365 WriteUnaligned32 (Buffer
, PciSegmentRead32 (StartAddress
));
1366 StartAddress
+= sizeof (UINT32
);
1367 Size
-= sizeof (UINT32
);
1368 Buffer
= (UINT32
*)Buffer
+ 1;
1371 if (Size
>= sizeof (UINT16
)) {
1373 // Read the last remaining word if exist
1375 WriteUnaligned16 (Buffer
, PciSegmentRead16 (StartAddress
));
1376 StartAddress
+= sizeof (UINT16
);
1377 Size
-= sizeof (UINT16
);
1378 Buffer
= (UINT16
*)Buffer
+ 1;
1381 if (Size
>= sizeof (UINT8
)) {
1383 // Read the last remaining byte if exist
1385 *(volatile UINT8
*)Buffer
= PciSegmentRead8 (StartAddress
);
1392 Copies the data in a caller supplied buffer to a specified range of PCI
1393 configuration space.
1395 Writes the range of PCI configuration registers specified by StartAddress and
1396 Size from the buffer specified by Buffer. This function only allows the PCI
1397 configuration registers from a single PCI function to be written. Size is
1398 returned. When possible 32-bit PCI configuration write cycles are used to
1399 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1400 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1401 and the end of the range.
1403 If any reserved bits in StartAddress are set, then ASSERT().
1404 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1405 If Size > 0 and Buffer is NULL, then ASSERT().
1407 @param StartAddress The starting address that encodes the PCI Segment, Bus, Device,
1408 Function and Register.
1409 @param Size The size in bytes of the transfer.
1410 @param Buffer The pointer to a buffer containing the data to write.
1412 @return The parameter of Size.
1417 PciSegmentWriteBuffer (
1418 IN UINT64 StartAddress
,
1425 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress
, 0);
1426 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1432 ASSERT (Buffer
!= NULL
);
1435 // Save Size for return
1439 if ((StartAddress
& BIT0
) != 0) {
1441 // Write a byte if StartAddress is byte aligned
1443 PciSegmentWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1444 StartAddress
+= sizeof (UINT8
);
1445 Size
-= sizeof (UINT8
);
1446 Buffer
= (UINT8
*)Buffer
+ 1;
1449 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1451 // Write a word if StartAddress is word aligned
1453 PciSegmentWrite16 (StartAddress
, ReadUnaligned16 (Buffer
));
1454 StartAddress
+= sizeof (UINT16
);
1455 Size
-= sizeof (UINT16
);
1456 Buffer
= (UINT16
*)Buffer
+ 1;
1459 while (Size
>= sizeof (UINT32
)) {
1461 // Write as many double words as possible
1463 PciSegmentWrite32 (StartAddress
, ReadUnaligned32 (Buffer
));
1464 StartAddress
+= sizeof (UINT32
);
1465 Size
-= sizeof (UINT32
);
1466 Buffer
= (UINT32
*)Buffer
+ 1;
1469 if (Size
>= sizeof (UINT16
)) {
1471 // Write the last remaining word if exist
1473 PciSegmentWrite16 (StartAddress
, ReadUnaligned16 (Buffer
));
1474 StartAddress
+= sizeof (UINT16
);
1475 Size
-= sizeof (UINT16
);
1476 Buffer
= (UINT16
*)Buffer
+ 1;
1479 if (Size
>= sizeof (UINT8
)) {
1481 // Write the last remaining byte if exist
1483 PciSegmentWrite8 (StartAddress
, *(UINT8
*)Buffer
);