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2 // IPF Processor Defines for assembly code
5 // This file is included by assembly files as well. The assmber can NOT deal
6 // with /* */ commnets this is why this file is commented not following the
9 //Copyright (c) 2006, Intel Corporation
10 //All rights reserved. This program and the accompanying materials
11 //are licensed and made available under the terms and conditions of the BSD License
12 //which accompanies this distribution. The full text of the license may be found at
13 //http://opensource.org/licenses/bsd-license.php
15 //THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 //WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 //Module Name: IpfDefines.h
26 // IPI DElivery Methods
28 #define IPI_INT_DELIVERY 0x0
29 #define IPI_PMI_DELIVERY 0x2
30 #define IPI_NMI_DELIVERY 0x4
31 #define IPI_INIT_DELIVERY 0x5
32 #define IPI_ExtINT_DELIVERY 0x7
35 // Define Itanium-based system registers.
37 // Define Itanium-based system register bit field offsets.
39 // Processor Status Register (PSR) Bit positions
51 // PSR bits 6-12 reserved (must be zero)
54 #define PSR_MBZ0_V 0x1ffUL L
60 #define PSR_IC_MASK (1 << 13)
64 #define PSR_MBZ1_V 0x1UL L
78 // PSR bits 28-31 reserved (must be zero)
81 #define PSR_MBZ2_V 0xfUL L
91 #define PSR_IT_MASK 0x1000000000
102 // PSR bits 45-63 reserved (must be zero)
105 #define PSR_MBZ3_V 0xfffffUL L
108 // Floating Point Status Register (FPSR) Bit positions
121 // Status Field 0 - Controls
130 // Status Field 0 - Flags
140 // Status Field 1 - Controls
142 #define FPSR1_FTZ0 19
143 #define FPSR1_WRE0 20
149 // Status Field 1 - Flags
159 // Status Field 2 - Controls
161 #define FPSR2_FTZ0 32
162 #define FPSR2_WRE0 33
168 // Status Field 2 - Flags
178 // Status Field 3 - Controls
180 #define FPSR3_FTZ0 45
181 #define FPSR3_WRE0 46
187 // Status Field 0 - Flags
197 // FPSR bits 58-63 Reserved -- Must be zero
200 #define FPSR_MBZ0_V 0x3fUL L
203 // For setting up FPSR on kernel entry
204 // All traps are disabled.
206 #define FPSR_FOR_KERNEL 0x3f
208 #define FP_REG_SIZE 16 // 16 byte spill size
209 #define HIGHFP_REGS_LENGTH (96 * 16)
212 // Define hardware Task Priority Register (TPR)
217 #define TPR_MIC 4 // Bits 0 - 3 ignored
218 #define TPR_MIC_LEN 4
219 #define TPR_MMI 16 // Mask Maskable Interrupt
221 // Define hardware Interrupt Status Register (ISR)
227 #define ISR_CODE_LEN 16
228 #define ISR_CODE_MASK 0xFFFF
229 #define ISR_IA_VECTOR 16
230 #define ISR_IA_VECTOR_LEN 8
232 #define ISR_MBZ0_V 0xff
245 #define ISR_MBZ2_V 0xfffff
250 // For General exceptions: ISR{3:0}
252 #define ISR_ILLEGAL_OP 0 // Illegal operation fault
253 #define ISR_PRIV_OP 1 // Privileged operation fault
254 #define ISR_PRIV_REG 2 // Privileged register fauls
255 #define ISR_RESVD_REG 3 // Reserved register/field flt
256 #define ISR_ILLEGAL_ISA 4 // Disabled instruction set transition fault
258 // Define hardware Default Control Register (DCR)
267 #define DCR_MBZ0_V 0xf
275 #define DCR_DEFER_ALL 0x7f00
277 #define DCR_MBZ1_V 0xffffffffffffUL L
280 // Define hardware RSE Configuration Register
282 // RS Configuration (RSC) bit field positions
288 #define RSC_MBZ0_V 0x3ff
289 #define RSC_LOADRS 16
290 #define RSC_LOADRS_LEN 14
292 #define RSC_MBZ1_V 0x3ffffffffUL L
297 #define RSC_MODE_LY (0x0) // Lazy
298 #define RSC_MODE_SI (0x1) // Store intensive
299 #define RSC_MODE_LI (0x2) // Load intensive
300 #define RSC_MODE_EA (0x3) // Eager
302 // RSC Endian bit values
304 #define RSC_BE_LITTLE 0
308 // Define Interruption Function State (IFS) Register
310 // IFS bit field positions
313 #define IFS_IFM_LEN 38
315 #define IFS_MBZ0_V 0x1ffffff
320 // IFS is valid when IFS_V = IFS_VALID
325 // Define Page Table Address (PTA)
330 #define PTA_SIZE_LEN 6
334 // Define Region Register (RR)
337 // RR bit field positions
344 #define RR_RID_LEN 24
348 // SAL uses region register 0 and RID of 1000
350 #define SAL_RID 0x1000
351 #define SAL_RR_REG 0x0
355 // Total number of region registers
360 // Define Protection Key Register (PKR)
362 // PKR bit field positions
370 #define PKR_KEY_LEN 24
373 #define PKR_VALID (1 << PKR_V)
376 // Number of protection key registers
381 // Define Interruption TLB Insertion register (ITIR)
384 // Define Translation Insertion Format (TR)
386 // PTE0 bit field positions
401 // ITIR bit field positions
405 #define ITIR_PS_LEN 6
407 #define ITIR_KEY_LEN 24
409 #define ITIR_MBZ1_LEN 16
411 #define ITIR_PPN_LEN 15
414 #define ATTR_IPAGE 0x661 // Access Rights = RWX (bits 11-9=011), PL 0(8-7=0)
415 #define ATTR_DEF_BITS 0x661 // Access Rights = RWX (bits 11-9=010), PL 0(8-7=0)
416 // Dirty (bit 6=1), Accessed (bit 5=1),
417 // MA WB (bits 4-2=000), Present (bit 0=1)
419 // Memory access rights
421 #define AR_UR_KR 0x0 // user/kernel read
422 #define AR_URX_KRX 0x1 // user/kernel read and execute
423 #define AR_URW_KRW 0x2 // user/kernel read & write
424 #define AR_URWX_KRWX 0x3 // user/kernel read,write&execute
425 #define AR_UR_KRW 0x4 // user read/kernel read,write
426 #define AR_URX_KRWX 0x5 // user read/execute, kernel all
427 #define AR_URWX_KRW 0x6 // user all, kernel read & write
428 #define AR_UX_KRX 0x7 // user execute only, kernel read and execute
430 // Memory attribute values
433 // The next 4 are all cached, non-sequential & speculative, coherent
435 #define MA_WBU 0x0 // Write back, unordered
437 // The next 3 are all non-cached, sequential & non-speculative
439 #define MA_UC 0x4 // Non-coalescing, sequential & non-speculative
440 #define MA_UCE 0x5 // Non-coalescing, sequential, non-speculative
441 // & fetchadd exported
443 #define MA_WC 0x6 // Non-cached, Coalescing, non-seq., spec.
444 #define MA_NAT 0xf // NaT page
446 // Definition of the offset of TRAP/INTERRUPT/FAULT handlers from the
447 // base of IVA (Interruption Vector Address)
449 #define IVT_SIZE 0x8000
450 #define EXTRA_ALIGNMENT 0x1000
452 #define OFF_VHPTFLT 0x0000 // VHPT Translation fault
453 #define OFF_ITLBFLT 0x0400 // Instruction TLB fault
454 #define OFF_DTLBFLT 0x0800 // Data TLB fault
455 #define OFF_ALTITLBFLT 0x0C00 // Alternate ITLB fault
456 #define OFF_ALTDTLBFLT 0x1000 // Alternate DTLB fault
457 #define OFF_NESTEDTLBFLT 0x1400 // Nested TLB fault
458 #define OFF_IKEYMISSFLT 0x1800 // Inst Key Miss fault
459 #define OFF_DKEYMISSFLT 0x1C00 // Data Key Miss fault
460 #define OFF_DIRTYBITFLT 0x2000 // Dirty-Bit fault
461 #define OFF_IACCESSBITFLT 0x2400 // Inst Access-Bit fault
462 #define OFF_DACCESSBITFLT 0x2800 // Data Access-Bit fault
463 #define OFF_BREAKFLT 0x2C00 // Break Inst fault
464 #define OFF_EXTINT 0x3000 // External Interrupt
466 // Offset 0x3400 to 0x0x4C00 are reserved
468 #define OFF_PAGENOTPFLT 0x5000 // Page Not Present fault
469 #define OFF_KEYPERMFLT 0x5100 // Key Permission fault
470 #define OFF_IACCESSRTFLT 0x5200 // Inst Access-Rights flt
471 #define OFF_DACCESSRTFLT 0x5300 // Data Access-Rights fault
472 #define OFF_GPFLT 0x5400 // General Exception fault
473 #define OFF_FPDISFLT 0x5500 // Disable-FP fault
474 #define OFF_NATFLT 0x5600 // NAT Consumption fault
475 #define OFF_SPECLNFLT 0x5700 // Speculation fault
476 #define OFF_DBGFLT 0x5900 // Debug fault
477 #define OFF_ALIGNFLT 0x5A00 // Unaligned Reference fault
478 #define OFF_LOCKDREFFLT 0x5B00 // Locked Data Reference fault
479 #define OFF_FPFLT 0x5C00 // Floating Point fault
480 #define OFF_FPTRAP 0x5D00 // Floating Point Trap
481 #define OFF_LOPRIVTRAP 0x5E00 // Lower-Privilege Transfer Trap
482 #define OFF_TAKENBRTRAP 0x5F00 // Taken Branch Trap
483 #define OFF_SSTEPTRAP 0x6000 // Single Step Trap
485 // Offset 0x6100 to 0x6800 are reserved
487 #define OFF_IA32EXCEPTN 0x6900 // iA32 Exception
488 #define OFF_IA32INTERCEPT 0x6A00 // iA32 Intercept
489 #define OFF_IA32INT 0x6B00 // iA32 Interrupt
490 #define NUMBER_OF_VECTORS 0x100
498 // Instruction set (IS) bits
504 // RSC while in kernel: enabled, little endian, PL = 0, eager mode
506 #define RSC_KERNEL ((RSC_MODE_EA << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))
509 // Lazy RSC in kernel: enabled, little endian, pl = 0, lazy mode
511 #define RSC_KERNEL_LAZ ((RSC_MODE_LY << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))
514 // RSE disabled: disabled, PL = 0, little endian, eager mode
516 #define RSC_KERNEL_DISABLED ((RSC_MODE_LY << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))
518 #define NAT_BITS_PER_RNAT_REG 63
521 // Macros for generating PTE0 and PTE1 value
523 #define PTE0(ed, ppn12_47, ar, pl, d, a, ma, p) \
524 ( ( ed << PTE0_ED ) | \
525 ( ppn12_47 << PTE0_PPN ) | \
526 ( ar << PTE0_AR ) | \
527 ( pl << PTE0_PL ) | \
530 ( ma << PTE0_MA ) | \
534 #define ITIR(ppn48_63, key, ps) \
535 ( ( ps << ITIR_PS ) | \
536 ( key << ITIR_KEY ) | \
537 ( ppn48_63 << ITIR_PPN ) \
541 // Macro to generate mask value from bit position. The result is a
544 #define BITMASK(bp, value) (value << bp)
546 #define BUNDLE_SIZE 16
547 #define SPURIOUS_INT 0xF
549 #define FAST_DISABLE_INTERRUPTS rsm BITMASK (PSR_I, 1);;
551 #define FAST_ENABLE_INTERRUPTS ssm BITMASK (PSR_I, 1);;