2 Main SAL API's defined in SAL 3.0 specification.
4 Copyright (c) 2006, Intel Corporation
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
22 // Table 2-2 of Intel Itanium Processor Family System Abstraction Layer Specification December 2003
24 #define EFI_SAL_FIT_FIT_HEADER_TYPE 0x00
25 #define EFI_SAL_FIT_PAL_B_TYPE 0x01
27 // type from 0x02 to 0x0E is reserved.
29 #define EFI_SAL_FIT_PAL_A_TYPE 0x0F
31 // OEM-defined type range is from 0x10 to 0x7E. Here we defined the PEI_CORE type as 0x10
33 #define EFI_SAL_FIT_PEI_CORE_TYPE 0x10
34 #define EFI_SAL_FIT_UNUSED_TYPE 0x7F
39 typedef UINTN EFI_SAL_STATUS
;
41 #define EFI_SAL_SUCCESS ((EFI_SAL_STATUS) 0)
42 #define EFI_SAL_MORE_RECORDS ((EFI_SAL_STATUS) 3)
43 #define EFI_SAL_NOT_IMPLEMENTED ((EFI_SAL_STATUS) - 1)
44 #define EFI_SAL_INVALID_ARGUMENT ((EFI_SAL_STATUS) - 2)
45 #define EFI_SAL_ERROR ((EFI_SAL_STATUS) - 3)
46 #define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)
47 #define EFI_SAL_NO_INFORMATION ((EFI_SAL_STATUS) - 5)
48 #define EFI_SAL_NOT_ENOUGH_SCRATCH ((EFI_SAL_STATUS) - 9)
51 // Return values from SAL
54 EFI_SAL_STATUS Status
; // register r8
61 // Delivery Mode of IPF CPU.
64 EFI_DELIVERY_MODE_INT
,
65 EFI_DELIVERY_MODE_MPreserved1
,
66 EFI_DELIVERY_MODE_PMI
,
67 EFI_DELIVERY_MODE_MPreserved2
,
68 EFI_DELIVERY_MODE_NMI
,
69 EFI_DELIVERY_MODE_INIT
,
70 EFI_DELIVERY_MODE_MPreserved3
,
71 EFI_DELIVERY_MODE_ExtINT
74 typedef SAL_RETURN_REGS (EFIAPI
*SAL_PROC
)
87 // SAL Procedure FunctionId definition
89 #define EFI_SAL_SET_VECTORS 0x01000000
90 #define EFI_SAL_GET_STATE_INFO 0x01000001
91 #define EFI_SAL_GET_STATE_INFO_SIZE 0x01000002
92 #define EFI_SAL_CLEAR_STATE_INFO 0x01000003
93 #define EFI_SAL_MC_RENDEZ 0x01000004
94 #define EFI_SAL_MC_SET_PARAMS 0x01000005
95 #define EFI_SAL_REGISTER_PHYSICAL_ADDR 0x01000006
96 #define EFI_SAL_CACHE_FLUSH 0x01000008
97 #define EFI_SAL_CACHE_INIT 0x01000009
98 #define EFI_SAL_PCI_CONFIG_READ 0x01000010
99 #define EFI_SAL_PCI_CONFIG_WRITE 0x01000011
100 #define EFI_SAL_FREQ_BASE 0x01000012
101 #define EFI_SAL_PHYSICAL_ID_INFO 0x01000013
102 #define EFI_SAL_UPDATE_PAL 0x01000020
104 #define EFI_SAL_FUNCTION_ID_MASK 0x0000ffff
105 #define EFI_SAL_MAX_SAL_FUNCTION_ID 0x00000021
108 // SAL Procedure parameter definitions
109 // Not much point in using typedefs or enums because all params
110 // are UINT64 and the entry point is common
112 // EFI_SAL_SET_VECTORS
114 #define EFI_SAL_SET_MCA_VECTOR 0x0
115 #define EFI_SAL_SET_INIT_VECTOR 0x1
116 #define EFI_SAL_SET_BOOT_RENDEZ_VECTOR 0x2
120 UINT64 ChecksumValid
: 1;
121 UINT64 Reserved1
: 7;
122 UINT64 ByteChecksum
: 8;
123 UINT64 Reserved2
: 16;
124 } SAL_SET_VECTORS_CS_N
;
127 // EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE,
128 // EFI_SAL_CLEAR_STATE_INFO
130 #define EFI_SAL_MCA_STATE_INFO 0x0
131 #define EFI_SAL_INIT_STATE_INFO 0x1
132 #define EFI_SAL_CMC_STATE_INFO 0x2
133 #define EFI_SAL_CP_STATE_INFO 0x3
136 // EFI_SAL_MC_SET_PARAMS
138 #define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1
139 #define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2
140 #define EFI_SAL_MC_SET_CPE_PARAM 0x3
142 #define EFI_SAL_MC_SET_INTR_PARAM 0x1
143 #define EFI_SAL_MC_SET_MEM_PARAM 0x2
146 // EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR
148 #define EFI_SAL_REGISTER_PAL_ADDR 0x0
151 // EFI_SAL_CACHE_FLUSH
153 #define EFI_SAL_FLUSH_I_CACHE 0x01
154 #define EFI_SAL_FLUSH_D_CACHE 0x02
155 #define EFI_SAL_FLUSH_BOTH_CACHE 0x03
156 #define EFI_SAL_FLUSH_MAKE_COHERENT 0x04
159 // EFI_SAL_PCI_CONFIG_READ, EFI_SAL_PCI_CONFIG_WRITE
161 #define EFI_SAL_PCI_CONFIG_ONE_BYTE 0x1
162 #define EFI_SAL_PCI_CONFIG_TWO_BYTES 0x2
163 #define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4
171 UINT64 Reserved
: 32;
177 #define EFI_SAL_CPU_INPUT_FREQ_BASE 0x0
178 #define EFI_SAL_PLATFORM_IT_FREQ_BASE 0x1
179 #define EFI_SAL_PLATFORM_RTC_FREQ_BASE 0x2
182 // EFI_SAL_UPDATE_PAL
184 #define EFI_SAL_UPDATE_BAD_PAL_VERSION ((UINT64) -1)
185 #define EFI_SAL_UPDATE_PAL_AUTH_FAIL ((UINT64) -2)
186 #define EFI_SAL_UPDATE_PAL_BAD_TYPE ((UINT64) -3)
187 #define EFI_SAL_UPDATE_PAL_READONLY ((UINT64) -4)
188 #define EFI_SAL_UPDATE_PAL_WRITE_FAIL ((UINT64) -10)
189 #define EFI_SAL_UPDATE_PAL_ERASE_FAIL ((UINT64) -11)
190 #define EFI_SAL_UPDATE_PAL_READ_FAIL ((UINT64) -12)
191 #define EFI_SAL_UPDATE_PAL_CANT_FIT ((UINT64) -13)
200 } SAL_UPDATE_PAL_DATA_BLOCK
;
202 typedef struct _SAL_UPDATE_PAL_INFO_BLOCK
{
203 struct _SAL_UPDATE_PAL_INFO_BLOCK
*Next
;
204 struct SAL_UPDATE_PAL_DATA_BLOCK
*DataBlock
;
207 } SAL_UPDATE_PAL_INFO_BLOCK
;
210 // SAL System Table Definitions
225 } SAL_SYSTEM_TABLE_HEADER
;
228 #define EFI_SAL_ST_HEADER_SIGNATURE "SST_"
229 #define EFI_SAL_REVISION 0x0300
233 #define EFI_SAL_ST_ENTRY_POINT 0
234 #define EFI_SAL_ST_MEMORY_DESCRIPTOR 1
235 #define EFI_SAL_ST_PLATFORM_FEATURES 2
236 #define EFI_SAL_ST_TR_USAGE 3
237 #define EFI_SAL_ST_PTC 4
238 #define EFI_SAL_ST_AP_WAKEUP 5
242 UINT8 Type
; // Type == 0
246 UINT64 SalGlobalDataPointer
;
248 } SAL_ST_ENTRY_POINT_DESCRIPTOR
;
251 // Not needed for Itanium-based OS boot
254 UINT8 Type
; // Type == 1
255 UINT8 NeedVirtualRegistration
;
256 UINT8 MemoryAttributes
;
257 UINT8 PageAccessRights
;
258 UINT8 SupportedAttributes
;
262 UINT64 PhysicalMemoryAddress
;
266 } SAL_ST_MEMORY_DESCRIPTOR_ENTRY
;
272 #define SAL_MDT_ATTRIB_WB 0x00
274 // #define SAL_MDT_ATTRIB_UC 0x02
276 #define SAL_MDT_ATTRIB_UC 0x04
277 #define SAL_MDT_ATTRIB_UCE 0x05
278 #define SAL_MDT_ATTRIB_WC 0x06
281 // Supported memory Attributes
283 #define SAL_MDT_SUPPORT_WB 0x1
284 #define SAL_MDT_SUPPORT_UC 0x2
285 #define SAL_MDT_SUPPORT_UCE 0x4
286 #define SAL_MDT_SUPPORT_WC 0x8
289 // Virtual address registration
291 #define SAL_MDT_NO_VA 0x00
292 #define SAL_MDT_NEED_VA 0x01
296 #define SAL_REGULAR_MEMORY 0x0000
297 #define SAL_MMIO_MAPPING 0x0001
298 #define SAL_SAPIC_IPI_BLOCK 0x0002
299 #define SAL_IO_PORT_MAPPING 0x0003
300 #define SAL_FIRMWARE_MEMORY 0x0004
301 #define SAL_BLACK_HOLE 0x000A
305 #define SAL_MDT_USAGE_UNSPECIFIED 0x00
306 #define SAL_PAL_CODE 0x01
307 #define SAL_BOOTSERVICE_CODE 0x02
308 #define SAL_BOOTSERVICE_DATA 0x03
309 #define SAL_RUNTIMESERVICE_CODE 0x04
310 #define SAL_RUNTIMESERVICE_DATA 0x05
311 #define SAL_IA32_OPTIONROM 0x06
312 #define SAL_IA32_SYSTEMROM 0x07
313 #define SAL_PMI_CODE 0x0a
314 #define SAL_PMI_DATA 0x0b
318 UINT8 Type
; // Type == 2
319 UINT8 PlatformFeatures
;
321 } SAL_ST_PLATFORM_FEATURES
;
324 #define SAL_PLAT_FEAT_BUS_LOCK 0x01
325 #define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02
326 #define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04
330 UINT8 Type
; // Type == 3
334 UINT64 VirtualAddress
;
335 UINT64 EncodedPageSize
;
337 } SAL_ST_TR_DECRIPTOR
;
340 #define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00
341 #define EFI_SAL_ST_TR_USAGE_DATA 01
345 UINT64 NumberOfProcessors
;
346 UINT64 LocalIDRegister
;
347 } SAL_COHERENCE_DOMAIN_INFO
;
352 UINT8 Type
; // Type == 4
354 UINT32 NumberOfDomains
;
355 SAL_COHERENCE_DOMAIN_INFO
*DomainInformation
;
356 } SAL_ST_CACHE_COHERENCE_DECRIPTOR
;
361 UINT8 Type
; // Type == 5
364 UINT64 ExternalInterruptVector
;
365 } SAL_ST_AP_WAKEUP_DECRIPTOR
;
370 #define EFI_SAL_FIT_ENTRY_PTR (0x100000000 - 32) // 4GB - 24
371 #define EFI_SAL_FIT_PALA_ENTRY (0x100000000 - 48) // 4GB - 32
372 #define EFI_SAL_FIT_PALB_TYPE 01
380 UINT8 CheckSumValid
: 1;
385 // SAL Common Record Header
407 UINT8 ValidationBits
;
409 SAL_TIME_STAMP TimeStamp
;
410 UINT8 OemPlatformId
[16];
416 UINT8 ErrorRecoveryInfo
;
418 UINT32 SectionLength
;
422 // SAL Processor Record
424 #define SAL_PROCESSOR_ERROR_RECORD_INFO \
426 0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
429 #define CHECK_INFO_VALID_BIT_MASK 0x1
430 #define REQUESTOR_ID_VALID_BIT_MASK 0x2
431 #define RESPONDER_ID_VALID_BIT_MASK 0x4
432 #define TARGER_ID_VALID_BIT_MASK 0x8
433 #define PRECISE_IP_VALID_BIT_MASK 0x10
436 UINT64 InfoValid
: 1;
438 UINT64 RespValid
: 1;
439 UINT64 TargetValid
: 1;
441 UINT64 Reserved
: 59;
459 #define MIN_STATE_VALID_BIT_MASK 0x1
460 #define BR_VALID_BIT_MASK 0x2
461 #define CR_VALID_BIT_MASK 0x4
462 #define AR_VALID_BIT_MASK 0x8
463 #define RR_VALID_BIT_MASK 0x10
464 #define FR_VALID_BIT_MASK 0x20
467 UINT64 ValidFieldBits
;
468 UINT8 MinStateInfo
[1024];
476 #define PROC_ERROR_MAP_VALID_BIT_MASK 0x1
477 #define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2
478 #define PROC_CR_LID_VALID_BIT_MASK 0x4
479 #define PROC_STATIC_STRUCT_VALID_BIT_MASK 0x8
480 #define CPU_INFO_VALID_BIT_MASK 0x1000000
483 SAL_SEC_HEADER SectionHeader
;
484 UINT64 ValidationBits
;
486 UINT64 ProcStateParameter
;
488 MOD_ERROR_INFO CacheError
[15];
489 MOD_ERROR_INFO TlbError
[15];
490 MOD_ERROR_INFO BusError
[15];
491 MOD_ERROR_INFO RegFileCheck
[15];
492 MOD_ERROR_INFO MsCheck
[15];
494 PSI_STATIC_STRUCT PsiValidData
;
495 } SAL_PROCESSOR_ERROR_RECORD
;
498 // Sal Platform memory Error Record
500 #define SAL_MEMORY_ERROR_RECORD_INFO \
502 0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
505 #define MEMORY_ERROR_STATUS_VALID_BIT_MASK 0x1
506 #define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK 0x2
507 #define MEMORY_ADDR_BIT_MASK 0x4
508 #define MEMORY_NODE_VALID_BIT_MASK 0x8
509 #define MEMORY_CARD_VALID_BIT_MASK 0x10
510 #define MEMORY_MODULE_VALID_BIT_MASK 0x20
511 #define MEMORY_BANK_VALID_BIT_MASK 0x40
512 #define MEMORY_DEVICE_VALID_BIT_MASK 0x80
513 #define MEMORY_ROW_VALID_BIT_MASK 0x100
514 #define MEMORY_COLUMN_VALID_BIT_MASK 0x200
515 #define MEMORY_BIT_POSITION_VALID_BIT_MASK 0x400
516 #define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x800
517 #define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x1000
518 #define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK 0x2000
519 #define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK 0x4000
520 #define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK 0x8000
521 #define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x10000
524 SAL_SEC_HEADER SectionHeader
;
525 UINT64 ValidationBits
;
526 UINT64 MemErrorStatus
;
527 UINT64 MemPhysicalAddress
;
528 UINT64 MemPhysicalAddressMask
;
536 UINT16 MemBitPosition
;
537 UINT64 ModRequestorId
;
538 UINT64 ModResponderId
;
540 UINT64 BusSpecificData
;
541 UINT8 MemPlatformOemId
[16];
542 } SAL_MEMORY_ERROR_RECORD
;
547 #define SAL_PCI_BUS_ERROR_RECORD_INFO \
549 0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
552 #define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK 0x1
553 #define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK 0x2
554 #define PCI_BUS_ID_VALID_BIT_MASK 0x4
555 #define PCI_BUS_ADDRESS_VALID_BIT_MASK 0x8
556 #define PCI_BUS_DATA_VALID_BIT_MASK 0x10
557 #define PCI_BUS_CMD_VALID_BIT_MASK 0x20
558 #define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK 0x40
559 #define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK 0x80
560 #define PCI_BUS_TARGET_VALID_BIT_MASK 0x100
561 #define PCI_BUS_OEM_ID_VALID_BIT_MASK 0x200
562 #define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK 0x400
570 SAL_SEC_HEADER SectionHeader
;
571 UINT64 ValidationBits
;
572 UINT64 PciBusErrorStatus
;
573 UINT16 PciBusErrorType
;
576 UINT64 PciBusAddress
;
578 UINT64 PciBusCommand
;
579 UINT64 PciBusRequestorId
;
580 UINT64 PciBusResponderId
;
581 UINT64 PciBusTargetId
;
582 UINT8 PciBusOemId
[16];
583 } SAL_PCI_BUS_ERROR_RECORD
;
586 // PCI Component Errors
588 #define SAL_PCI_COMP_ERROR_RECORD_INFO \
590 0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
593 #define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK 0x1
594 #define PCI_COMP_INFO_VALID_BIT_MASK 0x2
595 #define PCI_COMP_MEM_NUM_VALID_BIT_MASK 0x4
596 #define PCI_COMP_IO_NUM_VALID_BIT_MASK 0x8
597 #define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK 0x10
598 #define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20
604 UINT8 FunctionNumber
;
612 SAL_SEC_HEADER SectionHeader
;
613 UINT64 ValidationBits
;
614 UINT64 PciComponentErrorStatus
;
615 PCI_COMP_INFO PciComponentInfo
;
616 UINT32 PciComponentMemNum
;
617 UINT32 PciComponentIoNum
;
618 UINT8 PciBusOemId
[16];
619 } SAL_PCI_COMPONENT_ERROR_RECORD
;
622 // Sal Device Errors Info.
624 #define SAL_DEVICE_ERROR_RECORD_INFO \
626 0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
629 #define SEL_RECORD_ID_VALID_BIT_MASK 0x1;
630 #define SEL_RECORD_TYPE_VALID_BIT_MASK 0x2;
631 #define SEL_GENERATOR_ID_VALID_BIT_MASK 0x4;
632 #define SEL_EVM_REV_VALID_BIT_MASK 0x8;
633 #define SEL_SENSOR_TYPE_VALID_BIT_MASK 0x10;
634 #define SEL_SENSOR_NUM_VALID_BIT_MASK 0x20;
635 #define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;
636 #define SEL_EVENT_DATA1_VALID_BIT_MASK 0x80;
637 #define SEL_EVENT_DATA2_VALID_BIT_MASK 0x100;
638 #define SEL_EVENT_DATA3_VALID_BIT_MASK 0x200;
641 SAL_SEC_HEADER SectionHeader
;
642 UINT64 ValidationBits
;
654 } SAL_DEVICE_ERROR_RECORD
;
657 // Sal SMBIOS Device Errors Info.
659 #define SAL_SMBIOS_ERROR_RECORD_INFO \
661 0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
664 #define SMBIOS_EVENT_TYPE_VALID_BIT_MASK 0x1
665 #define SMBIOS_LENGTH_VALID_BIT_MASK 0x2
666 #define SMBIOS_TIME_STAMP_VALID_BIT_MASK 0x4
667 #define SMBIOS_DATA_VALID_BIT_MASK 0x8
670 SAL_SEC_HEADER SectionHeader
;
671 UINT64 ValidationBits
;
672 UINT8 SmbiosEventType
;
674 UINT8 SmbiosBcdTimeStamp
[6];
675 } SAL_SMBIOS_DEVICE_ERROR_RECORD
;
678 // Sal Platform Specific Errors Info.
680 #define SAL_PLATFORM_ERROR_RECORD_INFO \
682 0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
685 #define PLATFORM_ERROR_STATUS_VALID_BIT_MASK 0x1
686 #define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x2
687 #define PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x4
688 #define PLATFORM_TARGET_VALID_BIT_MASK 0x8
689 #define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK 0x10
690 #define PLATFORM_OEM_ID_VALID_BIT_MASK 0x20
691 #define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40
692 #define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80
695 SAL_SEC_HEADER SectionHeader
;
696 UINT64 ValidationBits
;
697 UINT64 PlatformErrorStatus
;
698 UINT64 PlatformRequestorId
;
699 UINT64 PlatformResponderId
;
700 UINT64 PlatformTargetId
;
701 UINT64 PlatformBusSpecificData
;
702 UINT8 OemComponentId
[16];
703 } SAL_PLATFORM_SPECIFIC_ERROR_RECORD
;
706 // Union of all the possible Sal Record Types
709 SAL_RECORD_HEADER
*RecordHeader
;
710 SAL_PROCESSOR_ERROR_RECORD
*SalProcessorRecord
;
711 SAL_PCI_BUS_ERROR_RECORD
*SalPciBusRecord
;
712 SAL_PCI_COMPONENT_ERROR_RECORD
*SalPciComponentRecord
;
713 SAL_DEVICE_ERROR_RECORD
*ImpiRecord
;
714 SAL_SMBIOS_DEVICE_ERROR_RECORD
*SmbiosRecord
;
715 SAL_PLATFORM_SPECIFIC_ERROR_RECORD
*PlatformRecord
;
716 SAL_MEMORY_ERROR_RECORD
*MemoryRecord
;
718 } SAL_ERROR_RECORDS_POINTERS
;