4 Copyright (c) 2006 -2007, Intel Corporation All rights
5 reserved. This program and the accompanying materials are
6 licensed and made available under the terms and conditions of
7 the BSD License which accompanies this distribution. The full
8 text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 Module Name: PalCallLib.h
18 #ifndef __PAL_CALL_LIB_H__
19 #define __PAL_CALL_LIB_H__
21 #define PAL_SUCCESS 0x0
24 // CacheType of PAL_CACHE_FLUSH.
26 #define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1
27 #define PAL_CACHE_FLUSH_DATA_ALL 2
28 #define PAL_CACHE_FLUSH_ALL 3
29 #define PAL_CACHE_FLUSH_SYNC_TO_DATA 4
33 // Bitmask of Opearation of PAL_CACHE_FLUSH.
35 #define PAL_CACHE_FLUSH_INVALIDATE_LINES BIT0
36 #define PAL_CACHE_FLUSH_NO_INVALIDATE_LINES 0
37 #define PAL_CACHE_FLUSH_POLL_INTERRUPT BIT1
38 #define PAL_CACHE_FLUSH_NO_INTERRUPT 0
42 PAL Procedure - PAL_CACHE_FLUSH.
44 Flush the instruction or data caches. It is required by IPF.
45 The PAL procedure supports the Static Registers calling
46 convention. It could be called at virtual mode and physical
49 @param Index Index of PAL_CACHE_FLUSH within the
50 list of PAL procedures.
52 @param CacheType Unsigned 64-bit integer indicating
55 @param Operation Formatted bit vector indicating the
56 operation of this call.
58 @param ProgressIndicator Unsigned 64-bit integer specifying
59 the starting position of the flush
62 @return R9 Unsigned 64-bit integer specifying the vector
63 number of the pending interrupt.
65 @return R10 Unsigned 64-bit integer specifying the
66 starting position of the flush operation.
68 @return R11 Unsigned 64-bit integer specifying the vector
69 number of the pending interrupt.
71 @return Status 2 - Call completed without error, but a PMI
72 was taken during the execution of this
75 @return Status 1 - Call has not completed flushing due to
78 @return Status 0 - Call completed without error
80 @return Status -2 - Invalid argument
82 @return Status -3 - Call completed with error
85 #define PAL_CACHE_FLUSH 1
89 // Attributes of PAL_CACHE_CONFIG_INFO1
91 #define PAL_CACHE_ATTR_WT 0
92 #define PAL_CACHE_ATTR_WB 1
95 // PAL_CACHE_CONFIG_INFO1.StoreHint
97 #define PAL_CACHE_STORE_TEMPORAL 0
98 #define PAL_CACHE_STORE_NONE_TEMPORAL 3
101 // PAL_CACHE_CONFIG_INFO1.StoreHint
103 #define PAL_CACHE_STORE_TEMPORAL_LVL_1 0
104 #define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3
107 // PAL_CACHE_CONFIG_INFO1.StoreHint
109 #define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0
110 #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1
111 #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3
114 // Detail the characteristics of a given processor controlled
115 // cache in the cache hierarchy.
118 UINT64 IsUnified
: 1;
119 UINT64 Attributes
: 2;
120 UINT64 Associativity
:8;
123 UINT64 StoreLatency
:8;
126 } PAL_CACHE_INFO_RETURN1
;
129 // Detail the characteristics of a given processor controlled
130 // cache in the cache hierarchy.
134 UINT64 AliasBoundary
:8;
137 } PAL_CACHE_INFO_RETURN2
;
141 PAL Procedure - PAL_CACHE_INFO.
143 Return detailed instruction or data cache information. It is
144 required by IPF. The PAL procedure supports the Static
145 Registers calling convention. It could be called at virtual
146 mode and physical mode.
148 @param Index Index of PAL_CACHE_INFO within the list of
151 @param CacheLevel Unsigned 64-bit integer specifying the
152 level in the cache hierarchy for which
153 information is requested. This value must
154 be between 0 and one less than the value
155 returned in the cache_levels return value
156 from PAL_CACHE_SUMMARY.
158 @param CacheType Unsigned 64-bit integer with a value of 1
159 for instruction cache and 2 for data or
160 unified cache. All other values are
163 @param Reserved Should be 0.
166 @return R9 Detail the characteristics of a given
167 processor controlled cache in the cache
168 hierarchy. See PAL_CACHE_INFO_RETURN1.
170 @return R10 Detail the characteristics of a given
171 processor controlled cache in the cache
172 hierarchy. See PAL_CACHE_INFO_RETURN2.
174 @return R11 Reserved with 0.
177 @return Status 0 - Call completed without error
179 @return Status -2 - Invalid argument
181 @return Status -3 - Call completed with error
184 #define PAL_CACHE_INFO 2
189 // Level of PAL_CACHE_INIT.
191 #define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL
196 #define PAL_CACHE_INIT_TYPE_INSTRUCTION 0x1
197 #define PAL_CACHE_INIT_TYPE_DATA 0x2
198 #define PAL_CACHE_INIT_TYPE_INSTRUCTION_AND_DATA 0x3
201 // Restrict of PAL_CACHE_INIT.
203 #define PAL_CACHE_INIT_NO_RESTRICT 0
204 #define PAL_CACHE_INIT_RESTRICTED 1
208 PAL Procedure - PAL_CACHE_INIT.
210 Initialize the instruction or data caches. It is required by
211 IPF. The PAL procedure supports the Static Registers calling
212 convention. It could be called at physical mode.
214 @param Index Index of PAL_CACHE_INIT within the list of PAL
217 @param Level Unsigned 64-bit integer containing the level of
218 cache to initialize. If the cache level can be
219 initialized independently, only that level will
220 be initialized. Otherwise
221 implementation-dependent side-effects will
224 @param CacheType Unsigned 64-bit integer with a value of 1 to
225 initialize the instruction cache, 2 to
226 initialize the data cache, or 3 to
227 initialize both. All other values are
230 @param Restrict Unsigned 64-bit integer with a value of 0 or
231 1. All other values are reserved. If
232 restrict is 1 and initializing the specified
233 level and cache_type of the cache would
234 cause side-effects, PAL_CACHE_INIT will
235 return -4 instead of initializing the cache.
238 @return Status 0 - Call completed without error
240 @return Status -2 - Invalid argument
242 @return Status -3 - Call completed with error.
244 @return Status -4 - Call could not initialize the specified
245 level and cache_type of the cache without
246 side-effects and restrict was 1.
249 #define PAL_CACHE_INIT 3
253 // PAL_CACHE_PROTECTION.Method.
255 #define PAL_CACHE_PROTECTION_NONE_PROTECT 0
256 #define PAL_CACHE_PROTECTION_ODD_PROTECT 1
257 #define PAL_CACHE_PROTECTION_EVEN_PROTECT 2
258 #define PAL_CACHE_PROTECTION_ECC_PROTECT 3
263 // PAL_CACHE_PROTECTION.TagOrData.
265 #define PAL_CACHE_PROTECTION_PROTECT_DATA 0
266 #define PAL_CACHE_PROTECTION_PROTECT_TAG 1
267 #define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2
268 #define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3
271 // 32-bit protection information structures.
280 } PAL_CACHE_PROTECTION
;
284 PAL Procedure - PAL_CACHE_PROT_INFO.
286 Return instruction or data cache protection information. It is
287 required by IPF. The PAL procedure supports the Static
288 Registers calling convention. It could be called at physical
289 mode and Virtual mode.
291 @param Index Index of PAL_CACHE_PROT_INFO within the list of
294 @param CacheLevel Unsigned 64-bit integer specifying the level
295 in the cache hierarchy for which information
296 is requested. This value must be between 0
297 and one less than the value returned in the
298 cache_levels return value from
301 @param CacheType Unsigned 64-bit integer with a value of 1
302 for instruction cache and 2 for data or
303 unified cache. All other values are
306 @return R9 Detail the characteristics of a given
307 processor controlled cache in the cache
308 hierarchy. See PAL_CACHE_PROTECTION[0..1].
310 @return R10 Detail the characteristics of a given
311 processor controlled cache in the cache
312 hierarchy. See PAL_CACHE_PROTECTION[2..3].
314 @return R11 Detail the characteristics of a given
315 processor controlled cache in the cache
316 hierarchy. See PAL_CACHE_PROTECTION[4..5].
319 @return Status 0 - Call completed without error
321 @return Status -2 - Invalid argument
323 @return Status -3 - Call completed with error.
326 #define PAL_CACHE_PROT_INFO 38
330 @param ThreadId The thread identifier of the logical
331 processor for which information is being
332 returned. This value will be unique on a per
335 @param CoreId The core identifier of the logical processor
336 for which information is being returned.
337 This value will be unique on a per physical
338 processor package basis.
342 UINT64 ThreadId
: 16;
343 UINT64 Reserved1
: 16;
345 UINT64 Reserved2
: 16;
346 } PAL_PCOC_N_CACHE_INFO1
;
350 @param LogicalAddress Logical address: geographical address
351 of the logical processor for which
352 information is being returned. This is
353 the same value that is returned by the
354 PAL_FIXED_ADDR procedure when it is
355 called on the logical processor.
359 UINT64 LogicalAddress
: 16;
360 UINT64 Reserved1
: 16;
361 UINT64 Reserved2
: 32;
362 } PAL_PCOC_N_CACHE_INFO2
;
366 PAL Procedure - PAL_CACHE_SHARED_INFO.
368 Returns information on which logical processors share caches.
369 It is optional. The PAL procedure supports the Static
370 Registers calling convention. It could be called at physical
371 mode and Virtual mode.
373 @param Index Index of PAL_CACHE_SHARED_INFO within the list
376 @param CacheLevel Unsigned 64-bit integer specifying the
377 level in the cache hierarchy for which
378 information is requested. This value must
379 be between 0 and one less than the value
380 returned in the cache_levels return value
381 from PAL_CACHE_SUMMARY.
383 @param CacheType Unsigned 64-bit integer with a value of 1
384 for instruction cache and 2 for data or
385 unified cache. All other values are
388 @param ProcNumber Unsigned 64-bit integer that specifies for
389 which logical processor information is
390 being requested. This input argument must
391 be zero for the first call to this
392 procedure and can be a maximum value of
393 one less than the number of logical
394 processors sharing this cache, which is
395 returned by the num_shared return value.
397 @return R9 Unsigned integer that returns the number of
398 logical processors that share the processor
399 cache level and type, for which information was
402 @return R10 The format of PAL_PCOC_N_CACHE_INFO1.
404 @return R11 The format of PAL_PCOC_N_CACHE_INFO2.
406 @return Status 0 - Call completed without error
408 @return Status -1 - Unimplemented procedure
410 @return Status -2 - Invalid argument
412 @return Status -3 - Call completed with error.
415 #define PAL_CACHE_SHARED_INFO 43
420 PAL Procedure - PAL_CACHE_SUMMARY.
422 Return a summary of the cache hierarchy. It is required by
423 IPF. The PAL procedure supports the Static Registers calling
424 convention. It could be called at physical mode and Virtual
427 @param Index Index of PAL_CACHE_SUMMARY within the list of
431 @return R9 CacheLevels Unsigned 64-bit integer denoting the
432 number of levels of cache
433 implemented by the processor.
434 Strictly, this is the number of
435 levels for which the cache
436 controller is integrated into the
437 processor (the cache SRAMs may be
438 external to the processor).
440 @return R10 UniqueCaches Unsigned 64-bit integer denoting the
441 number of unique caches implemented
442 by the processor. This has a maximum
443 of 2*cache_levels, but may be less
444 if any of the levels in the cache
445 hierarchy are unified caches or do
446 not have both instruction and data
449 @return Status 0 - Call completed without error
451 @return Status -2 - Invalid argument
453 @return Status -3 - Call completed with error.
456 #define PAL_CACHE_SUMMARY 4
460 // Virtual Memory Attributes implemented by processor.
462 #define PAL_MEMORY_ATTR_WB 0
463 #define PAL_MEMORY_ATTR_WC 6
464 #define PAL_MEMORY_ATTR_UC 4
465 #define PAL_MEMORY_ATTR_UCE 5
466 #define PAL_MEMORY_ATTR_NATPAGE 7
470 PAL Procedure - PAL_MEM_ATTRIB.
472 Return a list of supported memory attributes.. It is required
473 by IPF. The PAL procedure supports the Static Registers calling
474 convention. It could be called at physical mode and Virtual
477 @param Index Index of PAL_MEM_ATTRIB within the list of PAL
481 @return R9 Attributes 8-bit vector of memory attributes
482 implemented by processor. See Virtual
483 Memory Attributes above.
485 @return Status 0 - Call completed without error
487 @return Status -2 - Invalid argument
489 @return Status -3 - Call completed with error.
493 #define PAL_MEM_ATTRIB 5
497 PAL Procedure - PAL_PREFETCH_VISIBILITY.
499 Used in architected sequence to transition pages from a
500 cacheable, speculative attribute to an uncacheable attribute.
501 It is required by IPF. The PAL procedure supports the Static
502 Registers calling convention. It could be called at physical
503 mode and Virtual mode.
505 @param Index Index of PAL_PREFETCH_VISIBILITY within the list
508 @param TransitionType Unsigned integer specifying the type
509 of memory attribute transition that is
512 @return Status 1 Call completed without error; this
513 call is not necessary on remote
516 @return Status 0 - Call completed without error
518 @return Status -2 - Invalid argument
520 @return Status -3 - Call completed with error.
523 #define PAL_PREFETCH_VISIBILITY 41
527 PAL Procedure - PAL_PTCE_INFO.
529 Return information needed for ptc.e instruction to purge
530 entire TC. It is required by IPF. The PAL procedure supports
531 the Static Registers calling convention. It could be called at
532 physical mode and Virtual mode.
534 @param Index Index of PAL_PTCE_INFO within the list
537 @return R9 Unsigned 64-bit integer denoting the beginning
538 address to be used by the first PTCE instruction
541 @return R10 Two unsigned 32-bit integers denoting the loop
542 counts of the outer (loop 1) and inner (loop 2)
543 purge loops. count1 (loop 1) is contained in bits
544 63:32 of the parameter, and count2 (loop 2) is
545 contained in bits 31:0 of the parameter.
547 @return R11 Two unsigned 32-bit integers denoting the loop
548 strides of the outer (loop 1) and inner (loop 2)
549 purge loops. stride1 (loop 1) is contained in bits
550 63:32 of the parameter, and stride2 (loop 2) is
551 contained in bits 31:0 of the parameter.
553 @return Status 0 - Call completed without error
555 @return Status -2 - Invalid argument
557 @return Status -3 - Call completed with error.
560 #define PAL_PTCE_INFO 6
566 @param NumberSets Unsigned 8-bit integer denoting the number
567 of hash sets for the specified level
568 (1=fully associative)
570 @param NumberWays Unsigned 8-bit integer denoting the
571 associativity of the specified level
574 @param NumberEntries Unsigned 16-bit integer denoting the
575 number of entries in the specified TC.
578 @param PageSizeIsOptimized Flag denoting whether the
579 specified level is optimized for
580 the region's preferred page size
581 (1=optimized) tc_pages indicates
582 which page sizes are usable by
583 this translation cache.
585 @param TcIsUnified Flag denoting whether the specified TC is
588 @param EntriesReduction Flag denoting whether installed
589 translation registers will reduce
590 the number of entries within the
597 UINT64 NumberEntries
:16;
598 UINT64 PageSizeIsOptimized
:1;
599 UINT64 TcIsUnified
:1;
600 UINT64 EntriesReduction
:1;
605 PAL Procedure - PAL_VM_INFO.
607 Return detailed information about virtual memory features
608 supported in the processor. It is required by IPF. The PAL
609 procedure supports the Static Registers calling convention. It
610 could be called at physical mode and Virtual mode.
612 @param Index Index of PAL_VM_INFO within the list
615 @param TcLevel Unsigned 64-bit integer specifying the level
616 in the TLB hierarchy for which information is
617 required. This value must be between 0 and one
618 less than the value returned in the
619 vm_info_1.num_tc_levels return value from
622 @param TcType Unsigned 64-bit integer with a value of 1 for
623 instruction translation cache and 2 for data
624 or unified translation cache. All other values
627 @return R9 8-byte formatted value returning information
628 about the specified TC. See PAL_TC_INFO above.
630 @return R10 64-bit vector containing a bit for each page
631 size supported in the specified TC, where bit
632 position n indicates a page size of 2**n.
634 @return Status 0 - Call completed without error
636 @return Status -2 - Invalid argument
638 @return Status -3 - Call completed with error.
641 #define PAL_VM_INFO 7
646 PAL Procedure - PAL_VM_PAGE_SIZE.
648 Return virtual memory TC and hardware walker page sizes
649 supported in the processor. It is required by IPF. The PAL
650 procedure supports the Static Registers calling convention. It
651 could be called at physical mode and Virtual mode.
653 @param Index Index of PAL_VM_PAGE_SIZE within the list
657 @return R9 64-bit vector containing a bit for each
658 architected page size that is supported for
659 TLB insertions and region registers.
661 @return R10 64-bit vector containing a bit for each
662 architected page size supported for TLB purge
665 @return Status 0 - Call completed without error
667 @return Status -2 - Invalid argument
669 @return Status -3 - Call completed with error.
672 #define PAL_VM_PAGE_SIZE 34
676 @param WalkerPresent 1-bit flag indicating whether a hardware
677 TLB walker is implemented (1 = walker
680 @param WidthOfPhysicalAddress Unsigned 7-bit integer
681 denoting the number of bits of
682 physical address implemented.
684 @param WidthOfKey Unsigned 8-bit integer denoting the number
685 of bits mplemented in the PKR.key field.
687 @param MaxPkrIndex Unsigned 8-bit integer denoting the
688 maximum PKR index (number of PKRs-1).
690 @param HashTagId Unsigned 8-bit integer which uniquely
691 identifies the processor hash and tag
694 @param MaxDtrIndex Unsigned 8 bit integer denoting the
695 maximum data translation register index
696 (number of dtr entries - 1).
698 @param MaxItrIndex Unsigned 8 bit integer denoting the
699 maximum instruction translation register
700 index (number of itr entries - 1).
702 @param NumberOfUniqueTc Unsigned 8-bit integer denoting the
703 number of unique TCs implemented.
707 @param NumberOfTcLevels Unsigned 8-bit integer denoting the
712 UINT64 WalkerPresent
:1;
713 UINT64 WidthOfPhysicalAddress
: 7;
715 UINT64 MaxPkrIndex
:8;
717 UINT64 MaxDtrIndex
:8;
718 UINT64 MaxItrIndex
:8;
719 UINT64 NumberOfUniqueTc
:8;
720 UINT64 NumberOfTcLevels
:8;
725 @param WidthOfVirtualAddress Unsigned 8-bit integer denoting
726 is the total number of virtual
729 @param WidthOfRid Unsigned 8-bit integer denoting the number
730 of bits implemented in the RR.rid field.
732 @param MaxPurgedTlbs Unsigned 16 bit integer denoting the
733 maximum number of concurrent outstanding
734 TLB purges allowed by the processor. A
735 value of 0 indicates one outstanding
736 purge allowed. A value of 216-1
737 indicates no limit on outstanding
738 purges. All other values indicate the
739 actual number of concurrent outstanding
744 UINT64 WidthOfVirtualAddress
:8;
746 UINT64 MaxPurgedTlbs
:16;
752 PAL Procedure - PAL_VM_SUMMARY.
754 Return summary information about virtual memory features
755 supported in the processor. It is required by IPF. The PAL
756 procedure supports the Static Registers calling convention. It
757 could be called at physical mode and Virtual mode.
759 @param Index Index of PAL_VM_SUMMARY within the list
763 @return R9 8-byte formatted value returning global virtual
764 memory information. See PAL_VM_INFO1 above.
766 @return R10 8-byte formatted value returning global virtual
767 memory information. See PAL_VM_INFO2 above.
769 @return Status 0 - Call completed without error
771 @return Status -2 - Invalid argument
773 @return Status -3 - Call completed with error.
776 #define PAL_VM_SUMMARY 8
780 // Bit mask of TR_valid flag.
782 #define PAL_TR_ACCESS_RIGHT_IS_VALID BIT0
783 #define PAL_TR_PRIVILEGE_LEVEL_IS_VALID BIT1
784 #define PAL_TR_DIRTY_IS_VALID BIT2
785 #define PAL_TR_MEMORY_ATTR_IS_VALID BIT3
790 PAL Procedure - PAL_VM_TR_READ.
792 Read contents of a translation register. It is required by
793 IPF. The PAL procedure supports the Stacked Register calling
794 convention. It could be called at physical mode.
796 @param Index Index of PAL_VM_TR_READ within the list
799 @param RegNumber Unsigned 64-bit number denoting which TR to
802 @param TrType Unsigned 64-bit number denoting whether to
803 read an ITR (0) or DTR (1). All other values
806 @param TrBuffer 64-bit pointer to the 32-byte memory buffer in
807 which translation data is returned.
809 @return R9 Formatted bit vector denoting which fields are
810 valid. See TR_valid above.
812 @return Status 0 - Call completed without error
814 @return Status -2 - Invalid argument
816 @return Status -3 - Call completed with error.
819 #define PAL_VM_TR_READ 261
825 // Bit Mask of Processor Bus Fesatures .
830 When 0, bus data errors are detected and single bit errors are
831 corrected. When 1, no error detection or correction is done.
834 #define PAL_BUS_DISABLE_DATA_ERROR_SIGNALLING BIT63
839 When 0, bus address errors are signalled on the bus. When 1,
840 no bus errors are signalled on the bus. If Disable Bus Address
841 Error Checking is 1, this bit is ignored.
844 #define PAL_BUS_DISABLE_ADDRESS_ERROR_SIGNALLING BIT62
851 When 0, bus errors are detected, single bit errors are
852 corrected., and a CMCI or MCA is generated internally to the
853 processor. When 1, no bus address errors are detected or
857 #define PAL_BUS_DISABLE_ADDRESS_ERROR_CHECK BIT61
862 When 0, bus protocol errors (BINIT#) are signaled by the
863 processor on the bus. When 1, bus protocol errors (BINIT#) are
864 not signaled on the bus. If Disable Bus Initialization Event
865 Checking is 1, this bit is ignored.
868 #define PAL_BUS_DISABLE_INITIALIZATION_EVENT_SIGNALLING BIT60
873 When 0, bus protocol errors (BINIT#) are detected and sampled
874 and an MCA is generated internally to the processor. When 1,
875 the processor will ignore bus protocol error conditions
879 #define PAL_BUS_DISABLE_INITIALIZATION_EVENT_CHECK BIT59
885 When 0, BERR# is signalled if a bus error is detected. When 1,
886 bus errors are not signalled on the bus.
889 #define PAL_BUS_DISABLE_ERROR_SIGNALLING BIT58
896 When 0, BERR# is signalled when internal processor requestor
897 initiated bus errors are detected. When 1, internal requester
898 bus errors are not signalled on the bus.
901 #define PAL_BUS_DISABLE__INTERNAL_ERROR_SIGNALLING BIT57
906 When 0, the processor takes an MCA if BERR# is asserted. When
907 1, the processor ignores the BERR# signal.
910 #define PAL_BUS_DISABLE_ERROR_CHECK BIT56
915 When 0, the processor asserts BINIT# if it detects a parity
916 error on the signals which identify the transactions to which
917 this is a response. When 1, the processor ignores parity on
921 #define PAL_BUS_DISABLE_RSP_ERROR_CHECK BIT55
926 When 0, the in-order transaction queue is limited only by the
927 number of hardware entries. When 1, the processor's in-order
928 transactions queue is limited to one entry.
931 #define PAL_BUS_DISABLE_TRANSACTION_QUEUE BIT54
935 Enable a bus cache line replacement transaction when a cache
936 line in the exclusive state is replaced from the highest level
937 processor cache and is not present in the lower level processor
938 caches. When 0, no bus cache line replacement transaction will
939 be seen on the bus. When 1, bus cache line replacement
940 transactions will be seen on the bus when the above condition is
944 #define PAL_BUS_ENABLE_EXCLUSIVE_CACHE_LINE_REPLACEMENT BIT53
949 Enable a bus cache line replacement transaction when a cache
950 line in the shared or exclusive state is replaced from the
951 highest level processor cache and is not present in the lower
952 level processor caches.
953 When 0, no bus cache line replacement transaction will be seen
954 on the bus. When 1, bus cache line replacement transactions
955 will be seen on the bus when the above condition is detected.
958 #define PAL_BUS_ENABLE_SHARED_CACHE_LINE_REPLACEMENT BIT52
964 When 0, the data bus is configured at the 2x data transfer
965 rate.When 1, the data bus is configured at the 1x data
966 transfer rate, 30 Opt. Req. Disable Bus Lock Mask. When 0, the
967 processor executes locked transactions atomically. When 1, the
968 processor masks the bus lock signal and executes locked
969 transactions as a non-atomic series of transactions.
972 #define PAL_BUS_ENABLE_HALF_TRANSFER BIT30
976 When 0, the processor will deassert bus request when finished
977 with each transaction. When 1, the processor will continue to
978 assert bus request after it has finished, if it was the last
979 agent to own the bus and if there are no other pending
983 #define PAL_BUS_REQUEST_BUS_PARKING BIT29
988 PAL Procedure - PAL_BUS_GET_FEATURES.
990 Return configurable processor bus interface features and their
991 current settings. It is required by IPF. The PAL procedure
992 supports the Stacked Register calling convention. It could be
993 called at physical mode.
995 @param Index Index of PAL_BUS_GET_FEATURES within the list
998 @return R9 64-bit vector of features implemented.
999 (1=implemented, 0=not implemented)
1001 @return R10 64-bit vector of current feature settings.
1003 @return R11 64-bit vector of features controllable by
1004 software. (1=controllable, 0= not controllable)
1006 @return Status 0 - Call completed without error
1008 @return Status -2 - Invalid argument
1010 @return Status -3 - Call completed with error.
1013 #define PAL_BUS_GET_FEATURES 9
1017 PAL Procedure - PAL_BUS_SET_FEATURES.
1019 Enable or disable configurable features in processor bus
1020 interface. It is required by IPF. It is required by IPF. The PAL procedure
1021 supports the Static Registers calling convention. It could be
1022 called at physical mode.
1024 @param Index Index of PAL_BUS_SET_FEATURES within the list
1027 @param FeatureSelect 64-bit vector denoting desired state of
1028 each feature (1=select, 0=non-select).
1030 @return Status 0 - Call completed without error
1032 @return Status -2 - Invalid argument
1034 @return Status -3 - Call completed with error.
1037 #define PAL_BUS_SET_FEATURES 10
1042 PAL Procedure - PAL_DEBUG_INFO.
1044 Return the number of instruction and data breakpoint
1045 registers. It is required by IPF. It is required by IPF. The
1046 PAL procedure supports the Static Registers calling
1047 convention. It could be called at physical mode and virtual
1050 @param Index Index of PAL_DEBUG_INFO within the list of PAL
1053 @return R9 Unsigned 64-bit integer denoting the number of
1054 pairs of instruction debug registers implemented
1057 @return R10 Unsigned 64-bit integer denoting the number of
1058 pairs of data debug registers implemented by the
1061 @return Status 0 - Call completed without error
1063 @return Status -2 - Invalid argument
1065 @return Status -3 - Call completed with error.
1068 #define PAL_DEBUG_INFO 11
1072 PAL Procedure - PAL_FIXED_ADDR.
1074 Return the fixed component of a processor¡¯s directed address.
1075 It is required by IPF. It is required by IPF. The PAL
1076 procedure supports the Static Registers calling convention. It
1077 could be called at physical mode and virtual mode.
1079 @param Index Index of PAL_FIXED_ADDR within the list of PAL
1082 @return R9 Fixed geographical address of this processor.
1085 @return Status 0 - Call completed without error
1087 @return Status -2 - Invalid argument
1089 @return Status -3 - Call completed with error.
1092 #define PAL_FIXED_ADDR 12
1096 PAL Procedure - PAL_FREQ_BASE.
1098 Return the frequency of the output clock for use by the
1099 platform, if generated by the processor. It is optinal. The
1100 PAL procedure supports the Static Registers calling
1101 convention. It could be called at physical mode and virtual
1104 @param Index Index of PAL_FREQ_BASE within the list of PAL
1107 @return R9 Base frequency of the platform if generated by the
1111 @return Status 0 - Call completed without error
1113 @return Status -1 - Unimplemented procedure
1115 @return Status -2 - Invalid argument
1117 @return Status -3 - Call completed with error.
1120 #define PAL_FREQ_BASE 13
1125 PAL Procedure - PAL_FREQ_RATIOS.
1127 Return ratio of processor, bus, and interval time counter to
1128 processor input clock or output clock for platform use, if
1129 generated by the processor. It is required by IPF. The PAL
1130 procedure supports the Static Registers calling convention. It
1131 could be called at physical mode and virtual mode.
1133 @param Index Index of PAL_FREQ_RATIOS within the list of PAL
1136 @return R9 Ratio of the processor frequency to the input
1137 clock of the processor, if the platform clock is
1138 generated externally or to the output clock to the
1139 platform, if the platform clock is generated by
1142 @return R10 Ratio of the bus frequency to the input clock of
1143 the processor, if the platform clock is generated
1144 externally or to the output clock to the platform,
1145 if the platform clock is generated by the
1148 @return R11 Ratio of the interval timer counter rate to input
1149 clock of the processor, if the platform clock is
1150 generated externally or to the output clock to the
1151 platform, if the platform clock is generated by
1154 @return Status 0 - Call completed without error
1156 @return Status -2 - Invalid argument
1158 @return Status -3 - Call completed with error.
1161 #define PAL_FREQ_RATIOS 14
1165 @param NumberOfLogicalProcessors Total number of logical
1166 processors on this physical
1167 processor package that are
1170 @param ThreadsPerCore Number of threads per core.
1172 @param CoresPerProcessor Total number of cores on this
1173 physical processor package.
1175 @param PhysicalProcessorPackageId Physical processor package
1176 identifier which was
1177 assigned at reset by the
1179 controller. This value may
1180 or may not be unique
1181 across the entire platform
1182 since it depends on the
1183 platform vendor's policy.
1186 UINT64 NumberOfLogicalProcessors
:16;
1187 UINT64 ThreadsPerCore
:8;
1189 UINT64 CoresPerProcessor
;
1191 UINT64 PhysicalProcessorPackageId
:8;
1193 } PAL_LOGICAL_PROCESSPR_OVERVIEW
;
1197 @param ThreadId The thread identifier of the logical
1198 processor for which information is being
1199 returned. This value will be unique on a per
1202 @param CoreId The core identifier of the logical processor
1203 for which information is being returned.
1204 This value will be unique on a per physical
1205 processor package basis.
1210 UINT64 Reserved1
:16;
1212 UINT64 Reserved2
:16;
1213 } PAL_LOGICAL_PROCESSORN_INFO1
;
1218 @param LogicalAddress Geographical address of the logical
1219 processor for which information is being
1220 returned. This is the same value that is
1221 returned by the PAL_FIXED_ADDR procedure
1222 when it is called on the logical
1228 UINT64 LogicalAddress
:16;
1230 } PAL_LOGICAL_PROCESSORN_INFO2
;
1234 PAL Procedure - PAL_LOGICAL_TO_PHYSICAL.
1236 Return information on which logical processors map to a
1237 physical processor die. It is optinal. The PAL procedure
1238 supports the Static Registers calling convention. It could be
1239 called at physical mode and virtual mode.
1241 @param Index Index of PAL_LOGICAL_TO_PHYSICAL within the list of PAL
1244 @param ProcessorNumber Signed 64-bit integer that specifies
1245 for which logical processor
1246 information is being requested. When
1247 this input argument is -1, information
1248 is returned about the logical
1249 processor on which the procedure call
1250 is made. This input argument must be
1251 in the range of 1 up to one less than
1252 the number of logical processors
1253 returned by num_log in the
1254 log_overview return value.
1257 @return R9 The format of PAL_LOGICAL_PROCESSPR_OVERVIEW.
1259 @return R10 The format of PAL_LOGICAL_PROCESSORN_INFO1.
1261 @return R11 The format of PAL_LOGICAL_PROCESSORN_INFO2.
1264 @return Status 0 - Call completed without error
1266 @return Status -1 - Unimplemented procedure
1268 @return Status -2 - Invalid argument
1270 @return Status -3 - Call completed with error.
1273 #define PAL_LOGICAL_TO_PHYSICAL 42
1278 @param NumberOfPmcPairs Unsigned 8-bit number defining the
1279 number of generic PMC/PMD pairs.
1281 @param WidthOfCounter Unsigned 8-bit number in the range
1282 0:60 defining the number of
1283 implemented counter bits.
1285 @param TypeOfCycleCounting Unsigned 8-bit number defining the
1286 event type for counting processor
1290 @param TypeOfRetiredInstructionBundle Retired Unsigned 8-bit
1292 event type for retired
1293 instruction bundles.
1297 UINT64 NumberOfPmcPairs
:8;
1298 UINT64 WidthOfCounter
:8;
1299 UINT64 TypeOfCycleCounting
:8;
1300 UINT64 TypeOfRetiredInstructionBundle
:8;
1302 } PAL_PERFORMANCE_INFO
;
1306 PAL Procedure - PAL_PERF_MON_INFO.
1308 Return the number and type of performance monitors. It is
1309 required by IPF. The PAL procedure supports the Static
1310 Registers calling convention. It could be called at physical
1311 mode and virtual mode.
1313 @param Index Index of PAL_PERF_MON_INFO within the list of
1316 @param PerformanceBuffer An address to an 8-byte aligned
1317 128-byte memory buffer.
1320 @return R9 Information about the performance monitors
1321 implemented. See PAL_PERFORMANCE_INFO;
1323 @return Status 0 - Call completed without error
1325 @return Status -2 - Invalid argument
1327 @return Status -3 - Call completed with error.
1330 #define PAL_PERF_MON_INFO 15
1332 #define PAL_PLATFORM_ADDR_INTERRUPT_BLOCK_TOKEN 0x0
1333 #define PAL_PLATFORM_ADDR_IO_BLOCK_TOKEN 0x1
1337 PAL Procedure - PAL_PLATFORM_ADDR.
1339 Specify processor interrupt block address and I/O port space
1340 address. It is required by IPF. The PAL procedure supports the
1341 Static Registers calling convention. It could be called at
1342 physical mode and virtual mode.
1344 @param Index Index of PAL_PLATFORM_ADDR within the list of
1347 @param Type Unsigned 64-bit integer specifying the type of
1348 block. 0 indicates that the processor interrupt
1349 block pointer should be initialized. 1 indicates
1350 that the processor I/O block pointer should be
1353 @param Address Unsigned 64-bit integer specifying the address
1354 to which the processor I/O block or interrupt
1355 block shall be set. The address must specify
1356 an implemented physical address on the
1357 processor model, bit 63 is ignored.
1360 @return Status 0 - Call completed without error
1362 @return Status -1 - Unimplemented procedure.
1364 @return Status -2 - Invalid argument
1366 @return Status -3 - Call completed with error.
1369 #define PAL_PLATFORM_ADDR 16
1374 @param EnableBerrPromotion Bit63. Enable BERR promotion. When
1375 1, the Bus Error (BERR) signal is
1376 promoted to the Bus Initialization
1377 (BINIT) signal, and the BINIT pin
1378 is asserted on the occurrence of
1379 each Bus Error. Setting this bit
1380 has no effect if BINIT signalling
1382 PAL_BUS_GET/SET_FEATURES)
1384 @param EnableMcaPromotion Bit62, Enable MCA promotion. When
1385 1, machine check aborts (MCAs) are
1386 promoted to the Bus Error signal,
1387 and the BERR pin is assert on each
1388 occurrence of an MCA. Setting this
1389 bit has no effect if BERR
1390 signalling is disabled. (See
1391 PAL_BUS_GET/SET_FEATURES)
1393 @param EnableMcaToBinitPromotion Bit61, Enable MCA to BINIT
1394 promotion. When 1, machine
1395 check aborts (MCAs) are
1397 Initialization signal, and
1398 the BINIT pin is assert on
1399 each occurrence of an MCA.
1400 Setting this bit has no
1401 effect if BINIT signalling
1403 PAL_BUS_GET/SET_FEATURES)
1405 @param EnableCmciPromotion Bit60, Enable CMCI promotion When
1406 1, Corrected Machine Check
1407 Interrupts (CMCI) are promoted to
1408 MCAs. They are also further
1409 promoted to BERR if bit 39, Enable
1410 MCA promotion, is also set and
1411 they are promoted to BINIT if bit
1412 38, Enable MCA to BINIT promotion,
1413 is also set. This bit has no
1414 effect if MCA signalling is
1416 PAL_BUS_GET/SET_FEATURES)
1418 @param DisableCache Bit59, Disable Cache. When 0, the
1419 processor performs cast outs on
1420 cacheable pages and issues and responds
1421 to coherency requests normally. When 1,
1422 the processor performs a memory access
1423 for each reference regardless of cache
1424 contents and issues no coherence
1425 requests and responds as if the line
1426 were not present. Cache contents cannot
1427 be relied upon when the cache is
1428 disabled. WARNING: Semaphore
1429 instructions may not be atomic or may
1430 cause Unsupported Data Reference faults
1431 if caches are disabled.
1433 @param DisableCoherency Bit58, Disable Coherency. When 0,
1434 the processor uses normal coherency
1435 requests and responses. When 1, the
1436 processor answers all requests as if
1437 the line were not present.
1439 @param DisableDPM Bit57, Disable Dynamic Power Management
1440 (DPM). When 0, the hardware may reduce
1441 power consumption by removing the clock
1442 input from idle functional units. When 1,
1443 all functional units will receive clock
1444 input, even when idle.
1446 @param DisableBinitWithTimeout Bit56, Disable a BINIT on
1447 internal processor time-out.
1448 When 0, the processor may
1449 generate a BINIT on an
1450 internal processor time-out.
1451 When 1, the processor will not
1452 generate a BINIT on an
1453 internal processor time-out.
1454 The event is silently ignored.
1457 @param EnableEnvNotification Bit55, Enable external
1458 notification when the processor
1459 detects hardware errors caused
1460 by environmental factors that
1462 deterministic behavior of the
1463 processor. When 1, this bit will
1464 enable external notification,
1465 when 0 external notification is
1466 not provided. The type of
1467 external notification of these
1468 errors is processor-dependent. A
1469 loss of processor deterministic
1470 behavior is considered to have
1472 environmentally induced errors
1473 cause the processor to deviate
1474 from its normal execution and
1475 eventually causes different
1476 behavior which can be observed
1477 at the processor bus pins.
1478 Processor errors that do not
1479 have this effects (i.e.,
1480 software induced machine checks)
1481 may or may not be promoted
1482 depending on the processor
1485 @param EnableVmsw Bit54, Enable the use of the vmsw
1486 instruction. When 0, the vmsw instruction
1487 causes a Virtualization fault when
1488 executed at the most privileged level.
1489 When 1, this bit will enable normal
1490 operation of the vmsw instruction.
1492 @param EnableMcaOnDataPoisoning Bit53, Enable MCA signaling
1493 on data-poisoning event
1494 detection. When 0, a CMCI
1495 will be signaled on error
1496 detection. When 1, an MCA
1497 will be signaled on error
1498 detection. If this feature
1499 is not supported, then the
1500 corresponding argument is
1501 ignored when calling
1502 PAL_PROC_SET_FEATURES. Note
1503 that the functionality of
1504 this bit is independent of
1505 the setting in bit 60
1506 (Enable CMCI promotion), and
1507 that the bit 60 setting does
1508 not affect CMCI signaling
1509 for data-poisoning related
1510 events. Volume 2: Processor
1511 Abstraction Layer 2:431
1512 PAL_PROC_GET_FEATURES
1514 @param DisablePState Bit52, Disable P-states. When 1, the PAL
1515 P-state procedures (PAL_PSTATE_INFO,
1516 PAL_SET_PSTATE, PAL_GET_PSTATE) will
1517 return with a status of -1
1518 (Unimplemented procedure).
1520 @param DisableBranchPrediction Bit47, Disable Dynamic branch
1521 prediction. When 0, the
1522 processor may predict branch
1523 targets and speculatively
1524 execute, but may not commit
1525 results. When 1, the processor
1526 must wait until branch targets
1527 are known to execute.
1529 @param DisableDynamicInsCachePrefetch Bit46, Disable
1530 DynamicInstruction Cache
1531 Prefetch. When 0, the
1532 processor may prefetch
1534 instruction which has
1535 not been executed, but
1538 instructions may not be
1539 fetched until needed or
1540 hinted for execution.
1541 (Prefetch for a hinted
1542 branch is allowed even
1543 when dynamic instruction
1547 @param DisableDynamicDataCachePrefetch Bit45, Disable Dynamic
1548 Data Cache Prefetch.
1549 When 0, the processor
1550 may prefetch into the
1551 caches any data which
1552 has not been accessed
1554 execution, but which
1556 accessed. When 1, no
1558 until it is needed for
1559 instruction execution
1563 @param DisableSpontaneousDeferral Bit44, Disable Spontaneous
1564 Deferral. When 1, the
1565 processor may optionally
1566 defer speculative loads
1567 that do not encounter any
1568 exception conditions, but
1570 implementation-dependent
1571 conditions (e.g., cache
1572 miss). When 0, spontaneous
1573 deferral is disabled.
1575 @param DisableDynamicPrediction Bit43, Disable Dynamic
1576 Predicate Prediction. When
1577 0, the processor may predict
1578 predicate results and
1579 execute speculatively, but
1580 may not commit results until
1581 the actual predicates are
1582 known. When 1, the processor
1583 shall not execute predicated
1584 instructions until the
1585 actual predicates are known.
1587 @param NoXr1ThroughXr3 Bit42, No XR1 through XR3 implemented.
1588 Denotes whether XR1 XR3 are
1589 implemented for machine check
1590 recovery. This feature may only be
1591 interrogated by PAL_PROC_GET_FEATURES.
1592 It may not be enabled or disabled by
1593 PAL_PROC_SET_FEATURES. The
1594 corresponding argument is ignored.
1596 @param NoXipXpsrXfs Bit41, No XIP, XPSR, and XFS
1597 implemented. Denotes whether XIP, XPSR,
1598 and XFS are implemented for machine
1599 check recovery. This feature may only be
1600 interrogated by PAL_PROC_GET_FEATURES.
1601 It may not be enabled or disabled by
1602 PAL_PROC_SET_FEATURES. The corresponding
1603 argument is ignored.
1605 @param NoVM Bit40, No Virtual Machine features implemented.
1606 Denotes whether PSR.vm is implemented. This
1607 feature may only be interrogated by
1608 PAL_PROC_GET_FEATURES. It may not be enabled or
1609 disabled by PAL_PROC_SET_FEATURES. The
1610 corresponding argument is ignored.
1612 @param NoVariablePState Bit39, No Variable P-state
1613 performance: A value of 1, indicates
1614 that a processor implements
1615 techniques to optimize performance
1616 for the given P-state power budget
1617 by dynamically varying the
1618 frequency, such that maximum
1619 performance is achieved for the
1620 power budget. A value of 0,
1621 indicates that P-states have no
1622 frequency variation or very small
1623 frequency variations for their given
1624 power budget. This feature may only
1626 PAL_PROC_GET_FEATURES. it may not be
1627 enabled or disabled by
1628 PAL_PROC_SET_FEATURES. The
1629 corresponding argument is ignored.
1632 @param NoSimpleImpInUndefinedIns Bit38, No Simple
1634 unimplemented instruction
1635 addresses. Denotes how an
1636 unimplemented instruction
1637 address is recorded in IIP
1639 Instruction Address trap or
1640 fault. When 1, the full
1641 unimplemented address is
1642 recorded in IIP; when 0, the
1643 address is sign extended
1644 (virtual addresses) or zero
1646 addresses). This feature may
1647 only be interrogated by
1648 PAL_PROC_GET_FEATURES. It
1649 may not be enabled or
1651 PAL_PROC_SET_FEATURES. The
1652 corresponding argument is
1655 @param NoPresentPmi Bit37, No INIT, PMI, and LINT pins
1656 present. Denotes the absence of INIT,
1657 PMI, LINT0 and LINT1 pins on the
1658 processor. When 1, the pins are absent.
1659 When 0, the pins are present. This
1660 feature may only be interrogated by
1661 PAL_PROC_GET_FEATURES. It may not be
1662 enabled or disabled by
1663 PAL_PROC_SET_FEATURES. The corresponding
1664 argument is ignored.
1666 @param FaultInUndefinedIns Bit36, No Unimplemented
1667 instruction address reported as
1668 fault. Denotes how the processor
1669 reports the detection of
1670 unimplemented instruction
1671 addresses. When 1, the processor
1672 reports an Unimplemented
1673 Instruction Address fault on the
1674 unimplemented address; when 0, it
1675 reports an Unimplemented
1676 Instruction Address trap on the
1677 previous instruction in program
1678 order. This feature may only be
1680 PAL_PROC_GET_FEATURES. It may not
1681 be enabled or disabled by
1682 PAL_PROC_SET_FEATURES. The
1683 corresponding argument is
1688 UINT64 Reserved1
:36;
1689 UINT64 FaultInUndefinedIns
:1;
1690 UINT64 NoPresentPmi
:1;
1691 UINT64 NoSimpleImpInUndefinedIns
:1;
1692 UINT64 NoVariablePState
:1;
1694 UINT64 NoXipXpsrXfs
:1;
1695 UINT64 NoXr1ThroughXr3
:1;
1696 UINT64 DisableDynamicPrediction
:1;
1697 UINT64 DisableSpontaneousDeferral
:1;
1698 UINT64 DisableDynamicDataCachePrefetch
:1;
1699 UINT64 DisableDynamicInsCachePrefetch
:1;
1700 UINT64 DisableBranchPrediction
:1;
1702 UINT64 DisablePState
:1;
1703 UINT64 EnableMcaOnDataPoisoning
:1;
1704 UINT64 EnableVmsw
:1;
1705 UINT64 EnableEnvNotification
:1;
1706 UINT64 DisableBinitWithTimeout
:1;
1707 UINT64 DisableDPM
:1;
1708 UINT64 DisableCoherency
:1;
1709 UINT64 DisableCache
:1;
1710 UINT64 EnableCmciPromotion
:1;
1711 UINT64 EnableMcaToBinitPromotion
:1;
1712 UINT64 EnableMcaPromotion
:1;
1713 UINT64 EnableBerrPromotion
:1;
1714 } PAL_PROCESSOR_FEATURES
;
1718 PAL Procedure - PAL_PROC_GET_FEATURES.
1720 Return configurable processor features and their current
1721 setting. It is required by IPF. The PAL procedure supports the
1722 Static Registers calling convention. It could be called at
1723 physical mode and virtual mode.
1725 @param Index Index of PAL_PROC_GET_FEATURES within the list of
1728 @param Reserved Reserved parameter.
1730 @param FeatureSet Feature set information is being requested
1734 @return R9 64-bit vector of features implemented. See
1735 PAL_PROCESSOR_FEATURES.
1737 @return R10 64-bit vector of current feature settings. See
1738 PAL_PROCESSOR_FEATURES.
1740 @return R11 64-bit vector of features controllable by
1743 @return Status 1 - Call completed without error; The
1744 feature_set passed is not supported but a
1745 feature_set of a larger value is supported.
1747 @return Status 0 - Call completed without error
1749 @return Status -2 - Invalid argument
1751 @return Status -3 - Call completed with error.
1753 @return Status -8 - feature_set passed is beyond the maximum
1754 feature_set supported
1757 #define PAL_PROC_GET_FEATURES 17
1762 PAL Procedure - PAL_PROC_SET_FEATURES.
1764 Enable or disable configurable processor features. It is
1765 required by IPF. The PAL procedure supports the Static
1766 Registers calling convention. It could be called at physical
1769 @param Index Index of PAL_PROC_SET_FEATURES within the list of
1772 @param FeatureSelect 64-bit vector denoting desired state of
1773 each feature (1=select, 0=non-select).
1775 @param FeatureSet Feature set to apply changes to. See
1776 PAL_PROC_GET_FEATURES for more information
1781 @return Status 1 - Call completed without error; The
1782 feature_set passed is not supported but a
1783 feature_set of a larger value is supported
1785 @return Status 0 - Call completed without error
1787 @return Status -2 - Invalid argument
1789 @return Status -3 - Call completed with error.
1791 @return Status -8 - feature_set passed is beyond the maximum
1792 feature_set supported
1795 #define PAL_PROC_SET_FEATURES 18
1799 // Value of PAL_REGISTER_INFO.InfoRequest.
1801 #define PAL_APPLICATION_REGISTER_IMPLEMENTED 0
1802 #define PAL_APPLICATION_REGISTER_READABLE 1
1803 #define PAL_CONTROL_REGISTER_IMPLEMENTED 2
1804 #define PAL_CONTROL_REGISTER_READABLE 3
1809 PAL Procedure - PAL_REGISTER_INFO.
1811 Return AR and CR register information. It is required by IPF.
1812 The PAL procedure supports the Static Registers calling
1813 convention. It could be called at physical mode and virtual
1816 @param Index Index of PAL_REGISTER_INFO within the list of
1819 @param InfoRequest Unsigned 64-bit integer denoting what
1820 register information is requested. See
1821 PAL_REGISTER_INFO.InfoRequest above.
1823 @return R9 64-bit vector denoting information for registers
1824 0-63. Bit 0 is register 0, bit 63 is register 63.
1826 @return R10 64-bit vector denoting information for registers
1827 64-127. Bit 0 is register 64, bit 63 is register
1831 @return Status 0 - Call completed without error
1833 @return Status -2 - Invalid argument
1835 @return Status -3 - Call completed with error.
1839 #define PAL_REGISTER_INFO 39
1843 PAL Procedure - PAL_RSE_INFO.
1845 Return RSE information. It is required by IPF. The PAL
1846 procedure supports the Static Registers calling convention. It
1847 could be called at physical mode and virtual mode.
1849 @param Index Index of PAL_RSE_INFO within the list of
1852 @param InfoRequest Unsigned 64-bit integer denoting what
1853 register information is requested. See
1854 PAL_REGISTER_INFO.InfoRequest above.
1856 @return R9 Number of physical stacked general registers.
1858 @return R10 RSE hints supported by processor.
1860 @return Status 0 - Call completed without error
1862 @return Status -2 - Invalid argument
1864 @return Status -3 - Call completed with error.
1868 #define PAL_RSE_INFO 19
1872 @param VersionOfPalB Is a 16-bit binary coded decimal (BCD)
1873 number that provides identification
1874 information about the PAL_B firmware.
1876 @param PalVendor Is an unsigned 8-bit integer indicating the
1877 vendor of the PAL code.
1879 @param VersionOfPalB Is a 16-bit binary coded decimal (BCD)
1880 number that provides identification
1881 information about the PAL_A firmware. In
1882 the split PAL_A model, this return value
1883 is the version number of the
1884 processor-specific PAL_A. The generic
1885 PAL_A version is not returned by this
1886 procedure in the split PAL_A model.
1890 UINT64 VersionOfPalB
:16;
1893 UINT64 VersionOfPalA
:16;
1894 UINT64 Reserved2
:16;
1899 PAL Procedure - PAL_VERSION.
1901 Return version of PAL code. It is required by IPF. The PAL
1902 procedure supports the Static Registers calling convention. It
1903 could be called at physical mode and virtual mode.
1905 @param Index Index of PAL_VERSION within the list of
1908 @param InfoRequest Unsigned 64-bit integer denoting what
1909 register information is requested. See
1910 PAL_REGISTER_INFO.InfoRequest above.
1912 @return R9 8-byte formatted value returning the minimum PAL
1913 version needed for proper operation of the
1914 processor. See PAL_VERSION_INFO above.
1916 @return R10 8-byte formatted value returning the current PAL
1917 version running on the processor. See
1918 PAL_VERSION_INFO above.
1920 @return Status 0 - Call completed without error
1922 @return Status -2 - Invalid argument
1924 @return Status -3 - Call completed with error.
1928 #define PAL_VERSION 20
1933 // Vectors of PAL_MC_CLEAR_LOG.pending
1935 #define PAL_MC_PENDING BIT0
1936 #define PAL_INIT_PENDING BIT1
1940 PAL Procedure - PAL_MC_CLEAR_LOG.
1942 Clear all error information from processor error logging
1943 registers. It is required by IPF. The PAL procedure supports
1944 the Static Registers calling convention. It could be called at
1945 physical mode and virtual mode.
1947 @param Index Index of PAL_MC_CLEAR_LOG within the list of
1951 @return R9 64-bit vector denoting whether an event is
1952 pending. See PAL_MC_CLEAR_LOG.pending above.
1955 @return Status 0 - Call completed without error
1957 @return Status -2 - Invalid argument
1959 @return Status -3 - Call completed with error.
1963 #define PAL_MC_CLEAR_LOG 21
1967 PAL Procedure - PAL_MC_DRAIN.
1969 Ensure that all operations that could cause an MCA have
1970 completed. It is required by IPF. The PAL procedure supports
1971 the Static Registers calling convention. It could be called at
1972 physical mode and virtual mode.
1974 @param Index Index of PAL_MC_DRAIN within the list of PAL
1978 @return Status 0 - Call completed without error
1980 @return Status -2 - Invalid argument
1982 @return Status -3 - Call completed with error.
1986 #define PAL_MC_DRAIN 22
1991 PAL Procedure - PAL_MC_DYNAMIC_STATE.
1993 Return Processor Dynamic State for logging by SAL. It is
1994 optional. The PAL procedure supports the Static Registers
1995 calling convention. It could be called at physical mode.
1997 @param Index Index of PAL_MC_DYNAMIC_STATE within the list of PAL
2000 @param Offset Offset of the next 8 bytes of Dynamic Processor
2001 State to return. (multiple of 8).
2003 @return R9 Unsigned 64-bit integer denoting bytes of Dynamic
2004 Processor State returned.
2006 @return R10 Next 8 bytes of Dynamic Processor State.
2008 @return Status 0 - Call completed without error
2010 @return Status -1 - Unimplemented procedure.
2012 @return Status -2 - Invalid argument
2014 @return Status -3 - Call completed with error.
2018 #define PAL_MC_DYNAMIC_STATE 24
2023 // Values of PAL_MC_ERROR_INFO.InfoIndex.
2025 #define PAL_PROCESSOR_ERROR_MAP 0
2026 #define PAL_PROCESSOR_STATE_PARAM 1
2027 #define PAL_STRUCTURE_SPECIFIC_ERROR 2
2031 @param CoreId Bit3:0, Processor core ID (default is 0 for
2032 processors with a single core)
2034 @param ThreadId Bit7:4, Logical thread ID (default is 0 for
2035 processors that execute a single thread)
2037 @param InfoOfInsCache Bit11:8, Error information is
2038 available for 1st, 2nd, 3rd, and 4th
2039 level instruction caches.
2041 @param InfoOfDataCache Bit15:12, Error information is
2042 available for 1st, 2nd, 3rd, and 4th
2043 level data/unified caches.
2045 @param InfoOfInsTlb Bit19:16 Error information is available
2046 for 1st, 2nd, 3rd, and 4th level
2049 @param InfoOfDataTlb Bit23:20, Error information is available
2050 for 1st, 2nd, 3rd, and 4th level
2053 @param InfoOfProcessorBus Bit27:24 Error information is
2054 available for the 1st, 2nd, 3rd,
2055 and 4th level processor bus
2058 @param InfoOfRegisterFile Bit31:28 Error information is
2059 available on register file
2062 @param InfoOfMicroArch Bit47:32, Error information is
2063 available on micro-architectural
2070 UINT64 InfoOfInsCache
:4;
2071 UINT64 InfoOfDataCache
:4;
2072 UINT64 InfoOfInsTlb
:4;
2073 UINT64 InfoOfDataTlb
:4;
2074 UINT64 InfoOfProcessorBus
:4;
2075 UINT64 InfoOfRegisterFile
:4;
2076 UINT64 InfoOfMicroArch
:4;
2078 } PAL_MC_ERROR_INFO_LEVEL_INDEX
;
2081 // Value of PAL_MC_ERROR_INFO.ErrorTypeIndex
2083 #define PAL_ERR_INFO_BY_LEVEL_INDEX 0
2084 #define PAL_ERR_INFO_TARGET_ADDRESS 1
2085 #define PAL_ERR_INFO_REQUESTER_IDENTIFIER 2
2086 #define PAL_ERR_INFO_REPONSER_INDENTIFIER 3
2087 #define PAL_ERR_INFO_PRECISE_INSTRUCTION_POINTER 4
2091 @param Operation Bit3:0, Type of cache operation that caused
2092 the machine check: 0 - unknown or internal
2093 error 1 - load 2 - store 3 - instruction
2094 fetch or instruction prefetch 4 - data
2095 prefetch (both hardware and software) 5 -
2096 snoop (coherency check) 6 - cast out
2097 (explicit or implicit write-back of a cache
2098 line) 7 - move in (cache line fill)
2100 @param FailedCacheLevel Bit5:4 Level of cache where the
2101 error occurred. A value of 0
2102 indicates the first level of cache.
2104 @param FailedInDataPart Bit8, Failure located in the data
2105 part of the cache line.
2107 @param FailedInTagPart Bit9, Failure located in the tag part
2110 @param FailedInDataCache Bit10, Failure located in the data
2113 @param FailedInInsCache Bit11, Failure located in the
2117 @param Mesi Bit14:12, 0 - cache line is invalid. 1 - cache
2118 line is held shared. 2 - cache line is held
2119 exclusive. 3 - cache line is modified. All other
2120 values are reserved.
2122 @param MesiIsValid Bit15, The mesi field in the cache_check
2125 @param FailedWay Bit20:16, Failure located in the way of
2126 the cache indicated by this value.
2128 @param WayIndexIsValid Bit21, The way and index field in the
2129 cache_check parameter is valid.
2131 @param MultipleBitsError Bit23, A multiple-bit error was
2132 detected, and data was poisoned for
2133 the corresponding cache line during
2136 @param IndexOfCacheLineError Bit51:32, Index of the cache
2137 line where the error occurred.
2139 @param InstructionSet Bit54, Instruction set. If this value
2140 is set to zero, the instruction that
2141 generated the machine check was an
2142 Intel Itanium instruction. If this bit
2143 is set to one, the instruction that
2144 generated the machine check was IA-32
2147 @param InstructionSetIsValid Bit55, The is field in the
2148 cache_check parameter is valid.
2150 @param PrivilegeLevel Bit57:56, Privilege level. The
2151 privilege level of the instruction
2152 bundle responsible for generating the
2155 @param PrivilegeLevelIsValide Bit58, The pl field of the
2156 cache_check parameter is
2159 @param McCorrected Bit59, Machine check corrected: This bit
2160 is set to one to indicate that the machine
2161 check has been corrected.
2163 @param TargetAddressIsValid Bit60, Target address is valid:
2164 This bit is set to one to
2165 indicate that a valid target
2166 address has been logged.
2168 @param RequesterIdentifier Bit61, Requester identifier: This
2169 bit is set to one to indicate that
2170 a valid requester identifier has
2173 @param ResponserIdentifier Bit62, Responder identifier: This
2174 bit is set to one to indicate that
2175 a valid responder identifier has
2178 @param PreciseInsPointer Bit63, Precise instruction pointer.
2179 This bit is set to one to indicate
2180 that a valid precise instruction
2181 pointer has been logged.
2186 UINT64 FailedCacheLevel
:2;
2188 UINT64 FailedInDataPart
:1;
2189 UINT64 FailedInTagPart
:1;
2190 UINT64 FailedInDataCache
:1;
2191 UINT64 FailedInInsCache
:1;
2193 UINT64 MesiIsValid
:1;
2195 UINT64 WayIndexIsValid
:1;
2198 UINT64 MultipleBitsError
:1;
2200 UINT64 IndexOfCacheLineError
:20;
2202 UINT64 InstructionSet
:1;
2203 UINT64 InstructionSetIsValid
:1;
2205 UINT64 PrivilegeLevel
:2;
2206 UINT64 PrivilegeLevelIsValide
:1;
2208 UINT64 McCorrected
:1;
2210 UINT64 TargetAddressIsValid
:1;
2211 UINT64 RequesterIdentifier
:1;
2212 UINT64 ResponserIdentifier
:1;
2213 UINT64 PreciseInsPointer
:1;
2215 } PAL_CACHE_CHECK_INFO
;
2219 @param FailedSlot Bit7:0, Slot number of the translation
2220 register where the failure occurred.
2222 @param FailedSlotIsValid Bit8, The tr_slot field in the
2223 TLB_check parameter is valid.
2225 @param TlbLevel Bit11:10, The level of the TLB where the
2226 error occurred. A value of 0 indicates the
2229 @param FailedInDataTr Bit16, Error occurred in the data
2230 translation registers.
2232 @param FailedInInsTr Bit17, Error occurred in the instruction
2233 translation registers
2235 @param FailedInDataTc Bit18, Error occurred in data
2238 @param FailedInInsTc Bit19, Error occurred in the instruction
2241 @param FailedOperation Bit23:20, Type of cache operation that
2242 caused the machine check: 0 - unknown
2243 1 - TLB access due to load instruction
2244 2 - TLB access due to store
2245 instruction 3 - TLB access due to
2246 instruction fetch or instruction
2247 prefetch 4 - TLB access due to data
2248 prefetch (both hardware and software)
2249 5 - TLB shoot down access 6 - TLB
2250 probe instruction (probe, tpa) 7 -
2251 move in (VHPT fill) 8 - purge (insert
2252 operation that purges entries or a TLB
2253 purge instruction) All other values
2256 @param InstructionSet Bit54, Instruction set. If this value
2257 is set to zero, the instruction that
2258 generated the machine check was an
2259 Intel Itanium instruction. If this bit
2260 is set to one, the instruction that
2261 generated the machine check was IA-32
2264 @param InstructionSetIsValid Bit55, The is field in the
2265 TLB_check parameter is valid.
2267 @param PrivelegeLevel Bit57:56, Privilege level. The
2268 privilege level of the instruction
2269 bundle responsible for generating the
2272 @param PrivelegeLevelIsValid Bit58, The pl field of the
2273 TLB_check parameter is valid.
2275 @param McCorrected Bit59, Machine check corrected: This bit
2276 is set to one to indicate that the machine
2277 check has been corrected.
2279 @param TargetAddressIsValid Bit60, Target address is valid:
2280 This bit is set to one to
2281 indicate that a valid target
2282 address has been logged.
2284 @param RequesterIdentifier Bit61 Requester identifier: This
2285 bit is set to one to indicate that
2286 a valid requester identifier has
2289 @param ResponserIdentifier Bit62, Responder identifier: This
2290 bit is set to one to indicate that
2291 a valid responder identifier has
2294 @param PreciseInsPointer Bit63 Precise instruction pointer.
2295 This bit is set to one to indicate
2296 that a valid precise instruction
2297 pointer has been logged.
2300 UINT64 FailedSlot
:8;
2301 UINT64 FailedSlotIsValid
:1;
2302 UINT64 Reserved1
:1;
2304 UINT64 Reserved2
:4;
2305 UINT64 FailedInDataTr
:1;
2306 UINT64 FailedInInsTr
:1;
2307 UINT64 FailedInDataTc
:1;
2308 UINT64 FailedInInsTc
:1;
2309 UINT64 FailedOperation
:4;
2310 UINT64 Reserved3
:30;
2311 UINT64 InstructionSet
:1;
2312 UINT64 InstructionSetIsValid
:1;
2313 UINT64 PrivelegeLevel
:2;
2314 UINT64 PrivelegeLevelIsValid
:1;
2315 UINT64 McCorrected
:1;
2316 UINT64 TargetAddressIsValid
:1;
2317 UINT64 RequesterIdentifier
:1;
2318 UINT64 ResponserIdentifier
:1;
2319 UINT64 PreciseInsPointer
:1;
2320 } PAL_TLB_CHECK_INFO
;
2324 PAL Procedure - PAL_MC_ERROR_INFO.
2326 Return Processor Machine Check Information and Processor
2327 Static State for logging by SAL. It is required by IPF. The
2328 PAL procedure supports the Static Registers calling
2329 convention. It could be called at physical and virtual mode.
2331 @param Index Index of PAL_MC_ERROR_INFO within the list of PAL
2334 @param InfoIndex Unsigned 64-bit integer identifying the
2335 error information that is being requested.
2336 See PAL_MC_ERROR_INFO.InfoIndex.
2338 @param LevelIndex 8-byte formatted value identifying the
2339 structure to return error information
2340 on. See PAL_MC_ERROR_INFO_LEVEL_INDEX.
2342 @param ErrorTypeIndex Unsigned 64-bit integer denoting the
2343 type of error information that is
2344 being requested for the structure
2345 identified in LevelIndex.
2348 @return R9 Error information returned. The format of this
2349 value is dependant on the input values passed.
2351 @return R10 If this value is zero, all the error information
2352 specified by err_type_index has been returned. If
2353 this value is one, more structure-specific error
2354 information is available and the caller needs to
2355 make this procedure call again with level_index
2356 unchanged and err_type_index, incremented.
2359 @return Status 0 - Call completed without error
2361 @return Status -2 - Invalid argument
2363 @return Status -3 - Call completed with error.
2365 @return Status -6 - Argument was valid, but no error
2366 information was available
2370 #define PAL_MC_ERROR_INFO 25
2374 PAL Procedure - PAL_MC_EXPECTED.
2376 Set/Reset Expected Machine Check Indicator. It is required by
2377 IPF. The PAL procedure supports the Static Registers calling
2378 convention. It could be called at physical mode.
2380 @param Index Index of PAL_MC_EXPECTED within the list of PAL
2383 @param Expected Unsigned integer with a value of 0 or 1 to
2384 set or reset the hardware resource
2385 PALE_CHECK examines for expected machine
2389 @return R9 Unsigned integer denoting whether a machine check
2390 was previously expected.
2393 @return Status 0 - Call completed without error
2395 @return Status -2 - Invalid argument
2397 @return Status -3 - Call completed with error.
2400 #define PAL_MC_EXPECTED 23
2404 PAL Procedure - PAL_MC_REGISTER_MEM.
2406 Register min-state save area with PAL for machine checks and
2407 inits. It is required by IPF. The PAL procedure supports the
2408 Static Registers calling convention. It could be called at
2411 @param Index Index of PAL_MC_REGISTER_MEM within the list of PAL
2414 @param Address Physical address of the buffer to be
2415 registered with PAL.
2419 @return Status 0 - Call completed without error
2421 @return Status -2 - Invalid argument
2423 @return Status -3 - Call completed with error.
2426 #define PAL_MC_REGISTER_MEM 27
2430 PAL Procedure - PAL_MC_RESUME.
2432 Restore minimal architected state and return to interrupted
2433 process. It is required by IPF. The PAL procedure supports the
2434 Static Registers calling convention. It could be called at
2437 @param Index Index of PAL_MC_RESUME within the list of PAL
2440 @param SetCmci Unsigned 64 bit integer denoting whether to
2441 set the CMC interrupt. A value of 0 indicates
2442 not to set the interrupt, a value of 1
2443 indicated to set the interrupt, and all other
2444 values are reserved.
2446 @param SavePtr Physical address of min-state save area used
2447 to used to restore processor state.
2449 @param NewContext Unsigned 64-bit integer denoting whether
2450 the caller is returning to a new context.
2451 A value of 0 indicates the caller is
2452 returning to the interrupted context, a
2453 value of 1 indicates that the caller is
2454 returning to a new context.
2458 @return Status -2 - Invalid argument
2460 @return Status -3 - Call completed with error.
2463 #define PAL_MC_RESUME 26
2467 PAL Procedure - PAL_HALT.
2469 Enter the low-power HALT state or an implementation-dependent
2470 low-power state. It is optinal. The PAL procedure supports the
2471 Static Registers calling convention. It could be called at
2474 @param Index Index of PAL_HALT within the list of PAL
2477 @param HaltState Unsigned 64-bit integer denoting low power
2480 @param IoDetailPtr 8-byte aligned physical address pointer to
2481 information on the type of I/O
2482 (load/store) requested.
2485 @return R9 Value returned if a load instruction is requested
2486 in the io_detail_ptr
2489 @return Status 0 - Call completed without error
2491 @return Status -1 - Unimplemented procedure
2493 @return Status -2 - Invalid argument
2495 @return Status -3 - Call completed with error.
2503 PAL Procedure - PAL_HALT_INFO.
2505 Return the low power capabilities of the processor. It is
2506 required by IPF. The PAL procedure supports the
2507 Stacked Registers calling convention. It could be called at
2508 physical and virtual mode.
2510 @param Index Index of PAL_HALT_INFO within the list of PAL
2513 @param PowerBuffer 64-bit pointer to a 64-byte buffer aligned
2514 on an 8-byte boundary.
2518 @return Status 0 - Call completed without error
2520 @return Status -2 - Invalid argument
2522 @return Status -3 - Call completed with error.
2525 #define PAL_HALT_INFO 257
2530 PAL Procedure - PAL_HALT_LIGHT.
2532 Enter the low power LIGHT HALT state. It is required by
2533 IPF. The PAL procedure supports the Static Registers calling
2534 convention. It could be called at physical and virtual mode.
2536 @param Index Index of PAL_HALT_LIGHT within the list of PAL
2540 @return Status 0 - Call completed without error
2542 @return Status -2 - Invalid argument
2544 @return Status -3 - Call completed with error.
2547 #define PAL_HALT_LIGHT 29
2551 PAL Procedure - PAL_CACHE_LINE_INIT.
2553 Initialize tags and data of a cache line for processor
2554 testing. It is required by IPF. The PAL procedure supports the
2555 Static Registers calling convention. It could be called at
2556 physical and virtual mode.
2558 @param Index Index of PAL_CACHE_LINE_INIT within the list of PAL
2561 @param Address Unsigned 64-bit integer value denoting the
2562 physical address from which the physical page
2563 number is to be generated. The address must be
2564 an implemented physical address, bit 63 must
2567 @param DataValue 64-bit data value which is used to
2568 initialize the cache line.
2571 @return Status 0 - Call completed without error
2573 @return Status -2 - Invalid argument
2575 @return Status -3 - Call completed with error.
2578 #define PAL_CACHE_LINE_INIT 31
2582 PAL Procedure - PAL_CACHE_READ.
2584 Read tag and data of a cache line for diagnostic testing. It
2585 is optional. The PAL procedure supports the
2586 Satcked Registers calling convention. It could be called at
2589 @param Index Index of PAL_CACHE_READ within the list of PAL
2592 @param LineId 8-byte formatted value describing where in the
2593 cache to read the data.
2595 @param Address 64-bit 8-byte aligned physical address from
2596 which to read the data. The address must be an
2597 implemented physical address on the processor
2598 model with bit 63 set to zero.
2600 @return R9 Right-justified value returned from the cache
2603 @return R10 The number of bits returned in data.
2605 @return R11 The status of the cache line.
2609 @return Status 1 - The word at address was found in the
2610 cache, but the line was invalid.
2612 @return Status 0 - Call completed without error
2614 @return Status -2 - Invalid argument
2616 @return Status -3 - Call completed with error.
2618 @return Status -5 - The word at address was not found in the
2621 @return Status -7 - The operation requested is not supported
2622 for this cache_type and level.
2625 #define PAL_CACHE_READ 259
2630 Write tag and data of a cache for diagnostic testing. It is
2631 optional. The PAL procedure supports the Satcked Registers
2632 calling convention. It could be called at physical mode.
2634 @param Index Index of PAL_CACHE_WRITE within the list of PAL
2637 @param LineId 8-byte formatted value describing where in the
2638 cache to write the data.
2640 @param Address 64-bit 8-byte aligned physical address at
2641 which the data should be written. The address
2642 must be an implemented physical address on the
2643 processor model with bit 63 set to 0.
2645 @param Data Unsigned 64-bit integer value to write into
2646 the specified part of the cache.
2649 @return Status 0 - Call completed without error
2651 @return Status -2 - Invalid argument
2653 @return Status -3 - Call completed with error.
2656 @return Status -7 - The operation requested is not supported
2657 for this cache_type and level.
2660 #define PAL_CACHE_WRITE 260
2664 PAL Procedure - PAL_TEST_INFO.
2666 Returns alignment and size requirements needed for the memory
2667 buffer passed to the PAL_TEST_PROC procedure as well as
2668 information on self-test control words for the processor self
2669 tests. It is required by IPF. The PAL procedure supports the
2670 Static Registers calling convention. It could be called at
2673 @param Index Index of PAL_TEST_INFO within the list of PAL
2676 @param TestPhase Unsigned integer that specifies which phase
2677 of the processor self-test information is
2678 being requested on. A value of 0 indicates
2679 the phase two of the processor self-test and
2680 a value of 1 indicates phase one of the
2681 processor self-test. All other values are
2684 @return R9 Unsigned 64-bit integer denoting the number of
2685 bytes of main memory needed to perform the second
2686 phase of processor self-test.
2688 @return R10 Unsigned 64-bit integer denoting the alignment
2689 required for the memory buffer.
2691 @return R11 48-bit wide bit-field indicating if control of
2692 the processor self-tests is supported and which
2693 bits of the test_control field are defined for
2697 @return Status 0 - Call completed without error
2699 @return Status -2 - Invalid argument
2701 @return Status -3 - Call completed with error.
2705 #define PAL_TEST_INFO 37
2709 @param BufferSize Indicates the size in bytes of the memory
2710 buffer that is passed to this procedure.
2711 BufferSize must be greater than or equal in
2712 size to the bytes_needed return value from
2713 PAL_TEST_INFO, otherwise this procedure will
2714 return with an invalid argument return
2717 @param TestPhase Defines which phase of the processor
2718 self-tests are requested to be run. A value
2719 of zero indicates to run phase two of the
2720 processor self-tests. Phase two of the
2721 processor self-tests are ones that require
2722 external memory to execute correctly. A
2723 value of one indicates to run phase one of
2724 the processor self-tests. Phase one of the
2725 processor self-tests are tests run during
2726 PALE_RESET and do not depend on external
2727 memory to run correctly. When the caller
2728 requests to have phase one of the processor
2729 self-test run via this procedure call, a
2730 memory buffer may be needed to save and
2731 restore state as required by the PAL calling
2732 conventions. The procedure PAL_TEST_INFO
2733 informs the caller about the requirements of
2738 UINT64 BufferSize
:56;
2740 } PAL_TEST_INFO_INFO
;
2744 @param TestControl This is an ordered implementation-specific
2745 control word that allows the user control
2746 over the length and runtime of the
2747 processor self-tests. This control word is
2748 ordered from the longest running tests up
2749 to the shortest running tests with bit 0
2750 controlling the longest running test. PAL
2751 may not implement all 47-bits of the
2752 test_control word. PAL communicates if a
2753 bit provides control by placing a zero in
2754 that bit. If a bit provides no control,
2755 PAL will place a one in it. PAL will have
2756 two sets of test_control bits for the two
2757 phases of the processor self-test. PAL
2758 provides information about implemented
2759 test_control bits at the hand-off from PAL
2760 to SAL for the firmware recovery check.
2761 These test_control bits provide control
2762 for phase one of processor self-test. It
2763 also provides this information via the PAL
2764 procedure call PAL_TEST_INFO for both the
2765 phase one and phase two processor tests
2766 depending on which information the caller
2767 is requesting. PAL interprets these bits
2768 as input parameters on two occasions. The
2769 first time is when SAL passes control back
2770 to PAL after the firmware recovery check.
2771 The second time is when a call to
2772 PAL_TEST_PROC is made. When PAL interprets
2773 these bits it will only interpret
2774 implemented test_control bits and will
2775 ignore the values located in the
2776 unimplemented test_control bits. PAL
2777 interprets the implemented bits such that
2778 if a bit contains a zero, this indicates
2779 to run the test. If a bit contains a one,
2780 this indicates to PAL to skip the test. If
2781 the cs bit indicates that control is not
2782 available, the test_control bits will be
2783 ignored or generate an illegal argument in
2784 procedure calls if the caller sets these
2787 @param ControlSupport This bit defines if an implementation
2788 supports control of the PAL self-tests
2789 via the self-test control word. If
2790 this bit is 0, the implementation does
2791 not support control of the processor
2792 self-tests via the self-test control
2793 word. If this bit is 1, the
2794 implementation does support control of
2795 the processor self-tests via the
2796 self-test control word. If control is
2797 not supported, GR37 will be ignored at
2798 the hand-off between SAL and PAL after
2799 the firmware recovery check and the
2800 PAL procedures related to the
2801 processor self-tests may return
2802 illegal arguments if a user tries to
2803 use the self-test control features.
2807 UINT64 TestControl
:47;
2808 UINT64 ControlSupport
:1;
2810 } PAL_SELF_TEST_CONTROL
;
2814 @param Attributes Specifies the memory attributes that are
2815 allowed to be used with the memory buffer
2816 passed to this procedure. The attributes
2817 parameter is a vector where each bit
2818 represents one of the virtual memory
2819 attributes defined by the architecture.See
2820 MEMORY_AATRIBUTES. The caller is required
2821 to support the cacheable attribute for the
2822 memory buffer, otherwise an invalid
2823 argument will be returned.
2826 @param TestControl Is the self-test control word
2827 corresponding to the test_phase passed.
2828 This test_control directs the coverage and
2829 runtime of the processor self-tests
2830 specified by the test_phase input
2831 argument. Information on if this
2832 feature is implemented and the number of
2833 bits supported can be obtained by the
2834 PAL_TEST_INFO procedure call. If this
2835 feature is implemented by the processor,
2836 the caller can selectively skip parts of
2837 the processor self-test by setting
2838 test_control bits to a one. If a bit has a
2839 zero, this test will be run. The values in
2840 the unimplemented bits are ignored. If
2841 PAL_TEST_INFO indicated that the self-test
2842 control word is not implemented, this
2843 procedure will return with an invalid
2844 argument status if the caller sets any of
2845 the test_control bits. See
2846 PAL_SELF_TEST_CONTROL.
2849 UINT64 Attributes
:8;
2851 UINT64 TestControl
:48;
2856 PAL Procedure - PAL_TEST_PROC.
2858 Perform late processor self test. It is required by IPF. The
2859 PAL procedure supports the Static Registers calling
2860 convention. It could be called at physical mode.
2862 @param Index Index of PAL_TEST_PROC within the list of PAL
2865 @param TestAddress 64-bit physical address of main memory
2866 area to be used by processor self-test.
2867 The memory region passed must be
2868 cacheable, bit 63 must be zero.
2870 @param TestInfo Input argument specifying the size of the
2871 memory buffer passed and the phase of the
2872 processor self-test that should be run. See
2875 @param TestParam Input argument specifying the self-test
2876 control word and the allowable memory
2877 attributes that can be used with the memory
2878 buffer. See PAL_TEST_CONTROL.
2880 @return R9 Formatted 8-byte value denoting the state of the
2881 processor after self-test
2885 @return Status 1 - Call completed without error, but hardware
2886 failures occurred during self-test.
2888 @return Status 0 - Call completed without error
2890 @return Status -2 - Invalid argument
2892 @return Status -3 - Call completed with error.
2896 #define PAL_TEST_PROC 258
2900 @param NumberOfInterruptControllers Number of interrupt
2901 controllers currently
2902 enabled on the system.
2904 @param NumberOfProcessors Number of processors currently
2905 enabled on the system.
2909 UINT32 NumberOfInterruptControllers
;
2910 UINT32 NumberOfProcessors
;
2911 } PAL_PLATFORM_INFO
;
2915 PAL Procedure - PAL_COPY_INFO.
2917 Return information needed to relocate PAL procedures and PAL
2918 PMI code to memory. It is required by IPF. The PAL procedure
2919 supports the Static Registers calling convention. It could be
2920 called at physical mode.
2922 @param Index Index of PAL_COPY_INFO within the list of PAL
2925 @param CopyType Unsigned integer denoting type of procedures
2926 for which copy information is requested.
2928 @param PlatformInfo 8-byte formatted value describing the
2929 number of processors and the number of
2930 interrupt controllers currently enabled
2931 on the system. See PAL_PLATFORM_INFO.
2934 @param McaProcStateInfo Unsigned integer denoting the number
2935 of bytes that SAL needs for the
2936 min-state save area for each
2941 @return R9 Unsigned integer denoting the number of bytes of
2942 PAL information that must be copied to main
2945 @return R10 Unsigned integer denoting the starting alignment
2946 of the data to be copied.
2948 @return Status 0 - Call completed without error
2950 @return Status -2 - Invalid argument
2952 @return Status -3 - Call completed with error.
2956 #define PAL_CODE_TOKEN 0x0
2957 #define PAL_IA32EMU_CODE_TOKEN 0x1
2959 #define PAL_COPY_INFO 30
2963 PAL Procedure - PAL_COPY_PAL.
2965 Relocate PAL procedures and PAL PMI code to memory. It is
2966 required by IPF. The PAL procedure supports the Stacked
2967 Registers calling convention. It could be called at physical
2970 @param Index Index of PAL_COPY_PAL within the list of PAL
2973 @param TargetAddress Physical address of a memory buffer to
2974 copy relocatable PAL procedures and PAL
2977 @param AllocSize Unsigned integer denoting the size of the
2978 buffer passed by SAL for the copy operation.
2981 @param CopyOption Unsigned integer indicating whether
2982 relocatable PAL code and PAL PMI code
2983 should be copied from firmware address
2984 space to main memory.
2987 @return R9 Unsigned integer denoting the offset of PAL_PROC
2988 in the relocatable segment copied.
2990 @return Status 0 - Call completed without error
2992 @return Status -2 - Invalid argument
2994 @return Status -3 - Call completed with error.
2998 #define PAL_COPY_PAL 256
3002 PAL Procedure - PAL_ENTER_IA_32_ENV.
3004 Enter IA-32 System environment. It is optional. The PAL
3005 procedure supports the Static Registers calling convention.
3006 It could be called at physical mode.
3008 Note: Since this is a special call, it does not follow the PAL
3009 static register calling convention. GR28 contains the index of
3010 PAL_ENTER_IA_32_ENV within the list of PAL procedures. All other
3011 input arguments including GR29-GR31 are setup by SAL to values
3012 as required by the IA-32 operating system defined in Table
3013 11-67. The registers that are designated as preserved, scratch,
3014 input arguments and procedure return values by the static
3015 procedure calling convention are not followed by this call. For
3016 instance, GR5 and GR6 need not be preserved since these are
3017 regarded as scratch by the IA-32 operating system. Note: In an
3018 MP system, this call must be COMPLETED on the first CPU to enter
3019 the IA-32 System Environment (may or may not be the BSP) prior
3020 to being called on the remaining processors in the MP system.
3022 @param Index GR28 contains the index of the
3023 PAL_ENTER_IA_32_ENV call within the list of PAL
3027 @return Status The status is returned in GR4.
3028 -1 - Un-implemented procedure 0 JMPE detected
3031 0 - 1 SAL allocated buffer for IA-32 System
3032 Environment operation is too small
3034 2 - IA-32 Firmware Checksum Error
3036 3 - SAL allocated buffer for IA-32 System
3037 Environment operation is not properly aligned
3039 4 - Error in SAL MP Info Table
3041 5 - Error in SAL Memory Descriptor Table
3043 6 - Error in SAL System Table
3045 7 - Inconsistent IA-32 state
3047 8 - IA-32 Firmware Internal Error
3049 9 - IA-32 Soft Reset (Note: remaining register
3050 state is undefined for this termination
3053 10 - Machine Check Error
3055 11 - Error in SAL I/O Intercept Table
3057 12 - Processor exit due to other processor in
3058 MP system terminating the IA32 system
3059 environment. (Note: remaining register state
3060 is undefined for this termination reason.)
3062 13 - Itanium architecture-based state
3063 corruption by either SAL PMI handler or I/O
3064 Intercept callback function.
3068 #define PAL_ENTER_IA_32_ENV 33
3072 PAL Procedure - PAL_PMI_ENTRYPOINT.
3074 Register PMI memory entrypoints with processor. It is required
3075 by IPF. The PAL procedure supports the Stacked Registers
3076 calling convention. It could be called at physical mode.
3078 @param Index Index of PAL_PMI_ENTRYPOINT within the list of
3081 @param SalPmiEntry 256-byte aligned physical address of SAL
3082 PMI entrypoint in memory.
3085 @return Status 0 - Call completed without error
3087 @return Status -2 - Invalid argument
3089 @return Status -3 - Call completed with error.
3093 #define PAL_PMI_ENTRYPOINT 32
3098 The ASCII brand identification string will be copied to the
3099 address specified in the address input argument. The processor
3100 brand identification string is defined to be a maximum of 128
3101 characters long; 127 bytes will contain characters and the 128th
3102 byte is defined to be NULL (0). A processor may return less than
3103 the 127 ASCII characters as long as the string is null
3104 terminated. The string length will be placed in the brand_info
3108 #define PAL_BRAND_INFO_ID_REQUEST 0
3112 PAL Procedure - PAL_BRAND_INFO.
3114 Provides processor branding information. It is optional by
3115 IPF. The PAL procedure supports the Stacked Registers calling
3116 convention. It could be called at physical and Virtual mode.
3119 @param Index Index of PAL_BRAND_INFO within the list of PAL
3122 @param InfoRequest Unsigned 64-bit integer specifying the
3123 information that is being requested. (See
3124 PAL_BRAND_INFO_ID_REQUEST)
3126 @param Address Unsigned 64-bit integer specifying the
3127 address of the 128-byte block to which the
3128 processor brand string shall be written.
3131 @reture R9 Brand information returned. The format of this
3132 value is dependent on the input values passed.
3135 @return Status 0 - Call completed without error
3137 @return Status -1 - Unimplemented procedure
3139 @return Status -2 - Invalid argument
3141 @return Status -3 - Call completed with error.
3143 @return Status -6 - Input argument is not implemented.
3146 #define PAL_BRAND_INFO 274
3150 PAL Procedure - PAL_GET_HW_POLICY.
3152 Returns the current hardware resource sharing policy of the
3153 processor. It is optional by IPF. The PAL procedure supports
3154 the Static Registers calling convention. It could be called at
3155 physical and Virtual mode.
3158 @param Index Index of PAL_GET_HW_POLICY within the list of PAL
3161 @param ProcessorNumber Unsigned 64-bit integer that specifies
3162 for which logical processor
3163 information is being requested. This
3164 input argument must be zero for the
3165 first call to this procedure and can
3166 be a maximum value of one less than
3167 the number of logical processors
3168 impacted by the hardware resource
3169 sharing policy, which is returned by
3170 the R10 return value.
3173 @reture R9 Unsigned 64-bit integer representing the current
3174 hardware resource sharing policy.
3176 @return R10 Unsigned 64-bit integer that returns the number
3177 of logical processors impacted by the policy
3180 @return R11 Unsigned 64-bit integer containing the logical
3181 address of one of the logical processors
3182 impacted by policy modification.
3185 @return Status 0 - Call completed without error
3187 @return Status -1 - Unimplemented procedure
3189 @return Status -2 - Invalid argument
3191 @return Status -3 - Call completed with error.
3193 @return Status -9 - Call requires PAL memory buffer.
3196 #define PAL_GET_HW_POLICY 48
3200 // Value of PAL_SET_HW_POLICY.Policy
3202 #define PAL_SET_HW_POLICY_PERFORMANCE 0
3203 #define PAL_SET_HW_POLICY_FAIRNESS 1
3204 #define PAL_SET_HW_POLICY_HIGH_PRIORITY 2
3205 #define PAL_SET_HW_POLICY_EXCLUSIVE_HIGH_PRIORITY 3
3209 PAL Procedure - PAL_SET_HW_POLICY.
3211 Sets the current hardware resource sharing policy of the
3212 processor. It is optional by IPF. The PAL procedure supports
3213 the Static Registers calling convention. It could be called at
3214 physical and Virtual mode.
3217 @param Index Index of PAL_SET_HW_POLICY within the list of PAL
3220 @param Policy Unsigned 64-bit integer specifying the hardware
3221 resource sharing policy the caller is setting.
3222 See Value of PAL_SET_HW_POLICY.Policy above.
3225 @return Status 1 - Call completed successfully but could not
3226 change the hardware policy since a
3227 competing logical processor is set in
3228 exclusive high priority.
3230 @return Status 0 - Call completed without error
3232 @return Status -1 - Unimplemented procedure
3234 @return Status -2 - Invalid argument
3236 @return Status -3 - Call completed with error.
3238 @return Status -9 - Call requires PAL memory buffer.
3241 #define PAL_SET_HW_POLICY 49
3246 @param Mode Bit2:0, Indicates the mode of operation for this
3247 procedure: 0 - Query mode 1 ¨C Error inject mode
3248 (err_inj should also be specified) 2 - Cancel
3249 outstanding trigger. All other fields in
3250 PAL_MC_ERROR_TYPE_INFO,
3251 PAL_MC_ERROR_STRUCTURE_INFO and
3252 PAL_MC_ERROR_DATA_BUFFER are ignored. All other
3253 values are reserved.
3255 @param ErrorInjection Bit5:3, indicates the mode of error
3256 injection: 0 - Error inject only (no
3257 error consumption) 1 - Error inject
3258 and consume All other values are
3262 @param ErrorSeverity Bit7:6, indicates the severity desired
3263 for error injection/query. Definitions
3264 of the different error severity types
3265 0 - Corrected error 1 - Recoverable
3266 error 2 - Fatal error 3 - Reserved
3269 @param ErrorStructure Bit12:8, Indicates the structure
3270 identification for error
3271 injection/query: 0 - Any structure
3272 (cannot be used during query mode).
3273 When selected, the structure type used
3274 for error injection is determined by
3275 PAL. 1 - Cache 2 - TLB 3 - Register
3276 file 4 - Bus/System interconnect 5-15
3277 - Reserved 16-31 - Processor
3278 specific error injection
3279 capabilities.ErrorDataBuffer is used
3280 to specify error types. Please refer
3281 to the processor specific
3282 documentation for additional details.
3284 @param StructureHierarchy Bit15:13, Indicates the structure
3286 injection/query: 0 - Any level of
3287 hierarchy (cannot be used during
3288 query mode). When selected, the
3289 structure hierarchy used for error
3290 injection is determined by PAL. 1
3291 - Error structure hierarchy
3292 level-1 2 - Error structure
3293 hierarchy level-2 3 - Error
3294 structure hierarchy level-3 4 -
3295 Error structure hierarchy level-4
3296 All other values are reserved.
3297 Reserved 63:16 Reserved
3302 UINT64 ErrorInjection
:3;
3303 UINT64 ErrorSeverity
:2;
3304 UINT64 ErrorStructure
:5;
3305 UINT64 StructureHierarchy
:3;
3307 } PAL_MC_ERROR_TYPE_INFO
;
3311 @param StructInfoIsValid Bit0 When 1, indicates that the
3312 structure information fields
3313 (c_t,cl_p,cl_id) are valid and
3314 should be used for error injection.
3315 When 0, the structure information
3316 fields are ignored, and the values
3317 of these fields used for error
3319 implementation-specific.
3321 @param CacheType Bit2:1 Indicates which cache should be used
3322 for error injection: 0 - Reserved 1 -
3323 Instruction cache 2 - Data or unified cache
3327 @param PortionOfCacheLine Bit5:3 Indicates the portion of the
3328 cache line where the error should
3329 be injected: 0 - Reserved 1 - Tag
3330 2 - Data 3 - mesi All other
3331 values are reserved.
3333 @param Mechanism Bit8:6 Indicates which mechanism is used to
3334 identify the cache line to be used for error
3335 injection: 0 - Reserved 1 - Virtual address
3336 provided in the inj_addr field of the buffer
3337 pointed to by err_data_buffer should be used
3338 to identify the cache line for error
3339 injection. 2 - Physical address provided in
3340 the inj_addr field of the buffer pointed to
3341 by err_data_buffershould be used to identify
3342 the cache line for error injection. 3 - way
3343 and index fields provided in err_data_buffer
3344 should be used to identify the cache line
3345 for error injection. All other values are
3348 @param DataPoisonOfCacheLine Bit9 When 1, indicates that a
3349 multiple bit, non-correctable
3350 error should be injected in the
3351 cache line specified by cl_id.
3352 If this injected error is not
3353 consumed, it may eventually
3354 cause a data-poisoning event
3355 resulting in a corrected error
3356 signal, when the associated
3357 cache line is cast out (implicit
3358 or explicit write-back of the
3359 cache line). The error severity
3360 specified by err_sev in
3361 err_type_info must be set to 0
3362 (corrected error) when this bit
3366 @param TrigerInfoIsValid Bit32 When 1, indicates that the
3367 trigger information fields (trigger,
3368 trigger_pl) are valid and should be
3369 used for error injection. When 0,
3370 the trigger information fields are
3371 ignored and error injection is
3372 performed immediately.
3374 @param Triger Bit36:33 Indicates the operation type to be
3375 used as the error trigger condition. The
3376 address corresponding to the trigger is
3377 specified in the trigger_addr field of the
3378 buffer pointed to by err_data_buffer: 0 -
3379 Instruction memory access. The trigger match
3380 conditions for this operation type are similar
3381 to the IBR address breakpoint match conditions
3382 1 - Data memory access. The trigger match
3383 conditions for this operation type are similar
3384 to the DBR address breakpoint match conditions
3385 All other values are reserved.
3387 @param PrivilegeOfTriger Bit39:37 Indicates the privilege
3388 level of the context during which
3389 the error should be injected: 0 -
3390 privilege level 0 1 - privilege
3391 level 1 2 - privilege level 2 3 -
3392 privilege level 3 All other values
3393 are reserved. If the implementation
3394 does not support privilege level
3395 qualifier for triggers (i.e. if
3396 trigger_pl is 0 in the capabilities
3397 vector), this field is ignored and
3398 triggers can be taken at any
3403 UINT64 StructInfoIsValid
:1;
3405 UINT64 PortionOfCacheLine
:3;
3407 UINT64 DataPoisonOfCacheLine
:1;
3408 UINT64 Reserved1
:22;
3409 UINT64 TrigerInfoIsValid
:1;
3411 UINT64 PrivilegeOfTriger
:3;
3412 UINT64 Reserved2
:24;
3413 } PAL_MC_ERROR_STRUCT_INFO
;
3417 Buffer Pointed to by err_data_buffer ¨C TLB
3421 UINT64 TrigerAddress
;
3422 UINT64 VirtualPageNumber
:52;
3425 UINT64 Reserved2
:40;
3426 } PAL_MC_ERROR_DATA_BUFFER_TLB
;
3430 PAL Procedure - PAL_MC_ERROR_INJECT.
3432 Injects the requested processor error or returns information
3433 on the supported injection capabilities for this particular
3434 processor implementation. It is optional by IPF. The PAL
3435 procedure supports the Stacked Registers calling convention.
3436 It could be called at physical and Virtual mode.
3439 @param Index Index of PAL_MC_ERROR_INJECT within the list of PAL
3442 @param ErrorTypeInfo Unsigned 64-bit integer specifying the
3443 first level error information which
3444 identifies the error structure and
3445 corresponding structure hierarchy, and
3448 @param ErrorStructInfo Unsigned 64-bit integer identifying
3449 the optional structure specific
3450 information that provides the second
3451 level details for the requested error.
3453 @param ErrorDataBuffer 64-bit physical address of a buffer
3454 providing additional parameters for
3455 the requested error. The address of
3456 this buffer must be 8-byte aligned.
3458 @return R9 64-bit vector specifying the supported error
3459 injection capabilities for the input argument
3460 combination of struct_hier, err_struct and
3461 err_sev fields in ErrorTypeInfo.
3463 @return R10 64-bit vector specifying the architectural
3464 resources that are used by the procedure.
3467 @return Status 0 - Call completed without error
3469 @return Status -1 - Unimplemented procedure
3471 @return Status -2 - Invalid argument
3473 @return Status -3 - Call completed with error.
3475 @return Status -4 - Call completed with error; the requested
3476 error could not be injected due to failure in
3477 locating the target location in the specified
3480 @return Status -5 - Argument was valid, but requested error
3481 injection capability is not supported.
3483 @return Status -9 - Call requires PAL memory buffer.
3486 #define PAL_MC_ERROR_INJECT 276
3490 // Types of PAL_GET_PSTATE.Type
3492 #define PAL_GET_PSTATE_RECENT 0
3493 #define PAL_GET_PSTATE_AVERAGE_NEW_START 1
3494 #define PAL_GET_PSTATE_AVERAGE 2
3495 #define PAL_GET_PSTATE_NOW 3
3499 PAL Procedure - PAL_GET_PSTATE.
3501 Returns the performance index of the processor. It is optional
3502 by IPF. The PAL procedure supports the Stacked Registers
3503 calling convention. It could be called at physical and Virtual
3507 @param Index Index of PAL_GET_PSTATE within the list of PAL
3510 @param Type Type of performance_index value to be returned
3511 by this procedure.See PAL_GET_PSTATE.Type above.
3514 @return R9 Unsigned integer denoting the processor
3515 performance for the time duration since the last
3516 PAL_GET_PSTATE procedure call was made. The
3517 value returned is between 0 and 100, and is
3518 relative to the performance index of the highest
3521 @return Status 1 - Call completed without error, but accuracy
3522 of performance index has been impacted by a
3523 thermal throttling event, or a
3524 hardware-initiated event.
3526 @return Status 0 - Call completed without error
3528 @return Status -1 - Unimplemented procedure
3530 @return Status -2 - Invalid argument
3532 @return Status -3 - Call completed with error.
3534 @return Status -9 - Call requires PAL memory buffer.
3537 #define PAL_GET_PSTATE 262
3541 Layout of PAL_PSTATE_INFO.PStateBuffer
3545 UINT32 PerformanceIndex
:7;
3547 UINT32 TypicalPowerDissipation
:20;
3548 UINT32 TransitionLatency1
;
3549 UINT32 TransitionLatency2
;
3551 } PAL_PSTATE_INFO_BUFFER
;
3556 PAL Procedure - PAL_PSTATE_INFO.
3558 Returns information about the P-states supported by the
3559 processor. It is optional by IPF. The PAL procedure supports
3560 the Static Registers calling convention. It could be called
3561 at physical and Virtual mode.
3564 @param Index Index of PAL_PSTATE_INFO within the list of PAL
3567 @param PStateBuffer 64-bit pointer to a 256-byte buffer
3568 aligned on an 8-byte boundary. See
3569 PAL_PSTATE_INFO_BUFFER above.
3572 @return R9 Unsigned integer denoting the number of P-states
3573 supported. The maximum value of this field is 16.
3575 @return R10 Dependency domain information
3578 @return Status 0 - Call completed without error
3580 @return Status -1 - Unimplemented procedure
3582 @return Status -2 - Invalid argument
3584 @return Status -3 - Call completed with error.
3587 #define PAL_PSTATE_INFO 44
3592 PAL Procedure - PAL_SET_PSTATE.
3594 To request a processor transition to a given P-state. It is
3595 optional by IPF. The PAL procedure supports the Stacked
3596 Registers calling convention. It could be called at physical
3600 @param Index Index of PAL_SET_PSTATE within the list of PAL
3603 @param PState Unsigned integer denoting the processor
3604 P-state being requested.
3606 @param ForcePState Unsigned integer denoting whether the
3607 P-state change should be forced for the
3614 @return Status 1 - Call completed without error, but
3615 transition request was not accepted
3617 @return Status 0 - Call completed without error
3619 @return Status -1 - Unimplemented procedure
3621 @return Status -2 - Invalid argument
3623 @return Status -3 - Call completed with error.
3625 @return Status -9 - Call requires PAL memory buffer.
3628 #define PAL_SET_PSTATE 263
3632 PAL Procedure - PAL_SHUTDOWN.
3634 Put the logical processor into a low power state which can be
3635 exited only by a reset event. It is optional by IPF. The PAL
3636 procedure supports the Static Registers calling convention. It
3637 could be called at physical mode.
3640 @param Index Index of PAL_SHUTDOWN within the list of PAL
3643 @param NotifyPlatform 8-byte aligned physical address
3644 pointer providing details on how to
3645 optionally notify the platform that
3646 the processor is entering a shutdown
3649 @return Status -1 - Unimplemented procedure
3651 @return Status -2 - Invalid argument
3653 @return Status -3 - Call completed with error.
3655 @return Status -9 - Call requires PAL memory buffer.
3658 #define PAL_SHUTDOWN 45
3662 Layout of PAL_MEMORY_BUFFER.ControlWord
3666 UINT64 Registration
:1;
3667 UINT64 ProbeInterrupt
:1;
3669 } PAL_MEMORY_CONTROL_WORD
;
3673 PAL Procedure - PAL_MEMORY_BUFFER.
3675 Provides cacheable memory to PAL for exclusive use during
3676 runtime. It is optional by IPF. The PAL procedure supports the
3677 Static Registers calling convention. It could be called at
3681 @param Index Index of PAL_MEMORY_BUFFER within the list of PAL
3684 @param BaseAddress Physical address of the memory buffer
3685 allocated for PAL use.
3687 @param AllocSize Unsigned integer denoting the size of the
3690 @param ControlWord Formatted bit vector that provides control
3691 options for this procedure. See
3692 PAL_MEMORY_CONTROL_WORD above.
3694 @return R9 Returns the minimum size of the memory buffer
3695 required if the alloc_size input argument was
3698 @return Status 1 - Call has not completed a buffer relocation
3699 due to a pending interrupt
3701 @return Status 0 - Call completed without error
3703 @return Status -1 - Unimplemented procedure
3705 @return Status -2 - Invalid argument
3707 @return Status -3 - Call completed with error.
3709 @return Status -9 - Call requires PAL memory buffer.
3712 #define PAL_MEMORY_BUFFER 277
3717 PAL Procedure - PAL_VP_CREATE.
3719 Initializes a new vpd for the operation of a new virtual
3720 processor in the virtual environment. It is optional by IPF.
3721 The PAL procedure supports the Stacked Registers calling
3722 convention. It could be called at Virtual mode.
3725 @param Index Index of PAL_VP_CREATE within the list of PAL
3728 @param Vpd 64-bit host virtual pointer to the Virtual
3729 Processor Descriptor (VPD).
3731 @param HostIva 64-bit host virtual pointer to the host IVT
3732 for the virtual processor
3734 @param OptionalHandler 64-bit non-zero host-virtual pointer
3735 to an optional handler for
3736 virtualization intercepts.
3739 @return Status 0 - Call completed without error
3741 @return Status -1 - Unimplemented procedure
3743 @return Status -2 - Invalid argument
3745 @return Status -3 - Call completed with error.
3747 @return Status -9 - Call requires PAL memory buffer.
3750 #define PAL_VP_CREATE 265
3754 Virtual Environment Information Parameter
3761 } PAL_VP_ENV_INFO_RETURN
;
3765 PAL Procedure - PAL_VP_ENV_INFO.
3767 Returns the parameters needed to enter a virtual environment.
3768 It is optional by IPF. The PAL procedure supports the Stacked
3769 Registers calling convention. It could be called at Virtual
3773 @param Index Index of PAL_VP_ENV_INFO within the list of PAL
3776 @param Vpd 64-bit host virtual pointer to the Virtual
3777 Processor Descriptor (VPD).
3779 @param HostIva 64-bit host virtual pointer to the host IVT
3780 for the virtual processor
3782 @param OptionalHandler 64-bit non-zero host-virtual pointer
3783 to an optional handler for
3784 virtualization intercepts.
3785 @return R9 Unsigned integer denoting the number of bytes
3786 required by the PAL virtual environment buffer
3787 during PAL_VP_INIT_ENV
3789 @return R10 64-bit vector of virtual environment
3790 information. See PAL_VP_ENV_INFO_RETURN.
3793 @return Status 0 - Call completed without error
3795 @return Status -1 - Unimplemented procedure
3797 @return Status -2 - Invalid argument
3799 @return Status -3 - Call completed with error.
3801 @return Status -9 - Call requires PAL memory buffer.
3804 #define PAL_VP_ENV_INFO 266
3808 PAL Procedure - PAL_VP_EXIT_ENV.
3810 Allows a logical processor to exit a virtual environment.
3811 It is optional by IPF. The PAL procedure supports the Stacked
3812 Registers calling convention. It could be called at Virtual
3816 @param Index Index of PAL_VP_EXIT_ENV within the list of PAL
3819 @param Iva Optional 64-bit host virtual pointer to the IVT
3820 when this procedure is done
3822 @return Status 0 - Call completed without error
3824 @return Status -1 - Unimplemented procedure
3826 @return Status -2 - Invalid argument
3828 @return Status -3 - Call completed with error.
3830 @return Status -9 - Call requires PAL memory buffer.
3833 #define PAL_VP_EXIT_ENV 267
3839 PAL Procedure - PAL_VP_INIT_ENV.
3841 Allows a logical processor to enter a virtual environment. It
3842 is optional by IPF. The PAL procedure supports the Stacked
3843 Registers calling convention. It could be called at Virtual
3847 @param Index Index of PAL_VP_INIT_ENV within the list of PAL
3850 @param ConfigOptions 64-bit vector of global configuration
3853 @param PhysicalBase Host physical base address of a block of
3854 contiguous physical memory for the PAL
3855 virtual environment buffer 1) This
3856 memory area must be allocated by the VMM
3857 and be 4K aligned. The first logical
3858 processor to enter the environment will
3859 initialize the physical block for
3860 virtualization operations.
3862 @param VirtualBase Host virtual base address of the
3863 corresponding physical memory block for
3864 the PAL virtual environment buffer : The
3865 VMM must maintain the host virtual to host
3866 physical data and instruction translations
3867 in TRs for addresses within the allocated
3868 address space. Logical processors in this
3869 virtual environment will use this address
3870 when transitioning to virtual mode
3873 @return R9 Virtualization Service Address ¨C VSA specifies
3874 the virtual base address of the PAL
3875 virtualization services in this virtual
3879 @return Status 0 - Call completed without error
3881 @return Status -1 - Unimplemented procedure
3883 @return Status -2 - Invalid argument
3885 @return Status -3 - Call completed with error.
3887 @return Status -9 - Call requires PAL memory buffer.
3890 #define PAL_VP_INIT_ENV 268
3895 PAL Procedure - PAL_VP_REGISTER.
3897 Register a different host IVT and/or a different optional
3898 virtualization intercept handler for the virtual processor
3899 specified by vpd. It is optional by IPF. The PAL procedure
3900 supports the Stacked Registers calling convention. It could be
3901 called at Virtual mode.
3904 @param Index Index of PAL_VP_REGISTER within the list of PAL
3907 @param Vpd 64-bit host virtual pointer to the Virtual
3908 Processor Descriptor (VPD) host_iva 64-bit host
3909 virtual pointer to the host IVT for the virtual
3912 @param OptionalHandler 64-bit non-zero host-virtual pointer
3913 to an optional handler for
3914 virtualization intercepts.
3917 @return Status 0 - Call completed without error
3919 @return Status -1 - Unimplemented procedure
3921 @return Status -2 - Invalid argument
3923 @return Status -3 - Call completed with error.
3925 @return Status -9 - Call requires PAL memory buffer.
3928 #define PAL_VP_REGISTER 269
3933 PAL Procedure - PAL_VP_RESTORE.
3935 Restores virtual processor state for the specified vpd on the
3936 logical processor. It is optional by IPF. The PAL procedure
3937 supports the Stacked Registers calling convention. It could be
3938 called at Virtual mode.
3941 @param Index Index of PAL_VP_RESTORE within the list of PAL
3944 @param Vpd 64-bit host virtual pointer to the Virtual
3945 Processor Descriptor (VPD) host_iva 64-bit host
3946 virtual pointer to the host IVT for the virtual
3949 @param PalVector Vector specifies PAL procedure
3950 implementation-specific state to be
3954 @return Status 0 - Call completed without error
3956 @return Status -1 - Unimplemented procedure
3958 @return Status -2 - Invalid argument
3960 @return Status -3 - Call completed with error.
3962 @return Status -9 - Call requires PAL memory buffer.
3965 #define PAL_VP_RESTORE 270
3969 PAL Procedure - PAL_VP_SAVE.
3971 Saves virtual processor state for the specified vpd on the
3972 logical processor. It is optional by IPF. The PAL procedure
3973 supports the Stacked Registers calling convention. It could be
3974 called at Virtual mode.
3977 @param Index Index of PAL_VP_SAVE within the list of PAL
3980 @param Vpd 64-bit host virtual pointer to the Virtual
3981 Processor Descriptor (VPD) host_iva 64-bit host
3982 virtual pointer to the host IVT for the virtual
3985 @param PalVector Vector specifies PAL procedure
3986 implementation-specific state to be
3990 @return Status 0 - Call completed without error
3992 @return Status -1 - Unimplemented procedure
3994 @return Status -2 - Invalid argument
3996 @return Status -3 - Call completed with error.
3998 @return Status -9 - Call requires PAL memory buffer.
4001 #define PAL_VP_SAVE 271
4006 PAL Procedure - PAL_VP_TERMINATE.
4008 Terminates operation for the specified virtual processor. It
4009 is optional by IPF. The PAL procedure supports the Stacked
4010 Registers calling convention. It could be called at Virtual
4014 @param Index Index of PAL_VP_TERMINATE within the list of PAL
4017 @param Vpd 64-bit host virtual pointer to the Virtual
4018 Processor Descriptor (VPD)
4020 @param Iva Optional 64-bit host virtual pointer to the IVT
4021 when this procedure is done.
4023 @return Status 0 - Call completed without error
4025 @return Status -1 - Unimplemented procedure
4027 @return Status -2 - Invalid argument
4029 @return Status -3 - Call completed with error.
4031 @return Status -9 - Call requires PAL memory buffer.
4034 #define PAL_VP_TERMINATE 272
4037 Makes a PAL procedure call.
4039 This is a wrapper function to make a PAL procedure call. Based on the Index value,
4040 this API will make static or stacked PAL call. Architected procedures may be designated
4041 as required or optional. If a PAL procedure is specified as optional, a unique return
4042 code of 0xFFFFFFFFFFFFFFFF is returned in the Status field of the PAL_CALL_RETURN structure.
4043 This indicates that the procedure is not present in this PAL implementation. It is the
4044 caller¡¯s responsibility to check for this return code after calling any optional PAL
4045 procedure. No parameter checking is performed on the 4 input parameters, but there are
4046 some common rules that the caller should follow when making a PAL call. Any address
4047 passed to PAL as buffers for return parameters must be 8-byte aligned. Unaligned addresses
4048 may cause undefined results. For those parameters defined as reserved or some fields
4049 defined as reserved must be zero filled or the invalid argument return value may be
4050 returned or undefined result may occur during the execution of the procedure.
4051 This function is only available on IPF.
4053 @param Index - The PAL procedure Index number.
4054 @param Arg2 - The 2nd parameter for PAL procedure calls.
4055 @param Arg3 - The 3rd parameter for PAL procedure calls.
4056 @param Arg4 - The 4th parameter for PAL procedure calls.
4058 @return structure returned from the PAL Call procedure, including the status and return value.