]>
git.proxmox.com Git - mirror_edk2.git/blob - OldMdePkg/Library/BasePciExpressLib/PciLib.c
4 Functions in this library instance make use of MMIO functions in IoLib to
5 access memory mapped PCI configuration space.
7 All assertions for I/O operations are handled in MMIO functions in the IoLib
10 Copyright (c) 2006, Intel Corporation<BR>
11 All rights reserved. This program and the accompanying materials
12 are licensed and made available under the terms and conditions of the BSD License
13 which accompanies this distribution. The full text of the license may be found at
14 http://opensource.org/licenses/bsd-license.php
16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
17 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
24 Assert the validity of a PCI address. A valid PCI address should contain 1's
25 only in the low 28 bits.
27 @param A The address to validate.
30 #define ASSERT_INVALID_PCI_ADDRESS(A) \
31 ASSERT (((A) & ~0xfffffff) == 0)
35 Gets the base address of PCI Express.
37 This internal functions retrieves PCI Express Base Address via a PCD entry
38 PcdPciExpressBaseAddress.
40 @return The base address of PCI Express.
45 GetPciExpressBaseAddress (
49 return (VOID
*)(UINTN
) PcdGet64 (PcdPciExpressBaseAddress
);
53 Reads an 8-bit PCI configuration register.
55 Reads and returns the 8-bit PCI configuration register specified by Address.
56 This function must guarantee that all PCI read and write operations are
59 If Address > 0x0FFFFFFF, then ASSERT().
61 @param Address Address that encodes the PCI Bus, Device, Function and
64 @return The read value from the PCI configuration register.
73 ASSERT_INVALID_PCI_ADDRESS (Address
);
74 return MmioRead8 ((UINTN
) GetPciExpressBaseAddress () + Address
);
78 Writes an 8-bit PCI configuration register.
80 Writes the 8-bit PCI configuration register specified by Address with the
81 value specified by Value. Value is returned. This function must guarantee
82 that all PCI read and write operations are serialized.
84 If Address > 0x0FFFFFFF, then ASSERT().
86 @param Address Address that encodes the PCI Bus, Device, Function and
88 @param Value The value to write.
90 @return The value written to the PCI configuration register.
100 ASSERT_INVALID_PCI_ADDRESS (Address
);
101 return MmioWrite8 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
105 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
108 Reads the 8-bit PCI configuration register specified by Address, performs a
109 bitwise inclusive OR between the read result and the value specified by
110 OrData, and writes the result to the 8-bit PCI configuration register
111 specified by Address. The value written to the PCI configuration register is
112 returned. This function must guarantee that all PCI read and write operations
115 If Address > 0x0FFFFFFF, then ASSERT().
117 @param Address Address that encodes the PCI Bus, Device, Function and
119 @param OrData The value to OR with the PCI configuration register.
121 @return The value written back to the PCI configuration register.
131 ASSERT_INVALID_PCI_ADDRESS (Address
);
132 return MmioOr8 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
136 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
139 Reads the 8-bit PCI configuration register specified by Address, performs a
140 bitwise AND between the read result and the value specified by AndData, and
141 writes the result to the 8-bit PCI configuration register specified by
142 Address. The value written to the PCI configuration register is returned.
143 This function must guarantee that all PCI read and write operations are
146 If Address > 0x0FFFFFFF, then ASSERT().
148 @param Address Address that encodes the PCI Bus, Device, Function and
150 @param AndData The value to AND with the PCI configuration register.
152 @return The value written back to the PCI configuration register.
162 ASSERT_INVALID_PCI_ADDRESS (Address
);
163 return MmioAnd8 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
167 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
168 value, followed a bitwise inclusive OR with another 8-bit value.
170 Reads the 8-bit PCI configuration register specified by Address, performs a
171 bitwise AND between the read result and the value specified by AndData,
172 performs a bitwise inclusive OR between the result of the AND operation and
173 the value specified by OrData, and writes the result to the 8-bit PCI
174 configuration register specified by Address. The value written to the PCI
175 configuration register is returned. This function must guarantee that all PCI
176 read and write operations are serialized.
178 If Address > 0x0FFFFFFF, then ASSERT().
180 @param Address Address that encodes the PCI Bus, Device, Function and
182 @param AndData The value to AND with the PCI configuration register.
183 @param OrData The value to OR with the result of the AND operation.
185 @return The value written back to the PCI configuration register.
190 PciExpressAndThenOr8 (
196 ASSERT_INVALID_PCI_ADDRESS (Address
);
197 return MmioAndThenOr8 (
198 (UINTN
) GetPciExpressBaseAddress () + Address
,
205 Reads a bit field of a PCI configuration register.
207 Reads the bit field in an 8-bit PCI configuration register. The bit field is
208 specified by the StartBit and the EndBit. The value of the bit field is
211 If Address > 0x0FFFFFFF, then ASSERT().
212 If StartBit is greater than 7, then ASSERT().
213 If EndBit is greater than 7, then ASSERT().
214 If EndBit is less than StartBit, then ASSERT().
216 @param Address PCI configuration register to read.
217 @param StartBit The ordinal of the least significant bit in the bit field.
219 @param EndBit The ordinal of the most significant bit in the bit field.
222 @return The value of the bit field read from the PCI configuration register.
227 PciExpressBitFieldRead8 (
233 ASSERT_INVALID_PCI_ADDRESS (Address
);
234 return MmioBitFieldRead8 (
235 (UINTN
) GetPciExpressBaseAddress () + Address
,
242 Writes a bit field to a PCI configuration register.
244 Writes Value to the bit field of the PCI configuration register. The bit
245 field is specified by the StartBit and the EndBit. All other bits in the
246 destination PCI configuration register are preserved. The new value of the
247 8-bit register is returned.
249 If Address > 0x0FFFFFFF, then ASSERT().
250 If StartBit is greater than 7, then ASSERT().
251 If EndBit is greater than 7, then ASSERT().
252 If EndBit is less than StartBit, then ASSERT().
254 @param Address PCI configuration register to write.
255 @param StartBit The ordinal of the least significant bit in the bit field.
257 @param EndBit The ordinal of the most significant bit in the bit field.
259 @param Value New value of the bit field.
261 @return The value written back to the PCI configuration register.
266 PciExpressBitFieldWrite8 (
273 ASSERT_INVALID_PCI_ADDRESS (Address
);
274 return MmioBitFieldWrite8 (
275 (UINTN
) GetPciExpressBaseAddress () + Address
,
283 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
284 writes the result back to the bit field in the 8-bit port.
286 Reads the 8-bit PCI configuration register specified by Address, performs a
287 bitwise inclusive OR between the read result and the value specified by
288 OrData, and writes the result to the 8-bit PCI configuration register
289 specified by Address. The value written to the PCI configuration register is
290 returned. This function must guarantee that all PCI read and write operations
291 are serialized. Extra left bits in OrData are stripped.
293 If Address > 0x0FFFFFFF, then ASSERT().
294 If StartBit is greater than 7, then ASSERT().
295 If EndBit is greater than 7, then ASSERT().
296 If EndBit is less than StartBit, then ASSERT().
298 @param Address PCI configuration register to write.
299 @param StartBit The ordinal of the least significant bit in the bit field.
301 @param EndBit The ordinal of the most significant bit in the bit field.
303 @param OrData The value to OR with the PCI configuration register.
305 @return The value written back to the PCI configuration register.
310 PciExpressBitFieldOr8 (
317 ASSERT_INVALID_PCI_ADDRESS (Address
);
318 return MmioBitFieldOr8 (
319 (UINTN
) GetPciExpressBaseAddress () + Address
,
327 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
328 AND, and writes the result back to the bit field in the 8-bit register.
330 Reads the 8-bit PCI configuration register specified by Address, performs a
331 bitwise AND between the read result and the value specified by AndData, and
332 writes the result to the 8-bit PCI configuration register specified by
333 Address. The value written to the PCI configuration register is returned.
334 This function must guarantee that all PCI read and write operations are
335 serialized. Extra left bits in AndData are stripped.
337 If Address > 0x0FFFFFFF, then ASSERT().
338 If StartBit is greater than 7, then ASSERT().
339 If EndBit is greater than 7, then ASSERT().
340 If EndBit is less than StartBit, then ASSERT().
342 @param Address PCI configuration register to write.
343 @param StartBit The ordinal of the least significant bit in the bit field.
345 @param EndBit The ordinal of the most significant bit in the bit field.
347 @param AndData The value to AND with the PCI configuration register.
349 @return The value written back to the PCI configuration register.
354 PciExpressBitFieldAnd8 (
361 ASSERT_INVALID_PCI_ADDRESS (Address
);
362 return MmioBitFieldAnd8 (
363 (UINTN
) GetPciExpressBaseAddress () + Address
,
371 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
372 bitwise inclusive OR, and writes the result back to the bit field in the
375 Reads the 8-bit PCI configuration register specified by Address, performs a
376 bitwise AND followed by a bitwise inclusive OR between the read result and
377 the value specified by AndData, and writes the result to the 8-bit PCI
378 configuration register specified by Address. The value written to the PCI
379 configuration register is returned. This function must guarantee that all PCI
380 read and write operations are serialized. Extra left bits in both AndData and
383 If Address > 0x0FFFFFFF, then ASSERT().
384 If StartBit is greater than 7, then ASSERT().
385 If EndBit is greater than 7, then ASSERT().
386 If EndBit is less than StartBit, then ASSERT().
388 @param Address PCI configuration register to write.
389 @param StartBit The ordinal of the least significant bit in the bit field.
391 @param EndBit The ordinal of the most significant bit in the bit field.
393 @param AndData The value to AND with the PCI configuration register.
394 @param OrData The value to OR with the result of the AND operation.
396 @return The value written back to the PCI configuration register.
401 PciExpressBitFieldAndThenOr8 (
409 ASSERT_INVALID_PCI_ADDRESS (Address
);
410 return MmioBitFieldAndThenOr8 (
411 (UINTN
) GetPciExpressBaseAddress () + Address
,
420 Reads a 16-bit PCI configuration register.
422 Reads and returns the 16-bit PCI configuration register specified by Address.
423 This function must guarantee that all PCI read and write operations are
426 If Address > 0x0FFFFFFF, then ASSERT().
427 If Address is not aligned on a 16-bit boundary, then ASSERT().
429 @param Address Address that encodes the PCI Bus, Device, Function and
432 @return The read value from the PCI configuration register.
441 ASSERT_INVALID_PCI_ADDRESS (Address
);
442 return MmioRead16 ((UINTN
) GetPciExpressBaseAddress () + Address
);
446 Writes a 16-bit PCI configuration register.
448 Writes the 16-bit PCI configuration register specified by Address with the
449 value specified by Value. Value is returned. This function must guarantee
450 that all PCI read and write operations are serialized.
452 If Address > 0x0FFFFFFF, then ASSERT().
453 If Address is not aligned on a 16-bit boundary, then ASSERT().
455 @param Address Address that encodes the PCI Bus, Device, Function and
457 @param Value The value to write.
459 @return The value written to the PCI configuration register.
469 ASSERT_INVALID_PCI_ADDRESS (Address
);
470 return MmioWrite16 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
474 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
477 Reads the 16-bit PCI configuration register specified by Address, performs a
478 bitwise inclusive OR between the read result and the value specified by
479 OrData, and writes the result to the 16-bit PCI configuration register
480 specified by Address. The value written to the PCI configuration register is
481 returned. This function must guarantee that all PCI read and write operations
484 If Address > 0x0FFFFFFF, then ASSERT().
485 If Address is not aligned on a 16-bit boundary, then ASSERT().
487 @param Address Address that encodes the PCI Bus, Device, Function and
489 @param OrData The value to OR with the PCI configuration register.
491 @return The value written back to the PCI configuration register.
501 ASSERT_INVALID_PCI_ADDRESS (Address
);
502 return MmioOr16 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
506 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
509 Reads the 16-bit PCI configuration register specified by Address, performs a
510 bitwise AND between the read result and the value specified by AndData, and
511 writes the result to the 16-bit PCI configuration register specified by
512 Address. The value written to the PCI configuration register is returned.
513 This function must guarantee that all PCI read and write operations are
516 If Address > 0x0FFFFFFF, then ASSERT().
517 If Address is not aligned on a 16-bit boundary, then ASSERT().
519 @param Address Address that encodes the PCI Bus, Device, Function and
521 @param AndData The value to AND with the PCI configuration register.
523 @return The value written back to the PCI configuration register.
533 ASSERT_INVALID_PCI_ADDRESS (Address
);
534 return MmioAnd16 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
538 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
539 value, followed a bitwise inclusive OR with another 16-bit value.
541 Reads the 16-bit PCI configuration register specified by Address, performs a
542 bitwise AND between the read result and the value specified by AndData,
543 performs a bitwise inclusive OR between the result of the AND operation and
544 the value specified by OrData, and writes the result to the 16-bit PCI
545 configuration register specified by Address. The value written to the PCI
546 configuration register is returned. This function must guarantee that all PCI
547 read and write operations are serialized.
549 If Address > 0x0FFFFFFF, then ASSERT().
550 If Address is not aligned on a 16-bit boundary, then ASSERT().
552 @param Address Address that encodes the PCI Bus, Device, Function and
554 @param AndData The value to AND with the PCI configuration register.
555 @param OrData The value to OR with the result of the AND operation.
557 @return The value written back to the PCI configuration register.
562 PciExpressAndThenOr16 (
568 ASSERT_INVALID_PCI_ADDRESS (Address
);
569 return MmioAndThenOr16 (
570 (UINTN
) GetPciExpressBaseAddress () + Address
,
577 Reads a bit field of a PCI configuration register.
579 Reads the bit field in a 16-bit PCI configuration register. The bit field is
580 specified by the StartBit and the EndBit. The value of the bit field is
583 If Address > 0x0FFFFFFF, then ASSERT().
584 If Address is not aligned on a 16-bit boundary, then ASSERT().
585 If StartBit is greater than 15, then ASSERT().
586 If EndBit is greater than 15, then ASSERT().
587 If EndBit is less than StartBit, then ASSERT().
589 @param Address PCI configuration register to read.
590 @param StartBit The ordinal of the least significant bit in the bit field.
592 @param EndBit The ordinal of the most significant bit in the bit field.
595 @return The value of the bit field read from the PCI configuration register.
600 PciExpressBitFieldRead16 (
606 ASSERT_INVALID_PCI_ADDRESS (Address
);
607 return MmioBitFieldRead16 (
608 (UINTN
) GetPciExpressBaseAddress () + Address
,
615 Writes a bit field to a PCI configuration register.
617 Writes Value to the bit field of the PCI configuration register. The bit
618 field is specified by the StartBit and the EndBit. All other bits in the
619 destination PCI configuration register are preserved. The new value of the
620 16-bit register is returned.
622 If Address > 0x0FFFFFFF, then ASSERT().
623 If Address is not aligned on a 16-bit boundary, then ASSERT().
624 If StartBit is greater than 15, then ASSERT().
625 If EndBit is greater than 15, then ASSERT().
626 If EndBit is less than StartBit, then ASSERT().
628 @param Address PCI configuration register to write.
629 @param StartBit The ordinal of the least significant bit in the bit field.
631 @param EndBit The ordinal of the most significant bit in the bit field.
633 @param Value New value of the bit field.
635 @return The value written back to the PCI configuration register.
640 PciExpressBitFieldWrite16 (
647 ASSERT_INVALID_PCI_ADDRESS (Address
);
648 return MmioBitFieldWrite16 (
649 (UINTN
) GetPciExpressBaseAddress () + Address
,
657 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
658 writes the result back to the bit field in the 16-bit port.
660 Reads the 16-bit PCI configuration register specified by Address, performs a
661 bitwise inclusive OR between the read result and the value specified by
662 OrData, and writes the result to the 16-bit PCI configuration register
663 specified by Address. The value written to the PCI configuration register is
664 returned. This function must guarantee that all PCI read and write operations
665 are serialized. Extra left bits in OrData are stripped.
667 If Address > 0x0FFFFFFF, then ASSERT().
668 If Address is not aligned on a 16-bit boundary, then ASSERT().
669 If StartBit is greater than 15, then ASSERT().
670 If EndBit is greater than 15, then ASSERT().
671 If EndBit is less than StartBit, then ASSERT().
673 @param Address PCI configuration register to write.
674 @param StartBit The ordinal of the least significant bit in the bit field.
676 @param EndBit The ordinal of the most significant bit in the bit field.
678 @param OrData The value to OR with the PCI configuration register.
680 @return The value written back to the PCI configuration register.
685 PciExpressBitFieldOr16 (
692 ASSERT_INVALID_PCI_ADDRESS (Address
);
693 return MmioBitFieldOr16 (
694 (UINTN
) GetPciExpressBaseAddress () + Address
,
702 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
703 AND, and writes the result back to the bit field in the 16-bit register.
705 Reads the 16-bit PCI configuration register specified by Address, performs a
706 bitwise AND between the read result and the value specified by AndData, and
707 writes the result to the 16-bit PCI configuration register specified by
708 Address. The value written to the PCI configuration register is returned.
709 This function must guarantee that all PCI read and write operations are
710 serialized. Extra left bits in AndData are stripped.
712 If Address > 0x0FFFFFFF, then ASSERT().
713 If Address is not aligned on a 16-bit boundary, then ASSERT().
714 If StartBit is greater than 15, then ASSERT().
715 If EndBit is greater than 15, then ASSERT().
716 If EndBit is less than StartBit, then ASSERT().
718 @param Address PCI configuration register to write.
719 @param StartBit The ordinal of the least significant bit in the bit field.
721 @param EndBit The ordinal of the most significant bit in the bit field.
723 @param AndData The value to AND with the PCI configuration register.
725 @return The value written back to the PCI configuration register.
730 PciExpressBitFieldAnd16 (
737 ASSERT_INVALID_PCI_ADDRESS (Address
);
738 return MmioBitFieldAnd16 (
739 (UINTN
) GetPciExpressBaseAddress () + Address
,
747 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
748 bitwise inclusive OR, and writes the result back to the bit field in the
751 Reads the 16-bit PCI configuration register specified by Address, performs a
752 bitwise AND followed by a bitwise inclusive OR between the read result and
753 the value specified by AndData, and writes the result to the 16-bit PCI
754 configuration register specified by Address. The value written to the PCI
755 configuration register is returned. This function must guarantee that all PCI
756 read and write operations are serialized. Extra left bits in both AndData and
759 If Address > 0x0FFFFFFF, then ASSERT().
760 If Address is not aligned on a 16-bit boundary, then ASSERT().
761 If StartBit is greater than 15, then ASSERT().
762 If EndBit is greater than 15, then ASSERT().
763 If EndBit is less than StartBit, then ASSERT().
765 @param Address PCI configuration register to write.
766 @param StartBit The ordinal of the least significant bit in the bit field.
768 @param EndBit The ordinal of the most significant bit in the bit field.
770 @param AndData The value to AND with the PCI configuration register.
771 @param OrData The value to OR with the result of the AND operation.
773 @return The value written back to the PCI configuration register.
778 PciExpressBitFieldAndThenOr16 (
786 ASSERT_INVALID_PCI_ADDRESS (Address
);
787 return MmioBitFieldAndThenOr16 (
788 (UINTN
) GetPciExpressBaseAddress () + Address
,
797 Reads a 32-bit PCI configuration register.
799 Reads and returns the 32-bit PCI configuration register specified by Address.
800 This function must guarantee that all PCI read and write operations are
803 If Address > 0x0FFFFFFF, then ASSERT().
804 If Address is not aligned on a 32-bit boundary, then ASSERT().
806 @param Address Address that encodes the PCI Bus, Device, Function and
809 @return The read value from the PCI configuration register.
818 ASSERT_INVALID_PCI_ADDRESS (Address
);
819 return MmioRead32 ((UINTN
) GetPciExpressBaseAddress () + Address
);
823 Writes a 32-bit PCI configuration register.
825 Writes the 32-bit PCI configuration register specified by Address with the
826 value specified by Value. Value is returned. This function must guarantee
827 that all PCI read and write operations are serialized.
829 If Address > 0x0FFFFFFF, then ASSERT().
830 If Address is not aligned on a 32-bit boundary, then ASSERT().
832 @param Address Address that encodes the PCI Bus, Device, Function and
834 @param Value The value to write.
836 @return The value written to the PCI configuration register.
846 ASSERT_INVALID_PCI_ADDRESS (Address
);
847 return MmioWrite32 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
851 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
854 Reads the 32-bit PCI configuration register specified by Address, performs a
855 bitwise inclusive OR between the read result and the value specified by
856 OrData, and writes the result to the 32-bit PCI configuration register
857 specified by Address. The value written to the PCI configuration register is
858 returned. This function must guarantee that all PCI read and write operations
861 If Address > 0x0FFFFFFF, then ASSERT().
862 If Address is not aligned on a 32-bit boundary, then ASSERT().
864 @param Address Address that encodes the PCI Bus, Device, Function and
866 @param OrData The value to OR with the PCI configuration register.
868 @return The value written back to the PCI configuration register.
878 ASSERT_INVALID_PCI_ADDRESS (Address
);
879 return MmioOr32 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
883 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
886 Reads the 32-bit PCI configuration register specified by Address, performs a
887 bitwise AND between the read result and the value specified by AndData, and
888 writes the result to the 32-bit PCI configuration register specified by
889 Address. The value written to the PCI configuration register is returned.
890 This function must guarantee that all PCI read and write operations are
893 If Address > 0x0FFFFFFF, then ASSERT().
894 If Address is not aligned on a 32-bit boundary, then ASSERT().
896 @param Address Address that encodes the PCI Bus, Device, Function and
898 @param AndData The value to AND with the PCI configuration register.
900 @return The value written back to the PCI configuration register.
910 ASSERT_INVALID_PCI_ADDRESS (Address
);
911 return MmioAnd32 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
915 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
916 value, followed a bitwise inclusive OR with another 32-bit value.
918 Reads the 32-bit PCI configuration register specified by Address, performs a
919 bitwise AND between the read result and the value specified by AndData,
920 performs a bitwise inclusive OR between the result of the AND operation and
921 the value specified by OrData, and writes the result to the 32-bit PCI
922 configuration register specified by Address. The value written to the PCI
923 configuration register is returned. This function must guarantee that all PCI
924 read and write operations are serialized.
926 If Address > 0x0FFFFFFF, then ASSERT().
927 If Address is not aligned on a 32-bit boundary, then ASSERT().
929 @param Address Address that encodes the PCI Bus, Device, Function and
931 @param AndData The value to AND with the PCI configuration register.
932 @param OrData The value to OR with the result of the AND operation.
934 @return The value written back to the PCI configuration register.
939 PciExpressAndThenOr32 (
945 ASSERT_INVALID_PCI_ADDRESS (Address
);
946 return MmioAndThenOr32 (
947 (UINTN
) GetPciExpressBaseAddress () + Address
,
954 Reads a bit field of a PCI configuration register.
956 Reads the bit field in a 32-bit PCI configuration register. The bit field is
957 specified by the StartBit and the EndBit. The value of the bit field is
960 If Address > 0x0FFFFFFF, then ASSERT().
961 If Address is not aligned on a 32-bit boundary, then ASSERT().
962 If StartBit is greater than 31, then ASSERT().
963 If EndBit is greater than 31, then ASSERT().
964 If EndBit is less than StartBit, then ASSERT().
966 @param Address PCI configuration register to read.
967 @param StartBit The ordinal of the least significant bit in the bit field.
969 @param EndBit The ordinal of the most significant bit in the bit field.
972 @return The value of the bit field read from the PCI configuration register.
977 PciExpressBitFieldRead32 (
983 ASSERT_INVALID_PCI_ADDRESS (Address
);
984 return MmioBitFieldRead32 (
985 (UINTN
) GetPciExpressBaseAddress () + Address
,
992 Writes a bit field to a PCI configuration register.
994 Writes Value to the bit field of the PCI configuration register. The bit
995 field is specified by the StartBit and the EndBit. All other bits in the
996 destination PCI configuration register are preserved. The new value of the
997 32-bit register is returned.
999 If Address > 0x0FFFFFFF, then ASSERT().
1000 If Address is not aligned on a 32-bit boundary, then ASSERT().
1001 If StartBit is greater than 31, then ASSERT().
1002 If EndBit is greater than 31, then ASSERT().
1003 If EndBit is less than StartBit, then ASSERT().
1005 @param Address PCI configuration register to write.
1006 @param StartBit The ordinal of the least significant bit in the bit field.
1008 @param EndBit The ordinal of the most significant bit in the bit field.
1010 @param Value New value of the bit field.
1012 @return The value written back to the PCI configuration register.
1017 PciExpressBitFieldWrite32 (
1024 ASSERT_INVALID_PCI_ADDRESS (Address
);
1025 return MmioBitFieldWrite32 (
1026 (UINTN
) GetPciExpressBaseAddress () + Address
,
1034 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1035 writes the result back to the bit field in the 32-bit port.
1037 Reads the 32-bit PCI configuration register specified by Address, performs a
1038 bitwise inclusive OR between the read result and the value specified by
1039 OrData, and writes the result to the 32-bit PCI configuration register
1040 specified by Address. The value written to the PCI configuration register is
1041 returned. This function must guarantee that all PCI read and write operations
1042 are serialized. Extra left bits in OrData are stripped.
1044 If Address > 0x0FFFFFFF, then ASSERT().
1045 If Address is not aligned on a 32-bit boundary, then ASSERT().
1046 If StartBit is greater than 31, then ASSERT().
1047 If EndBit is greater than 31, then ASSERT().
1048 If EndBit is less than StartBit, then ASSERT().
1050 @param Address PCI configuration register to write.
1051 @param StartBit The ordinal of the least significant bit in the bit field.
1053 @param EndBit The ordinal of the most significant bit in the bit field.
1055 @param OrData The value to OR with the PCI configuration register.
1057 @return The value written back to the PCI configuration register.
1062 PciExpressBitFieldOr32 (
1069 ASSERT_INVALID_PCI_ADDRESS (Address
);
1070 return MmioBitFieldOr32 (
1071 (UINTN
) GetPciExpressBaseAddress () + Address
,
1079 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1080 AND, and writes the result back to the bit field in the 32-bit register.
1082 Reads the 32-bit PCI configuration register specified by Address, performs a
1083 bitwise AND between the read result and the value specified by AndData, and
1084 writes the result to the 32-bit PCI configuration register specified by
1085 Address. The value written to the PCI configuration register is returned.
1086 This function must guarantee that all PCI read and write operations are
1087 serialized. Extra left bits in AndData are stripped.
1089 If Address > 0x0FFFFFFF, then ASSERT().
1090 If Address is not aligned on a 32-bit boundary, then ASSERT().
1091 If StartBit is greater than 31, then ASSERT().
1092 If EndBit is greater than 31, then ASSERT().
1093 If EndBit is less than StartBit, then ASSERT().
1095 @param Address PCI configuration register to write.
1096 @param StartBit The ordinal of the least significant bit in the bit field.
1098 @param EndBit The ordinal of the most significant bit in the bit field.
1100 @param AndData The value to AND with the PCI configuration register.
1102 @return The value written back to the PCI configuration register.
1107 PciExpressBitFieldAnd32 (
1114 ASSERT_INVALID_PCI_ADDRESS (Address
);
1115 return MmioBitFieldAnd32 (
1116 (UINTN
) GetPciExpressBaseAddress () + Address
,
1124 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1125 bitwise inclusive OR, and writes the result back to the bit field in the
1128 Reads the 32-bit PCI configuration register specified by Address, performs a
1129 bitwise AND followed by a bitwise inclusive OR between the read result and
1130 the value specified by AndData, and writes the result to the 32-bit PCI
1131 configuration register specified by Address. The value written to the PCI
1132 configuration register is returned. This function must guarantee that all PCI
1133 read and write operations are serialized. Extra left bits in both AndData and
1134 OrData are stripped.
1136 If Address > 0x0FFFFFFF, then ASSERT().
1137 If Address is not aligned on a 32-bit boundary, then ASSERT().
1138 If StartBit is greater than 31, then ASSERT().
1139 If EndBit is greater than 31, then ASSERT().
1140 If EndBit is less than StartBit, then ASSERT().
1142 @param Address PCI configuration register to write.
1143 @param StartBit The ordinal of the least significant bit in the bit field.
1145 @param EndBit The ordinal of the most significant bit in the bit field.
1147 @param AndData The value to AND with the PCI configuration register.
1148 @param OrData The value to OR with the result of the AND operation.
1150 @return The value written back to the PCI configuration register.
1155 PciExpressBitFieldAndThenOr32 (
1163 ASSERT_INVALID_PCI_ADDRESS (Address
);
1164 return MmioBitFieldAndThenOr32 (
1165 (UINTN
) GetPciExpressBaseAddress () + Address
,
1174 Reads a range of PCI configuration registers into a caller supplied buffer.
1176 Reads the range of PCI configuration registers specified by StartAddress and
1177 Size into the buffer specified by Buffer. This function only allows the PCI
1178 configuration registers from a single PCI function to be read. Size is
1179 returned. When possible 32-bit PCI configuration read cycles are used to read
1180 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1181 and 16-bit PCI configuration read cycles may be used at the beginning and the
1184 If StartAddress > 0x0FFFFFFF, then ASSERT().
1185 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1186 If Size > 0 and Buffer is NULL, then ASSERT().
1188 @param StartAddress Starting address that encodes the PCI Bus, Device,
1189 Function and Register.
1190 @param Size Size in bytes of the transfer.
1191 @param Buffer Pointer to a buffer receiving the data read.
1198 PciExpressReadBuffer (
1199 IN UINTN StartAddress
,
1206 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1207 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1213 ASSERT (Buffer
!= NULL
);
1216 // Save Size for return
1220 if ((StartAddress
& 1) != 0) {
1222 // Read a byte if StartAddress is byte aligned
1224 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1225 StartAddress
+= sizeof (UINT8
);
1226 Size
-= sizeof (UINT8
);
1227 Buffer
= (UINT8
*)Buffer
+ 1;
1230 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1232 // Read a word if StartAddress is word aligned
1234 *(volatile UINT16
*)Buffer
= PciExpressRead16 (StartAddress
);
1235 StartAddress
+= sizeof (UINT16
);
1236 Size
-= sizeof (UINT16
);
1237 Buffer
= (UINT16
*)Buffer
+ 1;
1240 while (Size
>= sizeof (UINT32
)) {
1242 // Read as many double words as possible
1244 *(volatile UINT32
*)Buffer
= PciExpressRead32 (StartAddress
);
1245 StartAddress
+= sizeof (UINT32
);
1246 Size
-= sizeof (UINT32
);
1247 Buffer
= (UINT32
*)Buffer
+ 1;
1250 if (Size
>= sizeof (UINT16
)) {
1252 // Read the last remaining word if exist
1254 *(volatile UINT16
*)Buffer
= PciExpressRead16 (StartAddress
);
1255 StartAddress
+= sizeof (UINT16
);
1256 Size
-= sizeof (UINT16
);
1257 Buffer
= (UINT16
*)Buffer
+ 1;
1260 if (Size
>= sizeof (UINT8
)) {
1262 // Read the last remaining byte if exist
1264 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1271 Copies the data in a caller supplied buffer to a specified range of PCI
1272 configuration space.
1274 Writes the range of PCI configuration registers specified by StartAddress and
1275 Size from the buffer specified by Buffer. This function only allows the PCI
1276 configuration registers from a single PCI function to be written. Size is
1277 returned. When possible 32-bit PCI configuration write cycles are used to
1278 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1279 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1280 and the end of the range.
1282 If StartAddress > 0x0FFFFFFF, then ASSERT().
1283 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1284 If Size > 0 and Buffer is NULL, then ASSERT().
1286 @param StartAddress Starting address that encodes the PCI Bus, Device,
1287 Function and Register.
1288 @param Size Size in bytes of the transfer.
1289 @param Buffer Pointer to a buffer containing the data to write.
1296 PciExpressWriteBuffer (
1297 IN UINTN StartAddress
,
1304 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1305 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1311 ASSERT (Buffer
!= NULL
);
1314 // Save Size for return
1318 if ((StartAddress
& 1) != 0) {
1320 // Write a byte if StartAddress is byte aligned
1322 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1323 StartAddress
+= sizeof (UINT8
);
1324 Size
-= sizeof (UINT8
);
1325 Buffer
= (UINT8
*)Buffer
+ 1;
1328 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1330 // Write a word if StartAddress is word aligned
1332 PciExpressWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1333 StartAddress
+= sizeof (UINT16
);
1334 Size
-= sizeof (UINT16
);
1335 Buffer
= (UINT16
*)Buffer
+ 1;
1338 while (Size
>= sizeof (UINT32
)) {
1340 // Write as many double words as possible
1342 PciExpressWrite32 (StartAddress
, *(UINT32
*)Buffer
);
1343 StartAddress
+= sizeof (UINT32
);
1344 Size
-= sizeof (UINT32
);
1345 Buffer
= (UINT32
*)Buffer
+ 1;
1348 if (Size
>= sizeof (UINT16
)) {
1350 // Write the last remaining word if exist
1352 PciExpressWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1353 StartAddress
+= sizeof (UINT16
);
1354 Size
-= sizeof (UINT16
);
1355 Buffer
= (UINT16
*)Buffer
+ 1;
1358 if (Size
>= sizeof (UINT8
)) {
1360 // Write the last remaining byte if exist
1362 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);