2 Abstractions for simple OMAP DMA channel.
5 Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
7 SPDX-License-Identifier: BSD-2-Clause-Patent
12 #include <Library/DebugLib.h>
13 #include <Library/OmapDmaLib.h>
14 #include <Library/IoLib.h>
15 #include <Library/BaseMemoryLib.h>
16 #include <Omap3530/Omap3530.h>
20 Configure OMAP DMA Channel
22 @param Channel DMA Channel to configure
23 @param Dma4 Pointer to structure used to initialize DMA registers for the Channel
25 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
26 @retval EFI_INVALID_PARAMETER Channel is not valid
27 @retval EFI_DEVICE_ERROR The system hardware could not map the requested information.
40 if (Channel
> DMA4_MAX_CHANNEL
) {
41 return EFI_INVALID_PARAMETER
;
44 /* 1) Configure the transfer parameters in the logical DMA registers */
45 /*-------------------------------------------------------------------*/
47 /* a) Set the data type CSDP[1:0], the Read/Write Port access type
48 CSDP[8:7]/[15:14], the Source/dest endianism CSDP[21]/CSDP[19],
49 write mode CSDP[17:16], source/dest packed or nonpacked CSDP[6]/CSDP[13] */
52 RegVal
= MmioRead32 (DMA4_CSDP (Channel
));
55 RegVal
= ((RegVal
& ~ 0x3) | DMA4
->DataType
);
56 RegVal
= ((RegVal
& ~(0x3 << 7)) | (DMA4
->ReadPortAccessType
<< 7));
57 RegVal
= ((RegVal
& ~(0x3 << 14)) | (DMA4
->WritePortAccessType
<< 14));
58 RegVal
= ((RegVal
& ~(0x1 << 21)) | (DMA4
->SourceEndiansim
<< 21));
59 RegVal
= ((RegVal
& ~(0x1 << 19)) | (DMA4
->DestinationEndianism
<< 19));
60 RegVal
= ((RegVal
& ~(0x3 << 16)) | (DMA4
->WriteMode
<< 16));
61 RegVal
= ((RegVal
& ~(0x1 << 6)) | (DMA4
->SourcePacked
<< 6));
62 RegVal
= ((RegVal
& ~(0x1 << 13)) | (DMA4
->DestinationPacked
<< 13));
64 MmioWrite32 (DMA4_CSDP (Channel
), RegVal
);
66 /* b) Set the number of element per frame CEN[23:0]*/
67 MmioWrite32 (DMA4_CEN (Channel
), DMA4
->NumberOfElementPerFrame
);
69 /* c) Set the number of frame per block CFN[15:0]*/
70 MmioWrite32 (DMA4_CFN (Channel
), DMA4
->NumberOfFramePerTransferBlock
);
72 /* d) Set the Source/dest start address index CSSA[31:0]/CDSA[31:0]*/
73 MmioWrite32 (DMA4_CSSA (Channel
), DMA4
->SourceStartAddress
);
74 MmioWrite32 (DMA4_CDSA (Channel
), DMA4
->DestinationStartAddress
);
76 /* e) Set the Read Port addressing mode CCR[13:12], the Write Port addressing mode CCR[15:14],
77 read/write priority CCR[6]/CCR[26]
78 I changed LCH CCR[20:19]=00 and CCR[4:0]=00000 to
79 LCH CCR[20:19]= DMA4->WriteRequestNumber and CCR[4:0]=DMA4->ReadRequestNumber
83 RegVal
= MmioRead32 (DMA4_CCR (Channel
));
86 RegVal
= ((RegVal
& ~0x1f) | DMA4
->ReadRequestNumber
);
87 RegVal
= ((RegVal
& ~(BIT20
| BIT19
)) | DMA4
->WriteRequestNumber
<< 19);
88 RegVal
= ((RegVal
& ~(0x3 << 12)) | (DMA4
->ReadPortAccessMode
<< 12));
89 RegVal
= ((RegVal
& ~(0x3 << 14)) | (DMA4
->WritePortAccessMode
<< 14));
90 RegVal
= ((RegVal
& ~(0x1 << 6)) | (DMA4
->ReadPriority
<< 6));
91 RegVal
= ((RegVal
& ~(0x1 << 26)) | (DMA4
->WritePriority
<< 26));
94 MmioWrite32 (DMA4_CCR (Channel
), RegVal
);
96 /* f)- Set the source element index CSEI[15:0]*/
97 MmioWrite32 (DMA4_CSEI (Channel
), DMA4
->SourceElementIndex
);
99 /* - Set the source frame index CSFI[15:0]*/
100 MmioWrite32 (DMA4_CSFI (Channel
), DMA4
->SourceFrameIndex
);
103 /* - Set the destination element index CDEI[15:0]*/
104 MmioWrite32 (DMA4_CDEI (Channel
), DMA4
->DestinationElementIndex
);
106 /* - Set the destination frame index CDFI[31:0]*/
107 MmioWrite32 (DMA4_CDFI (Channel
), DMA4
->DestinationFrameIndex
);
109 MmioWrite32 (DMA4_CDFI (Channel
), DMA4
->DestinationFrameIndex
);
111 // Enable all the status bits since we are polling
112 MmioWrite32 (DMA4_CICR (Channel
), DMA4_CICR_ENABLE_ALL
);
113 MmioWrite32 (DMA4_CSR (Channel
), DMA4_CSR_RESET
);
115 /* 2) Start the DMA transfer by Setting the enable bit CCR[7]=1 */
116 /*--------------------------------------------------------------*/
118 MmioOr32 (DMA4_CCR(Channel
), DMA4_CCR_ENABLE
); //Launch transfer
124 Turn of DMA channel configured by EnableDma().
126 @param Channel DMA Channel to configure
127 @param SuccesMask Bits in DMA4_CSR register indicate EFI_SUCCESS
128 @param ErrorMask Bits in DMA4_CSR register indicate EFI_DEVICE_ERROR
130 @retval EFI_SUCCESS DMA hardware disabled
131 @retval EFI_INVALID_PARAMETER Channel is not valid
132 @retval EFI_DEVICE_ERROR The system hardware could not map the requested information.
139 IN UINT32 SuccessMask
,
143 EFI_STATUS Status
= EFI_SUCCESS
;
147 if (Channel
> DMA4_MAX_CHANNEL
) {
148 return EFI_INVALID_PARAMETER
;
152 Reg
= MmioRead32 (DMA4_CSR(Channel
));
153 if ((Reg
& ErrorMask
) != 0) {
154 Status
= EFI_DEVICE_ERROR
;
155 DEBUG ((EFI_D_ERROR
, "DMA Error (%d) %x\n", Channel
, Reg
));
158 } while ((Reg
& SuccessMask
) != SuccessMask
);
161 // Disable all status bits and clear them
162 MmioWrite32 (DMA4_CICR (Channel
), 0);
163 MmioWrite32 (DMA4_CSR (Channel
), DMA4_CSR_RESET
);
165 MmioAnd32 (DMA4_CCR(0), ~(DMA4_CCR_ENABLE
| DMA4_CCR_RD_ACTIVE
| DMA4_CCR_WR_ACTIVE
));