OvmfPkg/AcpiTables/Facp.aslc

   1 /** @file
   2   FACP Table
   3
   4   Copyright (c) 2008 - 2009, Intel Corporation<BR> All rights
   5   reserved. This program and the accompanying materials are
   6   licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #include "Platform.h"
  16
  17 EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {
  18   EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
  19   sizeof (EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE),
  20   EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
  21   0,                // to make sum of entire table == 0
  22   EFI_ACPI_OEM_ID,         // OEMID is a 6 bytes long field
  23   EFI_ACPI_OEM_TABLE_ID,      // OEM table identification(8 bytes long)
  24   EFI_ACPI_OEM_REVISION,      // OEM revision number
  25   EFI_ACPI_CREATOR_ID,        // ASL compiler vendor ID
  26   EFI_ACPI_CREATOR_REVISION,  // ASL compiler revision number
  27   0,                // Physical addesss of FACS
  28   0,                // Physical address of DSDT
  29   INT_MODEL,        // System Interrupt Model
  30   RESERVED,         // reserved
  31   SCI_INT_VECTOR,   // System vector of SCI interrupt
  32   SMI_CMD_IO_PORT,  // Port address of SMI command port
  33   ACPI_ENABLE,      // value to write to port smi_cmd to enable ACPI
  34   ACPI_DISABLE,     // value to write to port smi_cmd to disable ACPI
  35   S4BIOS_REQ,       // Value to write to SMI CMD port to enter the S4BIOS state
  36   0xE2,             // PState control
  37   PM1a_EVT_BLK,     // Port address of Power Mgt 1a Event Reg Blk
  38   PM1b_EVT_BLK,     // Port address of Power Mgt 1b Event Reg Blk
  39   PM1a_CNT_BLK,     // Port address of Power Mgt 1a Ctrl Reg Blk
  40   PM1b_CNT_BLK,     // Port address of Power Mgt 1b Ctrl Reg Blk
  41   PM2_CNT_BLK,      // Port address of Power Mgt 2  Ctrl Reg Blk
  42   PM_TMR_BLK,       // Port address of Power Mgt Timer Ctrl Reg Blk
  43   GPE0_BLK,         // Port addr of General Purpose Event 0 Reg Blk
  44   GPE1_BLK,         // Port addr of General Purpose Event 1 Reg Blk
  45   PM1_EVT_LEN,      // Byte Length of ports at pm1X_evt_blk
  46   PM1_CNT_LEN,      // Byte Length of ports at pm1X_cnt_blk
  47   PM2_CNT_LEN,      // Byte Length of ports at pm2_cnt_blk
  48   PM_TM_LEN,        // Byte Length of ports at pm_tm_blk
  49   GPE0_BLK_LEN,     // Byte Length of ports at gpe0_blk
  50   GPE1_BLK_LEN,     // Byte Length of ports at gpe1_blk
  51   GPE1_BASE,        // offset in gpe model where gpe1 events start
  52   0xE3,             // _CST support
  53   P_LVL2_LAT,       // worst case HW latency to enter/exit C2 state
  54   P_LVL3_LAT,       // worst case HW latency to enter/exit C3 state
  55   FLUSH_SIZE,       // Size of area read to flush caches
  56   FLUSH_STRIDE,     // Stride used in flushing caches
  57   DUTY_OFFSET,      // bit location of duty cycle field in p_cnt reg
  58   DUTY_WIDTH,       // bit width of duty cycle field in p_cnt reg
  59   DAY_ALRM,         // index to day-of-month alarm in RTC CMOS RAM
  60   MON_ALRM,         // index to month-of-year alarm in RTC CMOS RAM
  61   CENTURY,          // index to century in RTC CMOS RAM
  62   0x03,             // Boot architecture flag
  63   0x00,             // Boot architecture flag
  64   RESERVED,         // reserved
  65   FLAG
  66 };
  67
  68
  69 VOID*
  70 ReferenceAcpiTable (
  71   VOID
  72   )
  73 {
  74   //
  75   // Reference the table being generated to prevent the optimizer from removing the
  76   // data structure from the exeutable
  77   //
  78   return (VOID*)&FACP;
  79 }