OvmfPkg/Bhyve/PlatformPei/Platform.c

   1 /**@file
   2   Platform PEI driver
   3
   4   Copyright (c) 2020, Rebecca Cran <rebecca@bsdio.com>
   5   Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
   6   Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
   7
   8   SPDX-License-Identifier: BSD-2-Clause-Patent
   9
  10 **/
  11
  12 //
  13 // The package level header files this module uses
  14 //
  15 #include <PiPei.h>
  16
  17 //
  18 // The Library classes this module consumes
  19 //
  20 #include <Library/BaseLib.h>
  21 #include <Library/DebugLib.h>
  22 #include <Library/HobLib.h>
  23 #include <Library/IoLib.h>
  24 #include <Library/LocalApicLib.h>
  25 #include <Library/MemoryAllocationLib.h>
  26 #include <Library/PcdLib.h>
  27 #include <Library/PciLib.h>
  28 #include <Library/PeimEntryPoint.h>
  29 #include <Library/PeiServicesLib.h>
  30 #include <Library/ResourcePublicationLib.h>
  31 #include <Guid/MemoryTypeInformation.h>
  32 #include <Ppi/MasterBootMode.h>
  33 #include <IndustryStandard/Pci22.h>
  34 #include <OvmfPlatforms.h>
  35
  36 #include "Platform.h"
  37 #include "Cmos.h"
  38
  39 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
  40   { EfiACPIMemoryNVS,       0x004 },
  41   { EfiACPIReclaimMemory,   0x008 },
  42   { EfiReservedMemoryType,  0x004 },
  43   { EfiRuntimeServicesData, 0x024 },
  44   { EfiRuntimeServicesCode, 0x030 },
  45   { EfiBootServicesCode,    0x180 },
  46   { EfiBootServicesData,    0xF00 },
  47   { EfiMaxMemoryType,       0x000 }
  48 };
  49
  50
  51 EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {
  52   {
  53     EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  54     &gEfiPeiMasterBootModePpiGuid,
  55     NULL
  56   }
  57 };
  58
  59
  60 UINT16 mHostBridgeDevId;
  61
  62 EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
  63
  64 BOOLEAN mS3Supported = FALSE;
  65
  66 UINT32 mMaxCpuCount;
  67
  68 VOID
  69 AddIoMemoryBaseSizeHob (
  70   EFI_PHYSICAL_ADDRESS        MemoryBase,
  71   UINT64                      MemorySize
  72   )
  73 {
  74   BuildResourceDescriptorHob (
  75     EFI_RESOURCE_MEMORY_MAPPED_IO,
  76       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  77       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  78       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  79       EFI_RESOURCE_ATTRIBUTE_TESTED,
  80     MemoryBase,
  81     MemorySize
  82     );
  83 }
  84
  85 VOID
  86 AddReservedMemoryBaseSizeHob (
  87   EFI_PHYSICAL_ADDRESS        MemoryBase,
  88   UINT64                      MemorySize,
  89   BOOLEAN                     Cacheable
  90   )
  91 {
  92   BuildResourceDescriptorHob (
  93     EFI_RESOURCE_MEMORY_RESERVED,
  94       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  95       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  96       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  97       (Cacheable ?
  98        EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
  99        EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 100        EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
 101        0
 102        ) |
 103       EFI_RESOURCE_ATTRIBUTE_TESTED,
 104     MemoryBase,
 105     MemorySize
 106     );
 107 }
 108
 109 VOID
 110 AddIoMemoryRangeHob (
 111   EFI_PHYSICAL_ADDRESS        MemoryBase,
 112   EFI_PHYSICAL_ADDRESS        MemoryLimit
 113   )
 114 {
 115   AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 116 }
 117
 118
 119 VOID
 120 AddMemoryBaseSizeHob (
 121   EFI_PHYSICAL_ADDRESS        MemoryBase,
 122   UINT64                      MemorySize
 123   )
 124 {
 125   BuildResourceDescriptorHob (
 126     EFI_RESOURCE_SYSTEM_MEMORY,
 127       EFI_RESOURCE_ATTRIBUTE_PRESENT |
 128       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 129       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 130       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 131       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 132       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
 133       EFI_RESOURCE_ATTRIBUTE_TESTED,
 134     MemoryBase,
 135     MemorySize
 136     );
 137 }
 138
 139
 140 VOID
 141 AddMemoryRangeHob (
 142   EFI_PHYSICAL_ADDRESS        MemoryBase,
 143   EFI_PHYSICAL_ADDRESS        MemoryLimit
 144   )
 145 {
 146   AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 147 }
 148
 149
 150 VOID
 151 MemMapInitialization (
 152   VOID
 153   )
 154 {
 155   UINT64        PciIoBase;
 156   UINT64        PciIoSize;
 157   RETURN_STATUS PcdStatus;
 158
 159   PciIoBase = 0xC000;
 160   PciIoSize = 0x4000;
 161
 162   //
 163   // Create Memory Type Information HOB
 164   //
 165   BuildGuidDataHob (
 166     &gEfiMemoryTypeInformationGuid,
 167     mDefaultMemoryTypeInformation,
 168     sizeof(mDefaultMemoryTypeInformation)
 169     );
 170
 171   //
 172   // Video memory + Legacy BIOS region
 173   //
 174   AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
 175
 176   if (TRUE) {
 177     UINT32  TopOfLowRam;
 178     UINT64  PciExBarBase;
 179     UINT32  PciBase;
 180     UINT32  PciSize;
 181
 182     TopOfLowRam = GetSystemMemorySizeBelow4gb ();
 183     PciExBarBase = 0;
 184     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 185       //
 186       // The MMCONFIG area is expected to fall between the top of low RAM and
 187       // the base of the 32-bit PCI host aperture.
 188       //
 189       PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);
 190       ASSERT (TopOfLowRam <= PciExBarBase);
 191       ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
 192       PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
 193     } else {
 194       PciBase = PcdGet64 (PcdPciMmio32Base);
 195       if (PciBase == 0)
 196         PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;
 197     }
 198
 199     //
 200     // address       purpose   size
 201     // ------------  --------  -------------------------
 202     // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)
 203     // 0xFC000000    gap                           44 MB
 204     // 0xFEC00000    IO-APIC                        4 KB
 205     // 0xFEC01000    gap                         1020 KB
 206     // 0xFED00000    HPET                           1 KB
 207     // 0xFED00400    gap                          111 KB
 208     // 0xFED1C000    gap (PIIX4) / RCRB (ICH9)     16 KB
 209     // 0xFED20000    gap                          896 KB
 210     // 0xFEE00000    LAPIC                          1 MB
 211     //
 212     PciSize = 0xFC000000 - PciBase;
 213     AddIoMemoryBaseSizeHob (PciBase, PciSize);
 214     PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);
 215     ASSERT_RETURN_ERROR (PcdStatus);
 216     PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize);
 217     ASSERT_RETURN_ERROR (PcdStatus);
 218
 219     AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
 220     AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
 221     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 222       AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
 223       //
 224       // Note: there should be an
 225       //
 226       //   AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
 227       //
 228       // call below, just like the one above for RCBA. However, Linux insists
 229       // that the MMCONFIG area be marked in the E820 or UEFI memory map as
 230       // "reserved memory" -- Linux does not content itself with a simple gap
 231       // in the memory map wherever the MCFG ACPI table points to.
 232       //
 233       // This appears to be a safety measure. The PCI Firmware Specification
 234       // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
 235       // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
 236       // [...]". (Emphasis added here.)
 237       //
 238       // Normally we add memory resource descriptor HOBs in
 239       // QemuInitializeRam(), and pre-allocate from those with memory
 240       // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
 241       // is most definitely not RAM; so, as an exception, cover it with
 242       // uncacheable reserved memory right here.
 243       //
 244       AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);
 245       BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,
 246         EfiReservedMemoryType);
 247     }
 248     AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
 249
 250     //
 251     // On Q35, the IO Port space is available for PCI resource allocations from
 252     // 0x6000 up.
 253     //
 254     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 255       PciIoBase = 0x6000;
 256       PciIoSize = 0xA000;
 257       ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);
 258     }
 259   }
 260
 261   //
 262   // Add PCI IO Port space available for PCI resource allocations.
 263   //
 264   BuildResourceDescriptorHob (
 265     EFI_RESOURCE_IO,
 266     EFI_RESOURCE_ATTRIBUTE_PRESENT     |
 267     EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
 268     PciIoBase,
 269     PciIoSize
 270     );
 271   PcdStatus = PcdSet64S (PcdPciIoBase, PciIoBase);
 272   ASSERT_RETURN_ERROR (PcdStatus);
 273   PcdStatus = PcdSet64S (PcdPciIoSize, PciIoSize);
 274   ASSERT_RETURN_ERROR (PcdStatus);
 275 }
 276
 277 VOID
 278 NoexecDxeInitialization (
 279   VOID
 280   )
 281 {
 282 }
 283
 284 VOID
 285 PciExBarInitialization (
 286   VOID
 287   )
 288 {
 289   union {
 290     UINT64 Uint64;
 291     UINT32 Uint32[2];
 292   } PciExBarBase;
 293
 294   //
 295   // We only support the 256MB size for the MMCONFIG area:
 296   // 256 buses * 32 devices * 8 functions * 4096 bytes config space.
 297   //
 298   // The masks used below enforce the Q35 requirements that the MMCONFIG area
 299   // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.
 300   //
 301   // Note that (b) also ensures that the minimum address width we have
 302   // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice
 303   // for DXE's page tables to cover the MMCONFIG area.
 304   //
 305   PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);
 306   ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);
 307   ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);
 308
 309   //
 310   // Clear the PCIEXBAREN bit first, before programming the high register.
 311   //
 312   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);
 313
 314   //
 315   // Program the high register. Then program the low register, setting the
 316   // MMCONFIG area size and enabling decoding at once.
 317   //
 318   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);
 319   PciWrite32 (
 320     DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),
 321     PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN
 322     );
 323 }
 324
 325 VOID
 326 MiscInitialization (
 327   VOID
 328   )
 329 {
 330   UINTN         PmCmd;
 331   UINTN         Pmba;
 332   UINT32        PmbaAndVal;
 333   UINT32        PmbaOrVal;
 334   UINTN         AcpiCtlReg;
 335   UINT8         AcpiEnBit;
 336   RETURN_STATUS PcdStatus;
 337
 338   //
 339   // Disable A20 Mask
 340   //
 341   IoOr8 (0x92, BIT1);
 342
 343   //
 344   // Build the CPU HOB with guest RAM size dependent address width and 16-bits
 345   // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
 346   // S3 resume as well, so we build it unconditionally.)
 347   //
 348   BuildCpuHob (mPhysMemAddressWidth, 16);
 349
 350   //
 351   // Determine platform type and save Host Bridge DID to PCD
 352   //
 353   switch (mHostBridgeDevId) {
 354     case 0x7432: // BHYVE (AMD hostbridge)
 355     case 0x1275: // BHYVE (Intel hostbridge)
 356     case INTEL_82441_DEVICE_ID:
 357       PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
 358       Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
 359       PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;
 360       PmbaOrVal  = PIIX4_PMBA_VALUE;
 361       AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
 362       AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;
 363       break;
 364     case INTEL_Q35_MCH_DEVICE_ID:
 365       PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
 366       Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
 367       PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;
 368       PmbaOrVal  = ICH9_PMBASE_VALUE;
 369       AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
 370       AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;
 371       break;
 372     default:
 373       DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
 374         __FUNCTION__, mHostBridgeDevId));
 375       ASSERT (FALSE);
 376       return;
 377   }
 378   PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
 379   ASSERT_RETURN_ERROR (PcdStatus);
 380
 381   //
 382   // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
 383   // has been configured (e.g., by Xen) and skip the setup here.
 384   // This matches the logic in AcpiTimerLibConstructor ().
 385   //
 386   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
 387     //
 388     // The PEI phase should be exited with fully accessibe ACPI PM IO space:
 389     // 1. set PMBA
 390     //
 391     PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);
 392
 393     //
 394     // 2. set PCICMD/IOSE
 395     //
 396     PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
 397
 398     //
 399     // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
 400     //
 401     PciOr8 (AcpiCtlReg, AcpiEnBit);
 402   }
 403
 404   if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 405     //
 406     // Set Root Complex Register Block BAR
 407     //
 408     PciWrite32 (
 409       POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),
 410       ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN
 411       );
 412
 413     //
 414     // Set PCI Express Register Range Base Address
 415     //
 416     PciExBarInitialization ();
 417   }
 418 }
 419
 420
 421 VOID
 422 BootModeInitialization (
 423   VOID
 424   )
 425 {
 426   EFI_STATUS    Status;
 427
 428   if (CmosRead8 (0xF) == 0xFE) {
 429     mBootMode = BOOT_ON_S3_RESUME;
 430   }
 431   CmosWrite8 (0xF, 0x00);
 432
 433   Status = PeiServicesSetBootMode (mBootMode);
 434   ASSERT_EFI_ERROR (Status);
 435
 436   Status = PeiServicesInstallPpi (mPpiBootMode);
 437   ASSERT_EFI_ERROR (Status);
 438 }
 439
 440
 441 VOID
 442 ReserveEmuVariableNvStore (
 443   )
 444 {
 445   EFI_PHYSICAL_ADDRESS VariableStore;
 446   RETURN_STATUS        PcdStatus;
 447
 448   //
 449   // Allocate storage for NV variables early on so it will be
 450   // at a consistent address.  Since VM memory is preserved
 451   // across reboots, this allows the NV variable storage to survive
 452   // a VM reboot.
 453   //
 454   VariableStore =
 455     (EFI_PHYSICAL_ADDRESS)(UINTN)
 456       AllocateRuntimePages (
 457         EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))
 458         );
 459   DEBUG ((DEBUG_INFO,
 460           "Reserved variable store memory: 0x%lX; size: %dkb\n",
 461           VariableStore,
 462           (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
 463         ));
 464   PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);
 465   ASSERT_RETURN_ERROR (PcdStatus);
 466 }
 467
 468
 469 VOID
 470 DebugDumpCmos (
 471   VOID
 472   )
 473 {
 474   UINT32 Loop;
 475
 476   DEBUG ((DEBUG_INFO, "CMOS:\n"));
 477
 478   for (Loop = 0; Loop < 0x80; Loop++) {
 479     if ((Loop % 0x10) == 0) {
 480       DEBUG ((DEBUG_INFO, "%02x:", Loop));
 481     }
 482     DEBUG ((DEBUG_INFO, " %02x", CmosRead8 (Loop)));
 483     if ((Loop % 0x10) == 0xf) {
 484       DEBUG ((DEBUG_INFO, "\n"));
 485     }
 486   }
 487 }
 488
 489
 490 VOID
 491 S3Verification (
 492   VOID
 493   )
 494 {
 495 #if defined (MDE_CPU_X64)
 496   if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {
 497     DEBUG ((DEBUG_ERROR,
 498       "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));
 499     DEBUG ((DEBUG_ERROR,
 500       "%a: Please disable S3 on the QEMU command line (see the README),\n",
 501       __FUNCTION__));
 502     DEBUG ((DEBUG_ERROR,
 503       "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));
 504     ASSERT (FALSE);
 505     CpuDeadLoop ();
 506   }
 507 #endif
 508 }
 509
 510
 511 /**
 512   Fetch the number of boot CPUs from QEMU and expose it to UefiCpuPkg modules.
 513   Set the mMaxCpuCount variable.
 514 **/
 515 VOID
 516 MaxCpuCountInitialization (
 517   VOID
 518   )
 519 {
 520   UINT16        ProcessorCount = 0;
 521   RETURN_STATUS PcdStatus;
 522
 523   //
 524   // If the fw_cfg key or fw_cfg entirely is unavailable, load mMaxCpuCount
 525   // from the PCD default. No change to PCDs.
 526   //
 527   if (ProcessorCount == 0) {
 528     mMaxCpuCount = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
 529     return;
 530   }
 531   //
 532   // Otherwise, set mMaxCpuCount to the value reported by QEMU.
 533   //
 534   mMaxCpuCount = ProcessorCount;
 535   //
 536   // Additionally, tell UefiCpuPkg modules (a) the exact number of VCPUs, (b)
 537   // to wait, in the initial AP bringup, exactly as long as it takes for all of
 538   // the APs to report in. For this, we set the longest representable timeout
 539   // (approx. 71 minutes).
 540   //
 541   PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, ProcessorCount);
 542   ASSERT_RETURN_ERROR (PcdStatus);
 543   PcdStatus = PcdSet32S (PcdCpuApInitTimeOutInMicroSeconds, MAX_UINT32);
 544   ASSERT_RETURN_ERROR (PcdStatus);
 545   DEBUG ((DEBUG_INFO, "%a: QEMU reports %d processor(s)\n", __FUNCTION__,
 546     ProcessorCount));
 547 }
 548
 549
 550 /**
 551   Perform Platform PEI initialization.
 552
 553   @param  FileHandle      Handle of the file being invoked.
 554   @param  PeiServices     Describes the list of possible PEI Services.
 555
 556   @return EFI_SUCCESS     The PEIM initialized successfully.
 557
 558 **/
 559 EFI_STATUS
 560 EFIAPI
 561 InitializePlatform (
 562   IN       EFI_PEI_FILE_HANDLE  FileHandle,
 563   IN CONST EFI_PEI_SERVICES     **PeiServices
 564   )
 565 {
 566   DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));
 567
 568   //
 569   // Initialize Local APIC Timer hardware and disable Local APIC Timer
 570   // interrupts before initializing the Debug Agent and the debug timer is
 571   // enabled.
 572   //
 573   InitializeApicTimer (0, MAX_UINT32, TRUE, 5);
 574   DisableApicTimerInterrupt ();
 575
 576   DebugDumpCmos ();
 577
 578   BootModeInitialization ();
 579   AddressWidthInitialization ();
 580   MaxCpuCountInitialization ();
 581
 582   //
 583   // Query Host Bridge DID
 584   //
 585   mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
 586
 587   if (FeaturePcdGet (PcdSmmSmramRequire)) {
 588     Q35TsegMbytesInitialization ();
 589   }
 590
 591   PublishPeiMemory ();
 592
 593   InitializeRamRegions ();
 594
 595   if (mBootMode != BOOT_ON_S3_RESUME) {
 596     if (!FeaturePcdGet (PcdSmmSmramRequire)) {
 597       ReserveEmuVariableNvStore ();
 598     }
 599     PeiFvInitialization ();
 600     MemMapInitialization ();
 601     NoexecDxeInitialization ();
 602   }
 603
 604   InstallClearCacheCallback ();
 605   AmdSevInitialize ();
 606   MiscInitialization ();
 607   InstallFeatureControlCallback ();
 608
 609   return EFI_SUCCESS;
 610 }