4 Copyright (c) 2020, Rebecca Cran <rebecca@bsdio.com>
5 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
6 Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
8 SPDX-License-Identifier: BSD-2-Clause-Patent
13 // The package level header files this module uses
18 // The Library classes this module consumes
20 #include <Library/BaseLib.h>
21 #include <Library/DebugLib.h>
22 #include <Library/HobLib.h>
23 #include <Library/IoLib.h>
24 #include <Library/LocalApicLib.h>
25 #include <Library/MemoryAllocationLib.h>
26 #include <Library/PcdLib.h>
27 #include <Library/PciLib.h>
28 #include <Library/PeimEntryPoint.h>
29 #include <Library/PeiServicesLib.h>
30 #include <Library/ResourcePublicationLib.h>
31 #include <Guid/MemoryTypeInformation.h>
32 #include <Ppi/MasterBootMode.h>
33 #include <IndustryStandard/Pci22.h>
34 #include <OvmfPlatforms.h>
39 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation
[] = {
40 { EfiACPIMemoryNVS
, 0x004 },
41 { EfiACPIReclaimMemory
, 0x008 },
42 { EfiReservedMemoryType
, 0x004 },
43 { EfiRuntimeServicesData
, 0x024 },
44 { EfiRuntimeServicesCode
, 0x030 },
45 { EfiBootServicesCode
, 0x180 },
46 { EfiBootServicesData
, 0xF00 },
47 { EfiMaxMemoryType
, 0x000 }
50 EFI_PEI_PPI_DESCRIPTOR mPpiBootMode
[] = {
52 EFI_PEI_PPI_DESCRIPTOR_PPI
| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST
,
53 &gEfiPeiMasterBootModePpiGuid
,
58 UINT16 mHostBridgeDevId
;
60 EFI_BOOT_MODE mBootMode
= BOOT_WITH_FULL_CONFIGURATION
;
62 BOOLEAN mS3Supported
= FALSE
;
67 AddIoMemoryBaseSizeHob (
68 EFI_PHYSICAL_ADDRESS MemoryBase
,
72 BuildResourceDescriptorHob (
73 EFI_RESOURCE_MEMORY_MAPPED_IO
,
74 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
75 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
76 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
77 EFI_RESOURCE_ATTRIBUTE_TESTED
,
84 AddReservedMemoryBaseSizeHob (
85 EFI_PHYSICAL_ADDRESS MemoryBase
,
90 BuildResourceDescriptorHob (
91 EFI_RESOURCE_MEMORY_RESERVED
,
92 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
93 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
94 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
96 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE
|
97 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE
|
98 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
:
101 EFI_RESOURCE_ATTRIBUTE_TESTED
,
108 AddIoMemoryRangeHob (
109 EFI_PHYSICAL_ADDRESS MemoryBase
,
110 EFI_PHYSICAL_ADDRESS MemoryLimit
113 AddIoMemoryBaseSizeHob (MemoryBase
, (UINT64
)(MemoryLimit
- MemoryBase
));
117 AddMemoryBaseSizeHob (
118 EFI_PHYSICAL_ADDRESS MemoryBase
,
122 BuildResourceDescriptorHob (
123 EFI_RESOURCE_SYSTEM_MEMORY
,
124 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
125 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
126 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
127 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE
|
128 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE
|
129 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
|
130 EFI_RESOURCE_ATTRIBUTE_TESTED
,
138 EFI_PHYSICAL_ADDRESS MemoryBase
,
139 EFI_PHYSICAL_ADDRESS MemoryLimit
142 AddMemoryBaseSizeHob (MemoryBase
, (UINT64
)(MemoryLimit
- MemoryBase
));
146 MemMapInitialization (
152 RETURN_STATUS PcdStatus
;
158 // Create Memory Type Information HOB
161 &gEfiMemoryTypeInformationGuid
,
162 mDefaultMemoryTypeInformation
,
163 sizeof (mDefaultMemoryTypeInformation
)
167 // Video memory + Legacy BIOS region
169 AddIoMemoryRangeHob (0x0A0000, BASE_1MB
);
177 TopOfLowRam
= GetSystemMemorySizeBelow4gb ();
179 if (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
181 // The MMCONFIG area is expected to fall between the top of low RAM and
182 // the base of the 32-bit PCI host aperture.
184 PciExBarBase
= FixedPcdGet64 (PcdPciExpressBaseAddress
);
185 ASSERT (TopOfLowRam
<= PciExBarBase
);
186 ASSERT (PciExBarBase
<= MAX_UINT32
- SIZE_256MB
);
187 PciBase
= (UINT32
)(PciExBarBase
+ SIZE_256MB
);
189 PciBase
= (UINT32
)PcdGet64 (PcdPciMmio32Base
);
191 PciBase
= (TopOfLowRam
< BASE_2GB
) ? BASE_2GB
: TopOfLowRam
;
196 // address purpose size
197 // ------------ -------- -------------------------
198 // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)
199 // 0xFC000000 gap 44 MB
200 // 0xFEC00000 IO-APIC 4 KB
201 // 0xFEC01000 gap 1020 KB
202 // 0xFED00000 HPET 1 KB
203 // 0xFED00400 gap 111 KB
204 // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB
205 // 0xFED20000 gap 896 KB
206 // 0xFEE00000 LAPIC 1 MB
208 PciSize
= 0xFC000000 - PciBase
;
209 AddIoMemoryBaseSizeHob (PciBase
, PciSize
);
210 PcdStatus
= PcdSet64S (PcdPciMmio32Base
, PciBase
);
211 ASSERT_RETURN_ERROR (PcdStatus
);
212 PcdStatus
= PcdSet64S (PcdPciMmio32Size
, PciSize
);
213 ASSERT_RETURN_ERROR (PcdStatus
);
215 AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB
);
216 AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB
);
217 if (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
218 AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE
, SIZE_16KB
);
220 // Note: there should be an
222 // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
224 // call below, just like the one above for RCBA. However, Linux insists
225 // that the MMCONFIG area be marked in the E820 or UEFI memory map as
226 // "reserved memory" -- Linux does not content itself with a simple gap
227 // in the memory map wherever the MCFG ACPI table points to.
229 // This appears to be a safety measure. The PCI Firmware Specification
230 // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
231 // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
232 // [...]". (Emphasis added here.)
234 // Normally we add memory resource descriptor HOBs in
235 // QemuInitializeRam(), and pre-allocate from those with memory
236 // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
237 // is most definitely not RAM; so, as an exception, cover it with
238 // uncacheable reserved memory right here.
240 AddReservedMemoryBaseSizeHob (PciExBarBase
, SIZE_256MB
, FALSE
);
241 BuildMemoryAllocationHob (
244 EfiReservedMemoryType
248 AddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress
), SIZE_1MB
);
251 // On Q35, the IO Port space is available for PCI resource allocations from
254 if (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
257 ASSERT ((ICH9_PMBASE_VALUE
& 0xF000) < PciIoBase
);
262 // Add PCI IO Port space available for PCI resource allocations.
264 BuildResourceDescriptorHob (
266 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
267 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
,
271 PcdStatus
= PcdSet64S (PcdPciIoBase
, PciIoBase
);
272 ASSERT_RETURN_ERROR (PcdStatus
);
273 PcdStatus
= PcdSet64S (PcdPciIoSize
, PciIoSize
);
274 ASSERT_RETURN_ERROR (PcdStatus
);
278 NoexecDxeInitialization (
285 PciExBarInitialization (
295 // We only support the 256MB size for the MMCONFIG area:
296 // 256 buses * 32 devices * 8 functions * 4096 bytes config space.
298 // The masks used below enforce the Q35 requirements that the MMCONFIG area
299 // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.
301 // Note that (b) also ensures that the minimum address width we have
302 // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice
303 // for DXE's page tables to cover the MMCONFIG area.
305 PciExBarBase
.Uint64
= FixedPcdGet64 (PcdPciExpressBaseAddress
);
306 ASSERT ((PciExBarBase
.Uint32
[1] & MCH_PCIEXBAR_HIGHMASK
) == 0);
307 ASSERT ((PciExBarBase
.Uint32
[0] & MCH_PCIEXBAR_LOWMASK
) == 0);
310 // Clear the PCIEXBAREN bit first, before programming the high register.
312 PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW
), 0);
315 // Program the high register. Then program the low register, setting the
316 // MMCONFIG area size and enabling decoding at once.
318 PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH
), PciExBarBase
.Uint32
[1]);
320 DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW
),
321 PciExBarBase
.Uint32
[0] | MCH_PCIEXBAR_BUS_FF
| MCH_PCIEXBAR_EN
336 RETURN_STATUS PcdStatus
;
344 // Build the CPU HOB with guest RAM size dependent address width and 16-bits
345 // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
346 // S3 resume as well, so we build it unconditionally.)
348 BuildCpuHob (mPhysMemAddressWidth
, 16);
351 // Determine platform type and save Host Bridge DID to PCD
353 switch (mHostBridgeDevId
) {
354 case 0x7432: // BHYVE (AMD hostbridge)
355 case 0x1275: // BHYVE (Intel hostbridge)
356 case INTEL_82441_DEVICE_ID
:
357 PmCmd
= POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET
);
358 Pmba
= POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA
);
359 PmbaAndVal
= ~(UINT32
)PIIX4_PMBA_MASK
;
360 PmbaOrVal
= PIIX4_PMBA_VALUE
;
361 AcpiCtlReg
= POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC
);
362 AcpiEnBit
= PIIX4_PMREGMISC_PMIOSE
;
364 case INTEL_Q35_MCH_DEVICE_ID
:
365 PmCmd
= POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET
);
366 Pmba
= POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE
);
367 PmbaAndVal
= ~(UINT32
)ICH9_PMBASE_MASK
;
368 PmbaOrVal
= ICH9_PMBASE_VALUE
;
369 AcpiCtlReg
= POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL
);
370 AcpiEnBit
= ICH9_ACPI_CNTL_ACPI_EN
;
375 "%a: Unknown Host Bridge Device ID: 0x%04x\n",
383 PcdStatus
= PcdSet16S (PcdOvmfHostBridgePciDevId
, mHostBridgeDevId
);
384 ASSERT_RETURN_ERROR (PcdStatus
);
387 // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
388 // has been configured (e.g., by Xen) and skip the setup here.
389 // This matches the logic in AcpiTimerLibConstructor ().
391 if ((PciRead8 (AcpiCtlReg
) & AcpiEnBit
) == 0) {
393 // The PEI phase should be exited with fully accessibe ACPI PM IO space:
396 PciAndThenOr32 (Pmba
, PmbaAndVal
, PmbaOrVal
);
399 // 2. set PCICMD/IOSE
401 PciOr8 (PmCmd
, EFI_PCI_COMMAND_IO_SPACE
);
404 // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
406 PciOr8 (AcpiCtlReg
, AcpiEnBit
);
409 if (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
411 // Set Root Complex Register Block BAR
414 POWER_MGMT_REGISTER_Q35 (ICH9_RCBA
),
415 ICH9_ROOT_COMPLEX_BASE
| ICH9_RCBA_EN
419 // Set PCI Express Register Range Base Address
421 PciExBarInitialization ();
426 BootModeInitialization (
432 if (CmosRead8 (0xF) == 0xFE) {
433 mBootMode
= BOOT_ON_S3_RESUME
;
436 CmosWrite8 (0xF, 0x00);
438 Status
= PeiServicesSetBootMode (mBootMode
);
439 ASSERT_EFI_ERROR (Status
);
441 Status
= PeiServicesInstallPpi (mPpiBootMode
);
442 ASSERT_EFI_ERROR (Status
);
446 ReserveEmuVariableNvStore (
449 EFI_PHYSICAL_ADDRESS VariableStore
;
450 RETURN_STATUS PcdStatus
;
453 // Allocate storage for NV variables early on so it will be
454 // at a consistent address. Since VM memory is preserved
455 // across reboots, this allows the NV variable storage to survive
459 (EFI_PHYSICAL_ADDRESS
)(UINTN
)
460 AllocateRuntimePages (
461 EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize
))
465 "Reserved variable store memory: 0x%lX; size: %dkb\n",
467 (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize
)) / 1024
469 PcdStatus
= PcdSet64S (PcdEmuVariableNvStoreReserved
, VariableStore
);
470 ASSERT_RETURN_ERROR (PcdStatus
);
480 DEBUG ((DEBUG_INFO
, "CMOS:\n"));
482 for (Loop
= 0; Loop
< 0x80; Loop
++) {
483 if ((Loop
% 0x10) == 0) {
484 DEBUG ((DEBUG_INFO
, "%02x:", Loop
));
487 DEBUG ((DEBUG_INFO
, " %02x", CmosRead8 (Loop
)));
488 if ((Loop
% 0x10) == 0xf) {
489 DEBUG ((DEBUG_INFO
, "\n"));
499 #if defined (MDE_CPU_X64)
500 if (FeaturePcdGet (PcdSmmSmramRequire
) && mS3Supported
) {
503 "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n",
508 "%a: Please disable S3 on the QEMU command line (see the README),\n",
513 "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n",
524 Fetch the number of boot CPUs from QEMU and expose it to UefiCpuPkg modules.
525 Set the mMaxCpuCount variable.
528 MaxCpuCountInitialization (
532 UINT16 ProcessorCount
= 0;
533 RETURN_STATUS PcdStatus
;
536 // If the fw_cfg key or fw_cfg entirely is unavailable, load mMaxCpuCount
537 // from the PCD default. No change to PCDs.
539 if (ProcessorCount
== 0) {
540 mMaxCpuCount
= PcdGet32 (PcdCpuMaxLogicalProcessorNumber
);
545 // Otherwise, set mMaxCpuCount to the value reported by QEMU.
547 mMaxCpuCount
= ProcessorCount
;
549 // Additionally, tell UefiCpuPkg modules (a) the exact number of VCPUs, (b)
550 // to wait, in the initial AP bringup, exactly as long as it takes for all of
551 // the APs to report in. For this, we set the longest representable timeout
552 // (approx. 71 minutes).
554 PcdStatus
= PcdSet32S (PcdCpuMaxLogicalProcessorNumber
, ProcessorCount
);
555 ASSERT_RETURN_ERROR (PcdStatus
);
556 PcdStatus
= PcdSet32S (PcdCpuApInitTimeOutInMicroSeconds
, MAX_UINT32
);
557 ASSERT_RETURN_ERROR (PcdStatus
);
560 "%a: QEMU reports %d processor(s)\n",
567 Perform Platform PEI initialization.
569 @param FileHandle Handle of the file being invoked.
570 @param PeiServices Describes the list of possible PEI Services.
572 @return EFI_SUCCESS The PEIM initialized successfully.
578 IN EFI_PEI_FILE_HANDLE FileHandle
,
579 IN CONST EFI_PEI_SERVICES
**PeiServices
582 DEBUG ((DEBUG_INFO
, "Platform PEIM Loaded\n"));
585 // Initialize Local APIC Timer hardware and disable Local APIC Timer
586 // interrupts before initializing the Debug Agent and the debug timer is
589 InitializeApicTimer (0, MAX_UINT32
, TRUE
, 5);
590 DisableApicTimerInterrupt ();
594 BootModeInitialization ();
595 AddressWidthInitialization ();
596 MaxCpuCountInitialization ();
599 // Query Host Bridge DID
601 mHostBridgeDevId
= PciRead16 (OVMF_HOSTBRIDGE_DID
);
603 if (FeaturePcdGet (PcdSmmSmramRequire
)) {
604 Q35TsegMbytesInitialization ();
609 InitializeRamRegions ();
611 if (mBootMode
!= BOOT_ON_S3_RESUME
) {
612 if (!FeaturePcdGet (PcdSmmSmramRequire
)) {
613 ReserveEmuVariableNvStore ();
616 PeiFvInitialization ();
617 MemMapInitialization ();
618 NoexecDxeInitialization ();
621 InstallClearCacheCallback ();
623 MiscInitialization ();
624 InstallFeatureControlCallback ();