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1 /** @file
2 PlatformInitLib header file.
3
4 Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
6
7 **/
8
9 #ifndef PLATFORM_INIT_LIB_H_
10 #define PLATFORM_INIT_LIB_H_
11
12 #include <PiPei.h>
13
14 #pragma pack(1)
15 typedef struct {
16 EFI_HOB_GUID_TYPE GuidHeader;
17 UINT16 HostBridgeDevId;
18
19 UINT64 PcdConfidentialComputingGuestAttr;
20 BOOLEAN SevEsIsEnabled;
21
22 UINT32 BootMode;
23 BOOLEAN S3Supported;
24
25 BOOLEAN SmmSmramRequire;
26 BOOLEAN Q35SmramAtDefaultSmbase;
27 UINT16 Q35TsegMbytes;
28
29 UINT64 FirstNonAddress;
30 UINT8 PhysMemAddressWidth;
31 UINT32 Uc32Base;
32 UINT32 Uc32Size;
33
34 BOOLEAN PcdSetNxForStack;
35 UINT64 PcdTdxSharedBitMask;
36
37 UINT64 PcdPciMmio64Base;
38 UINT64 PcdPciMmio64Size;
39 UINT32 PcdPciMmio32Base;
40 UINT32 PcdPciMmio32Size;
41 UINT64 PcdPciIoBase;
42 UINT64 PcdPciIoSize;
43
44 UINT64 PcdEmuVariableNvStoreReserved;
45 UINT32 PcdCpuBootLogicalProcessorNumber;
46 UINT32 PcdCpuMaxLogicalProcessorNumber;
47 UINT32 DefaultMaxCpuNumber;
48
49 UINT32 S3AcpiReservedMemoryBase;
50 UINT32 S3AcpiReservedMemorySize;
51 } EFI_HOB_PLATFORM_INFO;
52 #pragma pack()
53
54 /**
55 Reads 8-bits of CMOS data.
56
57 Reads the 8-bits of CMOS data at the location specified by Index.
58 The 8-bit read value is returned.
59
60 @param Index The CMOS location to read.
61
62 @return The value read.
63
64 **/
65 UINT8
66 EFIAPI
67 PlatformCmosRead8 (
68 IN UINTN Index
69 );
70
71 /**
72 Writes 8-bits of CMOS data.
73
74 Writes 8-bits of CMOS data to the location specified by Index
75 with the value specified by Value and returns Value.
76
77 @param Index The CMOS location to write.
78 @param Value The value to write to CMOS.
79
80 @return The value written to CMOS.
81
82 **/
83 UINT8
84 EFIAPI
85 PlatformCmosWrite8 (
86 IN UINTN Index,
87 IN UINT8 Value
88 );
89
90 /**
91 Dump the CMOS content
92 */
93 VOID
94 EFIAPI
95 PlatformDebugDumpCmos (
96 VOID
97 );
98
99 VOID
100 EFIAPI
101 PlatformAddIoMemoryBaseSizeHob (
102 IN EFI_PHYSICAL_ADDRESS MemoryBase,
103 IN UINT64 MemorySize
104 );
105
106 VOID
107 EFIAPI
108 PlatformAddIoMemoryRangeHob (
109 IN EFI_PHYSICAL_ADDRESS MemoryBase,
110 IN EFI_PHYSICAL_ADDRESS MemoryLimit
111 );
112
113 VOID
114 EFIAPI
115 PlatformAddMemoryBaseSizeHob (
116 IN EFI_PHYSICAL_ADDRESS MemoryBase,
117 IN UINT64 MemorySize
118 );
119
120 VOID
121 EFIAPI
122 PlatformAddMemoryRangeHob (
123 IN EFI_PHYSICAL_ADDRESS MemoryBase,
124 IN EFI_PHYSICAL_ADDRESS MemoryLimit
125 );
126
127 VOID
128 EFIAPI
129 PlatformAddReservedMemoryBaseSizeHob (
130 IN EFI_PHYSICAL_ADDRESS MemoryBase,
131 IN UINT64 MemorySize,
132 IN BOOLEAN Cacheable
133 );
134
135 #endif // PLATFORM_INIT_LIB_H_