2 A simple DXE_DRIVER that causes the PCI Bus UEFI_DRIVER to allocate 64-bit
3 MMIO BARs above 4 GB, regardless of option ROM availability (as long as a CSM
4 is not present), conserving 32-bit MMIO aperture for 32-bit BARs.
6 Copyright (C) 2016, Red Hat, Inc.
7 Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
9 SPDX-License-Identifier: BSD-2-Clause-Patent
12 #include <IndustryStandard/Acpi10.h>
13 #include <IndustryStandard/Pci22.h>
15 #include <Library/DebugLib.h>
16 #include <Library/MemoryAllocationLib.h>
17 #include <Library/PcdLib.h>
18 #include <Library/UefiBootServicesTableLib.h>
20 #include <Protocol/IncompatiblePciDeviceSupport.h>
21 #include <Protocol/LegacyBios.h>
24 // The Legacy BIOS protocol has been located.
26 STATIC BOOLEAN mLegacyBiosInstalled
;
29 // The protocol interface this driver produces.
31 STATIC EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL
32 mIncompatiblePciDeviceSupport
;
35 // Configuration template for the CheckDevice() protocol member function.
37 // Refer to Table 20 "ACPI 2.0 & 3.0 QWORD Address Space Descriptor Usage" in
38 // the Platform Init 1.4a Spec, Volume 5.
40 // This structure is interpreted by the UpdatePciInfo() function in the edk2
41 // PCI Bus UEFI_DRIVER.
45 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR AddressSpaceDesc
;
46 EFI_ACPI_END_TAG_DESCRIPTOR EndDesc
;
50 STATIC CONST MMIO64_PREFERENCE mConfiguration
= {
55 ACPI_ADDRESS_SPACE_DESCRIPTOR
, // Desc
57 sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) -
59 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
,
63 ACPI_ADDRESS_SPACE_TYPE_MEM
, // ResType
66 64, // AddrSpaceGranularity:
67 // aperture selection hint
71 // no special alignment
73 MAX_UINT64
, // AddrTranslationOffset:
77 // use probed BAR size
83 ACPI_END_TAG_DESCRIPTOR
, // Desc
84 0 // Checksum: to be ignored
89 // The CheckDevice() member function has been called.
91 STATIC BOOLEAN mCheckDeviceCalled
;
94 Notification callback for Legacy BIOS protocol installation.
96 @param[in] Event Event whose notification function is being invoked.
98 @param[in] Context The pointer to the notification function's context, which
99 is implementation-dependent.
104 LegacyBiosInstalled (
110 EFI_LEGACY_BIOS_PROTOCOL
*LegacyBios
;
112 ASSERT (!mCheckDeviceCalled
);
114 Status
= gBS
->LocateProtocol (
115 &gEfiLegacyBiosProtocolGuid
,
116 NULL
/* Registration */,
119 if (EFI_ERROR (Status
)) {
123 mLegacyBiosInstalled
= TRUE
;
126 // Close the event and deregister this callback.
128 Status
= gBS
->CloseEvent (Event
);
129 ASSERT_EFI_ERROR (Status
);
133 Returns a list of ACPI resource descriptors that detail the special resource
134 configuration requirements for an incompatible PCI device.
136 Prior to bus enumeration, the PCI bus driver will look for the presence of
137 the EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL. Only one instance of this
138 protocol can be present in the system. For each PCI device that the PCI bus
139 driver discovers, the PCI bus driver calls this function with the device's
140 vendor ID, device ID, revision ID, subsystem vendor ID, and subsystem device
141 ID. If the VendorId, DeviceId, RevisionId, SubsystemVendorId, or
142 SubsystemDeviceId value is set to (UINTN)-1, that field will be ignored. The
143 ID values that are not (UINTN)-1 will be used to identify the current device.
145 This function will only return EFI_SUCCESS. However, if the device is an
146 incompatible PCI device, a list of ACPI resource descriptors will be returned
147 in Configuration. Otherwise, NULL will be returned in Configuration instead.
148 The PCI bus driver does not need to allocate memory for Configuration.
149 However, it is the PCI bus driver's responsibility to free it. The PCI bus
150 driver then can configure this device with the information that is derived
151 from this list of resource nodes, rather than the result of BAR probing.
153 Only the following two resource descriptor types from the ACPI Specification
154 may be used to describe the incompatible PCI device resource requirements:
155 - QWORD Address Space Descriptor (ACPI 2.0, section 6.4.3.5.1; also ACPI 3.0)
156 - End Tag (ACPI 2.0, section 6.4.2.8; also ACPI 3.0)
158 The QWORD Address Space Descriptor can describe memory, I/O, and bus number
159 ranges for dynamic or fixed resources. The configuration of a PCI root bridge
160 is described with one or more QWORD Address Space Descriptors, followed by an
161 End Tag. See the ACPI Specification for details on the field values.
163 @param[in] This Pointer to the
164 EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL
167 @param[in] VendorId A unique ID to identify the manufacturer of
168 the PCI device. See the Conventional PCI
169 Specification 3.0 for details.
171 @param[in] DeviceId A unique ID to identify the particular PCI
172 device. See the Conventional PCI
173 Specification 3.0 for details.
175 @param[in] RevisionId A PCI device-specific revision identifier.
176 See the Conventional PCI Specification 3.0
179 @param[in] SubsystemVendorId Specifies the subsystem vendor ID. See the
180 Conventional PCI Specification 3.0 for
183 @param[in] SubsystemDeviceId Specifies the subsystem device ID. See the
184 Conventional PCI Specification 3.0 for
187 @param[out] Configuration A list of ACPI resource descriptors that
188 detail the configuration requirement.
190 @retval EFI_SUCCESS The function always returns EFI_SUCCESS.
196 IN EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL
*This
,
200 IN UINTN SubsystemVendorId
,
201 IN UINTN SubsystemDeviceId
,
202 OUT VOID
**Configuration
205 mCheckDeviceCalled
= TRUE
;
208 // Unlike the general description of this protocol member suggests, there is
209 // nothing incompatible about the PCI devices that we'll match here. We'll
210 // match all PCI devices, and generate exactly one QWORD Address Space
211 // Descriptor for each. That descriptor will instruct the PCI Bus UEFI_DRIVER
212 // not to degrade 64-bit MMIO BARs for the device, even if a PCI option ROM
213 // BAR is present on the device.
215 // The concern captured in the PCI Bus UEFI_DRIVER is that a legacy BIOS boot
216 // (via a CSM) could dispatch a legacy option ROM on the device, which might
217 // have trouble with MMIO BARs that have been allocated outside of the 32-bit
218 // address space. But, if we don't support legacy option ROMs at all, then
219 // this problem cannot arise.
221 if (mLegacyBiosInstalled
) {
223 // Don't interfere with resource degradation.
225 *Configuration
= NULL
;
230 // This member function is mis-specified actually: it is supposed to allocate
231 // memory, but as specified, it could not return an error status. Thankfully,
232 // the edk2 PCI Bus UEFI_DRIVER actually handles error codes; see the
233 // UpdatePciInfo() function.
235 *Configuration
= AllocateCopyPool (sizeof mConfiguration
, &mConfiguration
);
236 if (*Configuration
== NULL
) {
239 "%a: 64-bit MMIO BARs may be degraded for PCI 0x%04x:0x%04x (rev %d)\n",
245 return EFI_OUT_OF_RESOURCES
;
252 Entry point for this driver.
254 @param[in] ImageHandle Image handle of this driver.
255 @param[in] SystemTable Pointer to SystemTable.
257 @retval EFI_SUCESS Driver has loaded successfully.
258 @retval EFI_UNSUPPORTED PCI resource allocation has been disabled.
259 @retval EFI_UNSUPPORTED There is no 64-bit PCI MMIO aperture.
260 @return Error codes from lower level functions.
266 IN EFI_HANDLE ImageHandle
,
267 IN EFI_SYSTEM_TABLE
*SystemTable
275 // If there is no 64-bit PCI MMIO aperture, then 64-bit MMIO BARs have to be
276 // allocated under 4 GB unconditionally.
278 if (PcdGet64 (PcdPciMmio64Size
) == 0) {
279 return EFI_UNSUPPORTED
;
283 // Otherwise, create a protocol notify to see if a CSM is present. (With the
284 // CSM absent, the PCI Bus driver won't have to worry about allocating 64-bit
285 // MMIO BARs in the 32-bit MMIO aperture, for the sake of a legacy BIOS.)
287 // If the Legacy BIOS Protocol is present at the time of this driver starting
288 // up, we can mark immediately that the PCI Bus driver should perform the
289 // usual 64-bit MMIO BAR degradation.
291 // Otherwise, if the Legacy BIOS Protocol is absent at startup, it may be
292 // installed later. However, if it doesn't show up until the first
293 // EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL.CheckDevice() call from the
294 // PCI Bus driver, then it never will:
296 // 1. The following drivers are dispatched in some unspecified order:
297 // - PCI Host Bridge DXE_DRIVER,
298 // - PCI Bus UEFI_DRIVER,
299 // - this DXE_DRIVER,
300 // - Legacy BIOS DXE_DRIVER.
302 // 2. The DXE_CORE enters BDS.
304 // 3. The platform BDS connects the PCI Root Bridge IO instances (produced by
305 // the PCI Host Bridge DXE_DRIVER).
307 // 4. The PCI Bus UEFI_DRIVER enumerates resources and calls into this
308 // DXE_DRIVER (CheckDevice()).
310 // 5. This driver remembers if EFI_LEGACY_BIOS_PROTOCOL has been installed
311 // sometime during step 1 (produced by the Legacy BIOS DXE_DRIVER).
313 // For breaking this order, the Legacy BIOS DXE_DRIVER would have to install
314 // its protocol after the firmware enters BDS, which cannot happen.
316 Status
= gBS
->CreateEvent (
323 if (EFI_ERROR (Status
)) {
327 Status
= gBS
->RegisterProtocolNotify (
328 &gEfiLegacyBiosProtocolGuid
,
332 if (EFI_ERROR (Status
)) {
336 Status
= gBS
->SignalEvent (Event
);
337 ASSERT_EFI_ERROR (Status
);
339 mIncompatiblePciDeviceSupport
.CheckDevice
= CheckDevice
;
340 Status
= gBS
->InstallMultipleProtocolInterfaces (
342 &gEfiIncompatiblePciDeviceSupportProtocolGuid
,
343 &mIncompatiblePciDeviceSupport
,
346 if (EFI_ERROR (Status
)) {
353 if (!mLegacyBiosInstalled
) {
354 EFI_STATUS CloseStatus
;
356 CloseStatus
= gBS
->CloseEvent (Event
);
357 ASSERT_EFI_ERROR (CloseStatus
);