OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c

   1 /** @file
   2   Provide constructor and GetTick for BaseRom instance of ACPI Timer Library
   3
   4   Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.
   5   Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
   6
   7   SPDX-License-Identifier: BSD-2-Clause-Patent
   8 **/
   9
  10 #include <Library/DebugLib.h>
  11 #include <Library/IoLib.h>
  12 #include <Library/PciLib.h>
  13 #include <OvmfPlatforms.h>
  14
  15 /**
  16   The constructor function enables ACPI IO space.
  17
  18   If ACPI I/O space not enabled, this function will enable it.
  19   It will always return RETURN_SUCCESS.
  20
  21   @retval EFI_SUCCESS   The constructor always returns RETURN_SUCCESS.
  22
  23 **/
  24 RETURN_STATUS
  25 EFIAPI
  26 AcpiTimerLibConstructor (
  27   VOID
  28   )
  29 {
  30   UINT16  HostBridgeDevId;
  31   UINTN   Pmba;
  32   UINT32  PmbaAndVal;
  33   UINT32  PmbaOrVal;
  34   UINTN   AcpiCtlReg;
  35   UINT8   AcpiEnBit;
  36
  37   //
  38   // Query Host Bridge DID to determine platform type
  39   //
  40   HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
  41   switch (HostBridgeDevId) {
  42     case INTEL_82441_DEVICE_ID:
  43       Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
  44       PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;
  45       PmbaOrVal  = PIIX4_PMBA_VALUE;
  46       AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
  47       AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;
  48       break;
  49     case INTEL_Q35_MCH_DEVICE_ID:
  50       Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
  51       PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;
  52       PmbaOrVal  = ICH9_PMBASE_VALUE;
  53       AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
  54       AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;
  55       break;
  56     case CLOUDHV_DEVICE_ID:
  57       return RETURN_SUCCESS;
  58     default:
  59       DEBUG ((
  60         DEBUG_ERROR,
  61         "%a: Unknown Host Bridge Device ID: 0x%04x\n",
  62         __FUNCTION__,
  63         HostBridgeDevId
  64         ));
  65       ASSERT (FALSE);
  66       return RETURN_UNSUPPORTED;
  67   }
  68
  69   //
  70   // Check to see if the Power Management Base Address is already enabled
  71   //
  72   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
  73     //
  74     // If the Power Management Base Address is not programmed,
  75     // then program it now.
  76     //
  77     PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);
  78
  79     //
  80     // Enable PMBA I/O port decodes
  81     //
  82     PciOr8 (AcpiCtlReg, AcpiEnBit);
  83   }
  84
  85   return RETURN_SUCCESS;
  86 }
  87
  88 /**
  89   Internal function to read the current tick counter of ACPI.
  90
  91   Dynamically compute the address of the ACPI tick counter based on the
  92   properties of the underlying platform, to avoid relying on global variables.
  93
  94   @return The tick counter read.
  95
  96 **/
  97 UINT32
  98 InternalAcpiGetTimerTick (
  99   VOID
 100   )
 101 {
 102   UINT16  HostBridgeDevId;
 103   UINTN   Pmba;
 104
 105   //
 106   // Query Host Bridge DID to determine platform type
 107   //
 108   HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
 109   switch (HostBridgeDevId) {
 110     case INTEL_82441_DEVICE_ID:
 111       Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
 112       break;
 113     case INTEL_Q35_MCH_DEVICE_ID:
 114       Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
 115       break;
 116     case CLOUDHV_DEVICE_ID:
 117       return IoRead32 (CLOUDHV_ACPI_TIMER_IO_ADDRESS);
 118     default:
 119       DEBUG ((
 120         DEBUG_ERROR,
 121         "%a: Unknown Host Bridge Device ID: 0x%04x\n",
 122         __FUNCTION__,
 123         HostBridgeDevId
 124         ));
 125       ASSERT (FALSE);
 126       return 0;
 127   }
 128
 129   //
 130   //   Read PMBA to read and return the current ACPI timer value.
 131   //
 132   return IoRead32 ((PciRead32 (Pmba) & ~PMBA_RTE) + ACPI_TIMER_OFFSET);
 133 }