2 Functions in this library instance make use of MMIO functions in IoLib to
3 access memory mapped PCI configuration space.
5 All assertions for I/O operations are handled in MMIO functions in the IoLib
8 Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
9 SPDX-License-Identifier: BSD-2-Clause-Patent
15 #include <Library/BaseLib.h>
16 #include <Library/PciExpressLib.h>
17 #include <Library/IoLib.h>
18 #include <Library/DebugLib.h>
19 #include <Library/PcdLib.h>
22 Assert the validity of a PCI address. A valid PCI address should contain 1's
23 only in the low 28 bits.
25 @param A The address to validate.
28 #define ASSERT_INVALID_PCI_ADDRESS(A) \
29 ASSERT (((A) & ~0xfffffff) == 0)
32 Registers a PCI device so PCI configuration registers may be accessed after
33 SetVirtualAddressMap().
35 Registers the PCI device specified by Address so all the PCI configuration
36 registers associated with that PCI device may be accessed after SetVirtualAddressMap()
39 If Address > 0x0FFFFFFF, then ASSERT().
41 @param Address The address that encodes the PCI Bus, Device, Function and
44 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
45 @retval RETURN_UNSUPPORTED An attempt was made to call this function
46 after ExitBootServices().
47 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
48 at runtime could not be mapped.
49 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
50 complete the registration.
55 PciExpressRegisterForRuntimeAccess (
59 ASSERT_INVALID_PCI_ADDRESS (Address
);
60 return RETURN_UNSUPPORTED
;
63 STATIC UINT64 mPciExpressBaseAddress
;
67 PciExpressLibInitialize (
71 mPciExpressBaseAddress
= PcdGet64 (PcdPciExpressBaseAddress
);
72 return RETURN_SUCCESS
;
76 Gets the base address of PCI Express.
78 @return The base address of PCI Express.
82 GetPciExpressBaseAddress (
86 return (VOID
*)(UINTN
)mPciExpressBaseAddress
;
90 Reads an 8-bit PCI configuration register.
92 Reads and returns the 8-bit PCI configuration register specified by Address.
93 This function must guarantee that all PCI read and write operations are
96 If Address > 0x0FFFFFFF, then ASSERT().
98 @param Address The address that encodes the PCI Bus, Device, Function and
101 @return The read value from the PCI configuration register.
110 ASSERT_INVALID_PCI_ADDRESS (Address
);
111 return MmioRead8 ((UINTN
)GetPciExpressBaseAddress () + Address
);
115 Writes an 8-bit PCI configuration register.
117 Writes the 8-bit PCI configuration register specified by Address with the
118 value specified by Value. Value is returned. This function must guarantee
119 that all PCI read and write operations are serialized.
121 If Address > 0x0FFFFFFF, then ASSERT().
123 @param Address The address that encodes the PCI Bus, Device, Function and
125 @param Value The value to write.
127 @return The value written to the PCI configuration register.
137 ASSERT_INVALID_PCI_ADDRESS (Address
);
138 return MmioWrite8 ((UINTN
)GetPciExpressBaseAddress () + Address
, Value
);
142 Performs a bitwise OR of an 8-bit PCI configuration register with
145 Reads the 8-bit PCI configuration register specified by Address, performs a
146 bitwise OR between the read result and the value specified by
147 OrData, and writes the result to the 8-bit PCI configuration register
148 specified by Address. The value written to the PCI configuration register is
149 returned. This function must guarantee that all PCI read and write operations
152 If Address > 0x0FFFFFFF, then ASSERT().
154 @param Address The address that encodes the PCI Bus, Device, Function and
156 @param OrData The value to OR with the PCI configuration register.
158 @return The value written back to the PCI configuration register.
168 ASSERT_INVALID_PCI_ADDRESS (Address
);
169 return MmioOr8 ((UINTN
)GetPciExpressBaseAddress () + Address
, OrData
);
173 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
176 Reads the 8-bit PCI configuration register specified by Address, performs a
177 bitwise AND between the read result and the value specified by AndData, and
178 writes the result to the 8-bit PCI configuration register specified by
179 Address. The value written to the PCI configuration register is returned.
180 This function must guarantee that all PCI read and write operations are
183 If Address > 0x0FFFFFFF, then ASSERT().
185 @param Address The address that encodes the PCI Bus, Device, Function and
187 @param AndData The value to AND with the PCI configuration register.
189 @return The value written back to the PCI configuration register.
199 ASSERT_INVALID_PCI_ADDRESS (Address
);
200 return MmioAnd8 ((UINTN
)GetPciExpressBaseAddress () + Address
, AndData
);
204 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
205 value, followed a bitwise OR with another 8-bit value.
207 Reads the 8-bit PCI configuration register specified by Address, performs a
208 bitwise AND between the read result and the value specified by AndData,
209 performs a bitwise OR between the result of the AND operation and
210 the value specified by OrData, and writes the result to the 8-bit PCI
211 configuration register specified by Address. The value written to the PCI
212 configuration register is returned. This function must guarantee that all PCI
213 read and write operations are serialized.
215 If Address > 0x0FFFFFFF, then ASSERT().
217 @param Address The address that encodes the PCI Bus, Device, Function and
219 @param AndData The value to AND with the PCI configuration register.
220 @param OrData The value to OR with the result of the AND operation.
222 @return The value written back to the PCI configuration register.
227 PciExpressAndThenOr8 (
233 ASSERT_INVALID_PCI_ADDRESS (Address
);
234 return MmioAndThenOr8 (
235 (UINTN
)GetPciExpressBaseAddress () + Address
,
242 Reads a bit field of a PCI configuration register.
244 Reads the bit field in an 8-bit PCI configuration register. The bit field is
245 specified by the StartBit and the EndBit. The value of the bit field is
248 If Address > 0x0FFFFFFF, then ASSERT().
249 If StartBit is greater than 7, then ASSERT().
250 If EndBit is greater than 7, then ASSERT().
251 If EndBit is less than StartBit, then ASSERT().
253 @param Address The PCI configuration register to read.
254 @param StartBit The ordinal of the least significant bit in the bit field.
256 @param EndBit The ordinal of the most significant bit in the bit field.
259 @return The value of the bit field read from the PCI configuration register.
264 PciExpressBitFieldRead8 (
270 ASSERT_INVALID_PCI_ADDRESS (Address
);
271 return MmioBitFieldRead8 (
272 (UINTN
)GetPciExpressBaseAddress () + Address
,
279 Writes a bit field to a PCI configuration register.
281 Writes Value to the bit field of the PCI configuration register. The bit
282 field is specified by the StartBit and the EndBit. All other bits in the
283 destination PCI configuration register are preserved. The new value of the
284 8-bit register is returned.
286 If Address > 0x0FFFFFFF, then ASSERT().
287 If StartBit is greater than 7, then ASSERT().
288 If EndBit is greater than 7, then ASSERT().
289 If EndBit is less than StartBit, then ASSERT().
290 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
292 @param Address The PCI configuration register to write.
293 @param StartBit The ordinal of the least significant bit in the bit field.
295 @param EndBit The ordinal of the most significant bit in the bit field.
297 @param Value The new value of the bit field.
299 @return The value written back to the PCI configuration register.
304 PciExpressBitFieldWrite8 (
311 ASSERT_INVALID_PCI_ADDRESS (Address
);
312 return MmioBitFieldWrite8 (
313 (UINTN
)GetPciExpressBaseAddress () + Address
,
321 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
322 writes the result back to the bit field in the 8-bit port.
324 Reads the 8-bit PCI configuration register specified by Address, performs a
325 bitwise OR between the read result and the value specified by
326 OrData, and writes the result to the 8-bit PCI configuration register
327 specified by Address. The value written to the PCI configuration register is
328 returned. This function must guarantee that all PCI read and write operations
329 are serialized. Extra left bits in OrData are stripped.
331 If Address > 0x0FFFFFFF, then ASSERT().
332 If StartBit is greater than 7, then ASSERT().
333 If EndBit is greater than 7, then ASSERT().
334 If EndBit is less than StartBit, then ASSERT().
335 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
337 @param Address The PCI configuration register to write.
338 @param StartBit The ordinal of the least significant bit in the bit field.
340 @param EndBit The ordinal of the most significant bit in the bit field.
342 @param OrData The value to OR with the PCI configuration register.
344 @return The value written back to the PCI configuration register.
349 PciExpressBitFieldOr8 (
356 ASSERT_INVALID_PCI_ADDRESS (Address
);
357 return MmioBitFieldOr8 (
358 (UINTN
)GetPciExpressBaseAddress () + Address
,
366 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
367 AND, and writes the result back to the bit field in the 8-bit register.
369 Reads the 8-bit PCI configuration register specified by Address, performs a
370 bitwise AND between the read result and the value specified by AndData, and
371 writes the result to the 8-bit PCI configuration register specified by
372 Address. The value written to the PCI configuration register is returned.
373 This function must guarantee that all PCI read and write operations are
374 serialized. Extra left bits in AndData are stripped.
376 If Address > 0x0FFFFFFF, then ASSERT().
377 If StartBit is greater than 7, then ASSERT().
378 If EndBit is greater than 7, then ASSERT().
379 If EndBit is less than StartBit, then ASSERT().
380 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
382 @param Address The PCI configuration register to write.
383 @param StartBit The ordinal of the least significant bit in the bit field.
385 @param EndBit The ordinal of the most significant bit in the bit field.
387 @param AndData The value to AND with the PCI configuration register.
389 @return The value written back to the PCI configuration register.
394 PciExpressBitFieldAnd8 (
401 ASSERT_INVALID_PCI_ADDRESS (Address
);
402 return MmioBitFieldAnd8 (
403 (UINTN
)GetPciExpressBaseAddress () + Address
,
411 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
412 bitwise OR, and writes the result back to the bit field in the
415 Reads the 8-bit PCI configuration register specified by Address, performs a
416 bitwise AND followed by a bitwise OR between the read result and
417 the value specified by AndData, and writes the result to the 8-bit PCI
418 configuration register specified by Address. The value written to the PCI
419 configuration register is returned. This function must guarantee that all PCI
420 read and write operations are serialized. Extra left bits in both AndData and
423 If Address > 0x0FFFFFFF, then ASSERT().
424 If StartBit is greater than 7, then ASSERT().
425 If EndBit is greater than 7, then ASSERT().
426 If EndBit is less than StartBit, then ASSERT().
427 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
428 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
430 @param Address The PCI configuration register to write.
431 @param StartBit The ordinal of the least significant bit in the bit field.
433 @param EndBit The ordinal of the most significant bit in the bit field.
435 @param AndData The value to AND with the PCI configuration register.
436 @param OrData The value to OR with the result of the AND operation.
438 @return The value written back to the PCI configuration register.
443 PciExpressBitFieldAndThenOr8 (
451 ASSERT_INVALID_PCI_ADDRESS (Address
);
452 return MmioBitFieldAndThenOr8 (
453 (UINTN
)GetPciExpressBaseAddress () + Address
,
462 Reads a 16-bit PCI configuration register.
464 Reads and returns the 16-bit PCI configuration register specified by Address.
465 This function must guarantee that all PCI read and write operations are
468 If Address > 0x0FFFFFFF, then ASSERT().
469 If Address is not aligned on a 16-bit boundary, then ASSERT().
471 @param Address The address that encodes the PCI Bus, Device, Function and
474 @return The read value from the PCI configuration register.
483 ASSERT_INVALID_PCI_ADDRESS (Address
);
484 return MmioRead16 ((UINTN
)GetPciExpressBaseAddress () + Address
);
488 Writes a 16-bit PCI configuration register.
490 Writes the 16-bit PCI configuration register specified by Address with the
491 value specified by Value. Value is returned. This function must guarantee
492 that all PCI read and write operations are serialized.
494 If Address > 0x0FFFFFFF, then ASSERT().
495 If Address is not aligned on a 16-bit boundary, then ASSERT().
497 @param Address The address that encodes the PCI Bus, Device, Function and
499 @param Value The value to write.
501 @return The value written to the PCI configuration register.
511 ASSERT_INVALID_PCI_ADDRESS (Address
);
512 return MmioWrite16 ((UINTN
)GetPciExpressBaseAddress () + Address
, Value
);
516 Performs a bitwise OR of a 16-bit PCI configuration register with
519 Reads the 16-bit PCI configuration register specified by Address, performs a
520 bitwise OR between the read result and the value specified by
521 OrData, and writes the result to the 16-bit PCI configuration register
522 specified by Address. The value written to the PCI configuration register is
523 returned. This function must guarantee that all PCI read and write operations
526 If Address > 0x0FFFFFFF, then ASSERT().
527 If Address is not aligned on a 16-bit boundary, then ASSERT().
529 @param Address The address that encodes the PCI Bus, Device, Function and
531 @param OrData The value to OR with the PCI configuration register.
533 @return The value written back to the PCI configuration register.
543 ASSERT_INVALID_PCI_ADDRESS (Address
);
544 return MmioOr16 ((UINTN
)GetPciExpressBaseAddress () + Address
, OrData
);
548 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
551 Reads the 16-bit PCI configuration register specified by Address, performs a
552 bitwise AND between the read result and the value specified by AndData, and
553 writes the result to the 16-bit PCI configuration register specified by
554 Address. The value written to the PCI configuration register is returned.
555 This function must guarantee that all PCI read and write operations are
558 If Address > 0x0FFFFFFF, then ASSERT().
559 If Address is not aligned on a 16-bit boundary, then ASSERT().
561 @param Address The address that encodes the PCI Bus, Device, Function and
563 @param AndData The value to AND with the PCI configuration register.
565 @return The value written back to the PCI configuration register.
575 ASSERT_INVALID_PCI_ADDRESS (Address
);
576 return MmioAnd16 ((UINTN
)GetPciExpressBaseAddress () + Address
, AndData
);
580 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
581 value, followed a bitwise OR with another 16-bit value.
583 Reads the 16-bit PCI configuration register specified by Address, performs a
584 bitwise AND between the read result and the value specified by AndData,
585 performs a bitwise OR between the result of the AND operation and
586 the value specified by OrData, and writes the result to the 16-bit PCI
587 configuration register specified by Address. The value written to the PCI
588 configuration register is returned. This function must guarantee that all PCI
589 read and write operations are serialized.
591 If Address > 0x0FFFFFFF, then ASSERT().
592 If Address is not aligned on a 16-bit boundary, then ASSERT().
594 @param Address The address that encodes the PCI Bus, Device, Function and
596 @param AndData The value to AND with the PCI configuration register.
597 @param OrData The value to OR with the result of the AND operation.
599 @return The value written back to the PCI configuration register.
604 PciExpressAndThenOr16 (
610 ASSERT_INVALID_PCI_ADDRESS (Address
);
611 return MmioAndThenOr16 (
612 (UINTN
)GetPciExpressBaseAddress () + Address
,
619 Reads a bit field of a PCI configuration register.
621 Reads the bit field in a 16-bit PCI configuration register. The bit field is
622 specified by the StartBit and the EndBit. The value of the bit field is
625 If Address > 0x0FFFFFFF, then ASSERT().
626 If Address is not aligned on a 16-bit boundary, then ASSERT().
627 If StartBit is greater than 15, then ASSERT().
628 If EndBit is greater than 15, then ASSERT().
629 If EndBit is less than StartBit, then ASSERT().
631 @param Address The PCI configuration register to read.
632 @param StartBit The ordinal of the least significant bit in the bit field.
634 @param EndBit The ordinal of the most significant bit in the bit field.
637 @return The value of the bit field read from the PCI configuration register.
642 PciExpressBitFieldRead16 (
648 ASSERT_INVALID_PCI_ADDRESS (Address
);
649 return MmioBitFieldRead16 (
650 (UINTN
)GetPciExpressBaseAddress () + Address
,
657 Writes a bit field to a PCI configuration register.
659 Writes Value to the bit field of the PCI configuration register. The bit
660 field is specified by the StartBit and the EndBit. All other bits in the
661 destination PCI configuration register are preserved. The new value of the
662 16-bit register is returned.
664 If Address > 0x0FFFFFFF, then ASSERT().
665 If Address is not aligned on a 16-bit boundary, then ASSERT().
666 If StartBit is greater than 15, then ASSERT().
667 If EndBit is greater than 15, then ASSERT().
668 If EndBit is less than StartBit, then ASSERT().
669 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
671 @param Address The PCI configuration register to write.
672 @param StartBit The ordinal of the least significant bit in the bit field.
674 @param EndBit The ordinal of the most significant bit in the bit field.
676 @param Value The new value of the bit field.
678 @return The value written back to the PCI configuration register.
683 PciExpressBitFieldWrite16 (
690 ASSERT_INVALID_PCI_ADDRESS (Address
);
691 return MmioBitFieldWrite16 (
692 (UINTN
)GetPciExpressBaseAddress () + Address
,
700 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
701 writes the result back to the bit field in the 16-bit port.
703 Reads the 16-bit PCI configuration register specified by Address, performs a
704 bitwise OR between the read result and the value specified by
705 OrData, and writes the result to the 16-bit PCI configuration register
706 specified by Address. The value written to the PCI configuration register is
707 returned. This function must guarantee that all PCI read and write operations
708 are serialized. Extra left bits in OrData are stripped.
710 If Address > 0x0FFFFFFF, then ASSERT().
711 If Address is not aligned on a 16-bit boundary, then ASSERT().
712 If StartBit is greater than 15, then ASSERT().
713 If EndBit is greater than 15, then ASSERT().
714 If EndBit is less than StartBit, then ASSERT().
715 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
717 @param Address The PCI configuration register to write.
718 @param StartBit The ordinal of the least significant bit in the bit field.
720 @param EndBit The ordinal of the most significant bit in the bit field.
722 @param OrData The value to OR with the PCI configuration register.
724 @return The value written back to the PCI configuration register.
729 PciExpressBitFieldOr16 (
736 ASSERT_INVALID_PCI_ADDRESS (Address
);
737 return MmioBitFieldOr16 (
738 (UINTN
)GetPciExpressBaseAddress () + Address
,
746 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
747 AND, and writes the result back to the bit field in the 16-bit register.
749 Reads the 16-bit PCI configuration register specified by Address, performs a
750 bitwise AND between the read result and the value specified by AndData, and
751 writes the result to the 16-bit PCI configuration register specified by
752 Address. The value written to the PCI configuration register is returned.
753 This function must guarantee that all PCI read and write operations are
754 serialized. Extra left bits in AndData are stripped.
756 If Address > 0x0FFFFFFF, then ASSERT().
757 If Address is not aligned on a 16-bit boundary, then ASSERT().
758 If StartBit is greater than 15, then ASSERT().
759 If EndBit is greater than 15, then ASSERT().
760 If EndBit is less than StartBit, then ASSERT().
761 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
763 @param Address The PCI configuration register to write.
764 @param StartBit The ordinal of the least significant bit in the bit field.
766 @param EndBit The ordinal of the most significant bit in the bit field.
768 @param AndData The value to AND with the PCI configuration register.
770 @return The value written back to the PCI configuration register.
775 PciExpressBitFieldAnd16 (
782 ASSERT_INVALID_PCI_ADDRESS (Address
);
783 return MmioBitFieldAnd16 (
784 (UINTN
)GetPciExpressBaseAddress () + Address
,
792 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
793 bitwise OR, and writes the result back to the bit field in the
796 Reads the 16-bit PCI configuration register specified by Address, performs a
797 bitwise AND followed by a bitwise OR between the read result and
798 the value specified by AndData, and writes the result to the 16-bit PCI
799 configuration register specified by Address. The value written to the PCI
800 configuration register is returned. This function must guarantee that all PCI
801 read and write operations are serialized. Extra left bits in both AndData and
804 If Address > 0x0FFFFFFF, then ASSERT().
805 If Address is not aligned on a 16-bit boundary, then ASSERT().
806 If StartBit is greater than 15, then ASSERT().
807 If EndBit is greater than 15, then ASSERT().
808 If EndBit is less than StartBit, then ASSERT().
809 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
810 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
812 @param Address The PCI configuration register to write.
813 @param StartBit The ordinal of the least significant bit in the bit field.
815 @param EndBit The ordinal of the most significant bit in the bit field.
817 @param AndData The value to AND with the PCI configuration register.
818 @param OrData The value to OR with the result of the AND operation.
820 @return The value written back to the PCI configuration register.
825 PciExpressBitFieldAndThenOr16 (
833 ASSERT_INVALID_PCI_ADDRESS (Address
);
834 return MmioBitFieldAndThenOr16 (
835 (UINTN
)GetPciExpressBaseAddress () + Address
,
844 Reads a 32-bit PCI configuration register.
846 Reads and returns the 32-bit PCI configuration register specified by Address.
847 This function must guarantee that all PCI read and write operations are
850 If Address > 0x0FFFFFFF, then ASSERT().
851 If Address is not aligned on a 32-bit boundary, then ASSERT().
853 @param Address The address that encodes the PCI Bus, Device, Function and
856 @return The read value from the PCI configuration register.
865 ASSERT_INVALID_PCI_ADDRESS (Address
);
866 return MmioRead32 ((UINTN
)GetPciExpressBaseAddress () + Address
);
870 Writes a 32-bit PCI configuration register.
872 Writes the 32-bit PCI configuration register specified by Address with the
873 value specified by Value. Value is returned. This function must guarantee
874 that all PCI read and write operations are serialized.
876 If Address > 0x0FFFFFFF, then ASSERT().
877 If Address is not aligned on a 32-bit boundary, then ASSERT().
879 @param Address The address that encodes the PCI Bus, Device, Function and
881 @param Value The value to write.
883 @return The value written to the PCI configuration register.
893 ASSERT_INVALID_PCI_ADDRESS (Address
);
894 return MmioWrite32 ((UINTN
)GetPciExpressBaseAddress () + Address
, Value
);
898 Performs a bitwise OR of a 32-bit PCI configuration register with
901 Reads the 32-bit PCI configuration register specified by Address, performs a
902 bitwise OR between the read result and the value specified by
903 OrData, and writes the result to the 32-bit PCI configuration register
904 specified by Address. The value written to the PCI configuration register is
905 returned. This function must guarantee that all PCI read and write operations
908 If Address > 0x0FFFFFFF, then ASSERT().
909 If Address is not aligned on a 32-bit boundary, then ASSERT().
911 @param Address The address that encodes the PCI Bus, Device, Function and
913 @param OrData The value to OR with the PCI configuration register.
915 @return The value written back to the PCI configuration register.
925 ASSERT_INVALID_PCI_ADDRESS (Address
);
926 return MmioOr32 ((UINTN
)GetPciExpressBaseAddress () + Address
, OrData
);
930 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
933 Reads the 32-bit PCI configuration register specified by Address, performs a
934 bitwise AND between the read result and the value specified by AndData, and
935 writes the result to the 32-bit PCI configuration register specified by
936 Address. The value written to the PCI configuration register is returned.
937 This function must guarantee that all PCI read and write operations are
940 If Address > 0x0FFFFFFF, then ASSERT().
941 If Address is not aligned on a 32-bit boundary, then ASSERT().
943 @param Address The address that encodes the PCI Bus, Device, Function and
945 @param AndData The value to AND with the PCI configuration register.
947 @return The value written back to the PCI configuration register.
957 ASSERT_INVALID_PCI_ADDRESS (Address
);
958 return MmioAnd32 ((UINTN
)GetPciExpressBaseAddress () + Address
, AndData
);
962 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
963 value, followed a bitwise OR with another 32-bit value.
965 Reads the 32-bit PCI configuration register specified by Address, performs a
966 bitwise AND between the read result and the value specified by AndData,
967 performs a bitwise OR between the result of the AND operation and
968 the value specified by OrData, and writes the result to the 32-bit PCI
969 configuration register specified by Address. The value written to the PCI
970 configuration register is returned. This function must guarantee that all PCI
971 read and write operations are serialized.
973 If Address > 0x0FFFFFFF, then ASSERT().
974 If Address is not aligned on a 32-bit boundary, then ASSERT().
976 @param Address The address that encodes the PCI Bus, Device, Function and
978 @param AndData The value to AND with the PCI configuration register.
979 @param OrData The value to OR with the result of the AND operation.
981 @return The value written back to the PCI configuration register.
986 PciExpressAndThenOr32 (
992 ASSERT_INVALID_PCI_ADDRESS (Address
);
993 return MmioAndThenOr32 (
994 (UINTN
)GetPciExpressBaseAddress () + Address
,
1001 Reads a bit field of a PCI configuration register.
1003 Reads the bit field in a 32-bit PCI configuration register. The bit field is
1004 specified by the StartBit and the EndBit. The value of the bit field is
1007 If Address > 0x0FFFFFFF, then ASSERT().
1008 If Address is not aligned on a 32-bit boundary, then ASSERT().
1009 If StartBit is greater than 31, then ASSERT().
1010 If EndBit is greater than 31, then ASSERT().
1011 If EndBit is less than StartBit, then ASSERT().
1013 @param Address The PCI configuration register to read.
1014 @param StartBit The ordinal of the least significant bit in the bit field.
1016 @param EndBit The ordinal of the most significant bit in the bit field.
1019 @return The value of the bit field read from the PCI configuration register.
1024 PciExpressBitFieldRead32 (
1030 ASSERT_INVALID_PCI_ADDRESS (Address
);
1031 return MmioBitFieldRead32 (
1032 (UINTN
)GetPciExpressBaseAddress () + Address
,
1039 Writes a bit field to a PCI configuration register.
1041 Writes Value to the bit field of the PCI configuration register. The bit
1042 field is specified by the StartBit and the EndBit. All other bits in the
1043 destination PCI configuration register are preserved. The new value of the
1044 32-bit register is returned.
1046 If Address > 0x0FFFFFFF, then ASSERT().
1047 If Address is not aligned on a 32-bit boundary, then ASSERT().
1048 If StartBit is greater than 31, then ASSERT().
1049 If EndBit is greater than 31, then ASSERT().
1050 If EndBit is less than StartBit, then ASSERT().
1051 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1053 @param Address The PCI configuration register to write.
1054 @param StartBit The ordinal of the least significant bit in the bit field.
1056 @param EndBit The ordinal of the most significant bit in the bit field.
1058 @param Value The new value of the bit field.
1060 @return The value written back to the PCI configuration register.
1065 PciExpressBitFieldWrite32 (
1072 ASSERT_INVALID_PCI_ADDRESS (Address
);
1073 return MmioBitFieldWrite32 (
1074 (UINTN
)GetPciExpressBaseAddress () + Address
,
1082 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1083 writes the result back to the bit field in the 32-bit port.
1085 Reads the 32-bit PCI configuration register specified by Address, performs a
1086 bitwise OR between the read result and the value specified by
1087 OrData, and writes the result to the 32-bit PCI configuration register
1088 specified by Address. The value written to the PCI configuration register is
1089 returned. This function must guarantee that all PCI read and write operations
1090 are serialized. Extra left bits in OrData are stripped.
1092 If Address > 0x0FFFFFFF, then ASSERT().
1093 If Address is not aligned on a 32-bit boundary, then ASSERT().
1094 If StartBit is greater than 31, then ASSERT().
1095 If EndBit is greater than 31, then ASSERT().
1096 If EndBit is less than StartBit, then ASSERT().
1097 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1099 @param Address The PCI configuration register to write.
1100 @param StartBit The ordinal of the least significant bit in the bit field.
1102 @param EndBit The ordinal of the most significant bit in the bit field.
1104 @param OrData The value to OR with the PCI configuration register.
1106 @return The value written back to the PCI configuration register.
1111 PciExpressBitFieldOr32 (
1118 ASSERT_INVALID_PCI_ADDRESS (Address
);
1119 return MmioBitFieldOr32 (
1120 (UINTN
)GetPciExpressBaseAddress () + Address
,
1128 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1129 AND, and writes the result back to the bit field in the 32-bit register.
1131 Reads the 32-bit PCI configuration register specified by Address, performs a
1132 bitwise AND between the read result and the value specified by AndData, and
1133 writes the result to the 32-bit PCI configuration register specified by
1134 Address. The value written to the PCI configuration register is returned.
1135 This function must guarantee that all PCI read and write operations are
1136 serialized. Extra left bits in AndData are stripped.
1138 If Address > 0x0FFFFFFF, then ASSERT().
1139 If Address is not aligned on a 32-bit boundary, then ASSERT().
1140 If StartBit is greater than 31, then ASSERT().
1141 If EndBit is greater than 31, then ASSERT().
1142 If EndBit is less than StartBit, then ASSERT().
1143 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1145 @param Address The PCI configuration register to write.
1146 @param StartBit The ordinal of the least significant bit in the bit field.
1148 @param EndBit The ordinal of the most significant bit in the bit field.
1150 @param AndData The value to AND with the PCI configuration register.
1152 @return The value written back to the PCI configuration register.
1157 PciExpressBitFieldAnd32 (
1164 ASSERT_INVALID_PCI_ADDRESS (Address
);
1165 return MmioBitFieldAnd32 (
1166 (UINTN
)GetPciExpressBaseAddress () + Address
,
1174 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1175 bitwise OR, and writes the result back to the bit field in the
1178 Reads the 32-bit PCI configuration register specified by Address, performs a
1179 bitwise AND followed by a bitwise OR between the read result and
1180 the value specified by AndData, and writes the result to the 32-bit PCI
1181 configuration register specified by Address. The value written to the PCI
1182 configuration register is returned. This function must guarantee that all PCI
1183 read and write operations are serialized. Extra left bits in both AndData and
1184 OrData are stripped.
1186 If Address > 0x0FFFFFFF, then ASSERT().
1187 If Address is not aligned on a 32-bit boundary, then ASSERT().
1188 If StartBit is greater than 31, then ASSERT().
1189 If EndBit is greater than 31, then ASSERT().
1190 If EndBit is less than StartBit, then ASSERT().
1191 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1192 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1194 @param Address The PCI configuration register to write.
1195 @param StartBit The ordinal of the least significant bit in the bit field.
1197 @param EndBit The ordinal of the most significant bit in the bit field.
1199 @param AndData The value to AND with the PCI configuration register.
1200 @param OrData The value to OR with the result of the AND operation.
1202 @return The value written back to the PCI configuration register.
1207 PciExpressBitFieldAndThenOr32 (
1215 ASSERT_INVALID_PCI_ADDRESS (Address
);
1216 return MmioBitFieldAndThenOr32 (
1217 (UINTN
)GetPciExpressBaseAddress () + Address
,
1226 Reads a range of PCI configuration registers into a caller supplied buffer.
1228 Reads the range of PCI configuration registers specified by StartAddress and
1229 Size into the buffer specified by Buffer. This function only allows the PCI
1230 configuration registers from a single PCI function to be read. Size is
1231 returned. When possible 32-bit PCI configuration read cycles are used to read
1232 from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit
1233 and 16-bit PCI configuration read cycles may be used at the beginning and the
1236 If StartAddress > 0x0FFFFFFF, then ASSERT().
1237 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1238 If Size > 0 and Buffer is NULL, then ASSERT().
1240 @param StartAddress The starting address that encodes the PCI Bus, Device,
1241 Function and Register.
1242 @param Size The size in bytes of the transfer.
1243 @param Buffer The pointer to a buffer receiving the data read.
1245 @return Size read data from StartAddress.
1250 PciExpressReadBuffer (
1251 IN UINTN StartAddress
,
1258 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1259 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1265 ASSERT (Buffer
!= NULL
);
1268 // Save Size for return
1272 if ((StartAddress
& 1) != 0) {
1274 // Read a byte if StartAddress is byte aligned
1276 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1277 StartAddress
+= sizeof (UINT8
);
1278 Size
-= sizeof (UINT8
);
1279 Buffer
= (UINT8
*)Buffer
+ 1;
1282 if ((Size
>= sizeof (UINT16
)) && ((StartAddress
& 2) != 0)) {
1284 // Read a word if StartAddress is word aligned
1286 WriteUnaligned16 ((UINT16
*)Buffer
, (UINT16
)PciExpressRead16 (StartAddress
));
1288 StartAddress
+= sizeof (UINT16
);
1289 Size
-= sizeof (UINT16
);
1290 Buffer
= (UINT16
*)Buffer
+ 1;
1293 while (Size
>= sizeof (UINT32
)) {
1295 // Read as many double words as possible
1297 WriteUnaligned32 ((UINT32
*)Buffer
, (UINT32
)PciExpressRead32 (StartAddress
));
1299 StartAddress
+= sizeof (UINT32
);
1300 Size
-= sizeof (UINT32
);
1301 Buffer
= (UINT32
*)Buffer
+ 1;
1304 if (Size
>= sizeof (UINT16
)) {
1306 // Read the last remaining word if exist
1308 WriteUnaligned16 ((UINT16
*)Buffer
, (UINT16
)PciExpressRead16 (StartAddress
));
1309 StartAddress
+= sizeof (UINT16
);
1310 Size
-= sizeof (UINT16
);
1311 Buffer
= (UINT16
*)Buffer
+ 1;
1314 if (Size
>= sizeof (UINT8
)) {
1316 // Read the last remaining byte if exist
1318 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1325 Copies the data in a caller supplied buffer to a specified range of PCI
1326 configuration space.
1328 Writes the range of PCI configuration registers specified by StartAddress and
1329 Size from the buffer specified by Buffer. This function only allows the PCI
1330 configuration registers from a single PCI function to be written. Size is
1331 returned. When possible 32-bit PCI configuration write cycles are used to
1332 write from StartAddress to StartAddress + Size. Due to alignment restrictions,
1333 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1334 and the end of the range.
1336 If StartAddress > 0x0FFFFFFF, then ASSERT().
1337 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1338 If Size > 0 and Buffer is NULL, then ASSERT().
1340 @param StartAddress The starting address that encodes the PCI Bus, Device,
1341 Function and Register.
1342 @param Size The size in bytes of the transfer.
1343 @param Buffer The pointer to a buffer containing the data to write.
1345 @return Size written to StartAddress.
1350 PciExpressWriteBuffer (
1351 IN UINTN StartAddress
,
1358 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1359 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1365 ASSERT (Buffer
!= NULL
);
1368 // Save Size for return
1372 if ((StartAddress
& 1) != 0) {
1374 // Write a byte if StartAddress is byte aligned
1376 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1377 StartAddress
+= sizeof (UINT8
);
1378 Size
-= sizeof (UINT8
);
1379 Buffer
= (UINT8
*)Buffer
+ 1;
1382 if ((Size
>= sizeof (UINT16
)) && ((StartAddress
& 2) != 0)) {
1384 // Write a word if StartAddress is word aligned
1386 PciExpressWrite16 (StartAddress
, ReadUnaligned16 ((UINT16
*)Buffer
));
1387 StartAddress
+= sizeof (UINT16
);
1388 Size
-= sizeof (UINT16
);
1389 Buffer
= (UINT16
*)Buffer
+ 1;
1392 while (Size
>= sizeof (UINT32
)) {
1394 // Write as many double words as possible
1396 PciExpressWrite32 (StartAddress
, ReadUnaligned32 ((UINT32
*)Buffer
));
1397 StartAddress
+= sizeof (UINT32
);
1398 Size
-= sizeof (UINT32
);
1399 Buffer
= (UINT32
*)Buffer
+ 1;
1402 if (Size
>= sizeof (UINT16
)) {
1404 // Write the last remaining word if exist
1406 PciExpressWrite16 (StartAddress
, ReadUnaligned16 ((UINT16
*)Buffer
));
1407 StartAddress
+= sizeof (UINT16
);
1408 Size
-= sizeof (UINT16
);
1409 Buffer
= (UINT16
*)Buffer
+ 1;
1412 if (Size
>= sizeof (UINT8
)) {
1414 // Write the last remaining byte if exist
1416 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);