2 PCI Library functions that use
3 (a) I/O ports 0xCF8 and 0xCFC to perform PCI Configuration cycles, layering
4 on top of one PCI CF8 Library instance; or
5 (b) PCI Library functions that use the 256 MB PCI Express MMIO window to
6 perform PCI Configuration cycles, layering on PCI Express Library.
8 The decision is made in the entry point function, based on the OVMF platform
9 type, and then adhered to during the lifetime of the client module.
11 Copyright (C) 2016, Red Hat, Inc.
13 Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
14 This program and the accompanying materials
15 are licensed and made available under the terms and conditions of the BSD License
16 which accompanies this distribution. The full text of the license may be found at
17 http://opensource.org/licenses/bsd-license.php.
19 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
20 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
27 #include <IndustryStandard/Q35MchIch9.h>
29 #include <Library/PciLib.h>
30 #include <Library/PciCf8Lib.h>
31 #include <Library/PciExpressLib.h>
32 #include <Library/PcdLib.h>
34 STATIC BOOLEAN mRunningOnQ35
;
38 InitializeConfigAccessMethod (
42 mRunningOnQ35
= (PcdGet16 (PcdOvmfHostBridgePciDevId
) ==
43 INTEL_Q35_MCH_DEVICE_ID
);
44 return RETURN_SUCCESS
;
48 Registers a PCI device so PCI configuration registers may be accessed after
49 SetVirtualAddressMap().
51 Registers the PCI device specified by Address so all the PCI configuration registers
52 associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
54 If Address > 0x0FFFFFFF, then ASSERT().
56 @param Address The address that encodes the PCI Bus, Device, Function and
59 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
60 @retval RETURN_UNSUPPORTED An attempt was made to call this function
61 after ExitBootServices().
62 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
63 at runtime could not be mapped.
64 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
65 complete the registration.
70 PciRegisterForRuntimeAccess (
74 return mRunningOnQ35
?
75 PciExpressRegisterForRuntimeAccess (Address
) :
76 PciCf8RegisterForRuntimeAccess (Address
);
80 Reads an 8-bit PCI configuration register.
82 Reads and returns the 8-bit PCI configuration register specified by Address.
83 This function must guarantee that all PCI read and write operations are
86 If Address > 0x0FFFFFFF, then ASSERT().
88 @param Address The address that encodes the PCI Bus, Device, Function and
91 @return The read value from the PCI configuration register.
100 return mRunningOnQ35
?
101 PciExpressRead8 (Address
) :
102 PciCf8Read8 (Address
);
106 Writes an 8-bit PCI configuration register.
108 Writes the 8-bit PCI configuration register specified by Address with the
109 value specified by Value. Value is returned. This function must guarantee
110 that all PCI read and write operations are serialized.
112 If Address > 0x0FFFFFFF, then ASSERT().
114 @param Address The address that encodes the PCI Bus, Device, Function and
116 @param Value The value to write.
118 @return The value written to the PCI configuration register.
128 return mRunningOnQ35
?
129 PciExpressWrite8 (Address
, Value
) :
130 PciCf8Write8 (Address
, Value
);
134 Performs a bitwise OR of an 8-bit PCI configuration register with
137 Reads the 8-bit PCI configuration register specified by Address, performs a
138 bitwise OR between the read result and the value specified by
139 OrData, and writes the result to the 8-bit PCI configuration register
140 specified by Address. The value written to the PCI configuration register is
141 returned. This function must guarantee that all PCI read and write operations
144 If Address > 0x0FFFFFFF, then ASSERT().
146 @param Address The address that encodes the PCI Bus, Device, Function and
148 @param OrData The value to OR with the PCI configuration register.
150 @return The value written back to the PCI configuration register.
160 return mRunningOnQ35
?
161 PciExpressOr8 (Address
, OrData
) :
162 PciCf8Or8 (Address
, OrData
);
166 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
169 Reads the 8-bit PCI configuration register specified by Address, performs a
170 bitwise AND between the read result and the value specified by AndData, and
171 writes the result to the 8-bit PCI configuration register specified by
172 Address. The value written to the PCI configuration register is returned.
173 This function must guarantee that all PCI read and write operations are
176 If Address > 0x0FFFFFFF, then ASSERT().
178 @param Address The address that encodes the PCI Bus, Device, Function and
180 @param AndData The value to AND with the PCI configuration register.
182 @return The value written back to the PCI configuration register.
192 return mRunningOnQ35
?
193 PciExpressAnd8 (Address
, AndData
) :
194 PciCf8And8 (Address
, AndData
);
198 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
199 value, followed a bitwise OR with another 8-bit value.
201 Reads the 8-bit PCI configuration register specified by Address, performs a
202 bitwise AND between the read result and the value specified by AndData,
203 performs a bitwise OR between the result of the AND operation and
204 the value specified by OrData, and writes the result to the 8-bit PCI
205 configuration register specified by Address. The value written to the PCI
206 configuration register is returned. This function must guarantee that all PCI
207 read and write operations are serialized.
209 If Address > 0x0FFFFFFF, then ASSERT().
211 @param Address The address that encodes the PCI Bus, Device, Function and
213 @param AndData The value to AND with the PCI configuration register.
214 @param OrData The value to OR with the result of the AND operation.
216 @return The value written back to the PCI configuration register.
227 return mRunningOnQ35
?
228 PciExpressAndThenOr8 (Address
, AndData
, OrData
) :
229 PciCf8AndThenOr8 (Address
, AndData
, OrData
);
233 Reads a bit field of a PCI configuration register.
235 Reads the bit field in an 8-bit PCI configuration register. The bit field is
236 specified by the StartBit and the EndBit. The value of the bit field is
239 If Address > 0x0FFFFFFF, then ASSERT().
240 If StartBit is greater than 7, then ASSERT().
241 If EndBit is greater than 7, then ASSERT().
242 If EndBit is less than StartBit, then ASSERT().
244 @param Address The PCI configuration register to read.
245 @param StartBit The ordinal of the least significant bit in the bit field.
247 @param EndBit The ordinal of the most significant bit in the bit field.
250 @return The value of the bit field read from the PCI configuration register.
261 return mRunningOnQ35
?
262 PciExpressBitFieldRead8 (Address
, StartBit
, EndBit
) :
263 PciCf8BitFieldRead8 (Address
, StartBit
, EndBit
);
267 Writes a bit field to a PCI configuration register.
269 Writes Value to the bit field of the PCI configuration register. The bit
270 field is specified by the StartBit and the EndBit. All other bits in the
271 destination PCI configuration register are preserved. The new value of the
272 8-bit register is returned.
274 If Address > 0x0FFFFFFF, then ASSERT().
275 If StartBit is greater than 7, then ASSERT().
276 If EndBit is greater than 7, then ASSERT().
277 If EndBit is less than StartBit, then ASSERT().
278 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
280 @param Address The PCI configuration register to write.
281 @param StartBit The ordinal of the least significant bit in the bit field.
283 @param EndBit The ordinal of the most significant bit in the bit field.
285 @param Value The new value of the bit field.
287 @return The value written back to the PCI configuration register.
299 return mRunningOnQ35
?
300 PciExpressBitFieldWrite8 (Address
, StartBit
, EndBit
, Value
) :
301 PciCf8BitFieldWrite8 (Address
, StartBit
, EndBit
, Value
);
305 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
306 writes the result back to the bit field in the 8-bit port.
308 Reads the 8-bit PCI configuration register specified by Address, performs a
309 bitwise OR between the read result and the value specified by
310 OrData, and writes the result to the 8-bit PCI configuration register
311 specified by Address. The value written to the PCI configuration register is
312 returned. This function must guarantee that all PCI read and write operations
313 are serialized. Extra left bits in OrData are stripped.
315 If Address > 0x0FFFFFFF, then ASSERT().
316 If StartBit is greater than 7, then ASSERT().
317 If EndBit is greater than 7, then ASSERT().
318 If EndBit is less than StartBit, then ASSERT().
319 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
321 @param Address The PCI configuration register to write.
322 @param StartBit The ordinal of the least significant bit in the bit field.
324 @param EndBit The ordinal of the most significant bit in the bit field.
326 @param OrData The value to OR with the PCI configuration register.
328 @return The value written back to the PCI configuration register.
340 return mRunningOnQ35
?
341 PciExpressBitFieldOr8 (Address
, StartBit
, EndBit
, OrData
) :
342 PciCf8BitFieldOr8 (Address
, StartBit
, EndBit
, OrData
);
346 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
347 AND, and writes the result back to the bit field in the 8-bit register.
349 Reads the 8-bit PCI configuration register specified by Address, performs a
350 bitwise AND between the read result and the value specified by AndData, and
351 writes the result to the 8-bit PCI configuration register specified by
352 Address. The value written to the PCI configuration register is returned.
353 This function must guarantee that all PCI read and write operations are
354 serialized. Extra left bits in AndData are stripped.
356 If Address > 0x0FFFFFFF, then ASSERT().
357 If StartBit is greater than 7, then ASSERT().
358 If EndBit is greater than 7, then ASSERT().
359 If EndBit is less than StartBit, then ASSERT().
360 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
362 @param Address The PCI configuration register to write.
363 @param StartBit The ordinal of the least significant bit in the bit field.
365 @param EndBit The ordinal of the most significant bit in the bit field.
367 @param AndData The value to AND with the PCI configuration register.
369 @return The value written back to the PCI configuration register.
381 return mRunningOnQ35
?
382 PciExpressBitFieldAnd8 (Address
, StartBit
, EndBit
, AndData
) :
383 PciCf8BitFieldAnd8 (Address
, StartBit
, EndBit
, AndData
);
387 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
388 bitwise OR, and writes the result back to the bit field in the
391 Reads the 8-bit PCI configuration register specified by Address, performs a
392 bitwise AND followed by a bitwise OR between the read result and
393 the value specified by AndData, and writes the result to the 8-bit PCI
394 configuration register specified by Address. The value written to the PCI
395 configuration register is returned. This function must guarantee that all PCI
396 read and write operations are serialized. Extra left bits in both AndData and
399 If Address > 0x0FFFFFFF, then ASSERT().
400 If StartBit is greater than 7, then ASSERT().
401 If EndBit is greater than 7, then ASSERT().
402 If EndBit is less than StartBit, then ASSERT().
403 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
404 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
406 @param Address The PCI configuration register to write.
407 @param StartBit The ordinal of the least significant bit in the bit field.
409 @param EndBit The ordinal of the most significant bit in the bit field.
411 @param AndData The value to AND with the PCI configuration register.
412 @param OrData The value to OR with the result of the AND operation.
414 @return The value written back to the PCI configuration register.
419 PciBitFieldAndThenOr8 (
427 return mRunningOnQ35
?
428 PciExpressBitFieldAndThenOr8 (Address
, StartBit
, EndBit
, AndData
, OrData
) :
429 PciCf8BitFieldAndThenOr8 (Address
, StartBit
, EndBit
, AndData
, OrData
);
433 Reads a 16-bit PCI configuration register.
435 Reads and returns the 16-bit PCI configuration register specified by Address.
436 This function must guarantee that all PCI read and write operations are
439 If Address > 0x0FFFFFFF, then ASSERT().
440 If Address is not aligned on a 16-bit boundary, then ASSERT().
442 @param Address The address that encodes the PCI Bus, Device, Function and
445 @return The read value from the PCI configuration register.
454 return mRunningOnQ35
?
455 PciExpressRead16 (Address
) :
456 PciCf8Read16 (Address
);
460 Writes a 16-bit PCI configuration register.
462 Writes the 16-bit PCI configuration register specified by Address with the
463 value specified by Value. Value is returned. This function must guarantee
464 that all PCI read and write operations are serialized.
466 If Address > 0x0FFFFFFF, then ASSERT().
467 If Address is not aligned on a 16-bit boundary, then ASSERT().
469 @param Address The address that encodes the PCI Bus, Device, Function and
471 @param Value The value to write.
473 @return The value written to the PCI configuration register.
483 return mRunningOnQ35
?
484 PciExpressWrite16 (Address
, Value
) :
485 PciCf8Write16 (Address
, Value
);
489 Performs a bitwise OR of a 16-bit PCI configuration register with
492 Reads the 16-bit PCI configuration register specified by Address, performs a
493 bitwise OR between the read result and the value specified by
494 OrData, and writes the result to the 16-bit PCI configuration register
495 specified by Address. The value written to the PCI configuration register is
496 returned. This function must guarantee that all PCI read and write operations
499 If Address > 0x0FFFFFFF, then ASSERT().
500 If Address is not aligned on a 16-bit boundary, then ASSERT().
502 @param Address The address that encodes the PCI Bus, Device, Function and
504 @param OrData The value to OR with the PCI configuration register.
506 @return The value written back to the PCI configuration register.
516 return mRunningOnQ35
?
517 PciExpressOr16 (Address
, OrData
) :
518 PciCf8Or16 (Address
, OrData
);
522 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
525 Reads the 16-bit PCI configuration register specified by Address, performs a
526 bitwise AND between the read result and the value specified by AndData, and
527 writes the result to the 16-bit PCI configuration register specified by
528 Address. The value written to the PCI configuration register is returned.
529 This function must guarantee that all PCI read and write operations are
532 If Address > 0x0FFFFFFF, then ASSERT().
533 If Address is not aligned on a 16-bit boundary, then ASSERT().
535 @param Address The address that encodes the PCI Bus, Device, Function and
537 @param AndData The value to AND with the PCI configuration register.
539 @return The value written back to the PCI configuration register.
549 return mRunningOnQ35
?
550 PciExpressAnd16 (Address
, AndData
) :
551 PciCf8And16 (Address
, AndData
);
555 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
556 value, followed a bitwise OR with another 16-bit value.
558 Reads the 16-bit PCI configuration register specified by Address, performs a
559 bitwise AND between the read result and the value specified by AndData,
560 performs a bitwise OR between the result of the AND operation and
561 the value specified by OrData, and writes the result to the 16-bit PCI
562 configuration register specified by Address. The value written to the PCI
563 configuration register is returned. This function must guarantee that all PCI
564 read and write operations are serialized.
566 If Address > 0x0FFFFFFF, then ASSERT().
567 If Address is not aligned on a 16-bit boundary, then ASSERT().
569 @param Address The address that encodes the PCI Bus, Device, Function and
571 @param AndData The value to AND with the PCI configuration register.
572 @param OrData The value to OR with the result of the AND operation.
574 @return The value written back to the PCI configuration register.
585 return mRunningOnQ35
?
586 PciExpressAndThenOr16 (Address
, AndData
, OrData
) :
587 PciCf8AndThenOr16 (Address
, AndData
, OrData
);
591 Reads a bit field of a PCI configuration register.
593 Reads the bit field in a 16-bit PCI configuration register. The bit field is
594 specified by the StartBit and the EndBit. The value of the bit field is
597 If Address > 0x0FFFFFFF, then ASSERT().
598 If Address is not aligned on a 16-bit boundary, then ASSERT().
599 If StartBit is greater than 15, then ASSERT().
600 If EndBit is greater than 15, then ASSERT().
601 If EndBit is less than StartBit, then ASSERT().
603 @param Address The PCI configuration register to read.
604 @param StartBit The ordinal of the least significant bit in the bit field.
606 @param EndBit The ordinal of the most significant bit in the bit field.
609 @return The value of the bit field read from the PCI configuration register.
620 return mRunningOnQ35
?
621 PciExpressBitFieldRead16 (Address
, StartBit
, EndBit
) :
622 PciCf8BitFieldRead16 (Address
, StartBit
, EndBit
);
626 Writes a bit field to a PCI configuration register.
628 Writes Value to the bit field of the PCI configuration register. The bit
629 field is specified by the StartBit and the EndBit. All other bits in the
630 destination PCI configuration register are preserved. The new value of the
631 16-bit register is returned.
633 If Address > 0x0FFFFFFF, then ASSERT().
634 If Address is not aligned on a 16-bit boundary, then ASSERT().
635 If StartBit is greater than 15, then ASSERT().
636 If EndBit is greater than 15, then ASSERT().
637 If EndBit is less than StartBit, then ASSERT().
638 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
640 @param Address The PCI configuration register to write.
641 @param StartBit The ordinal of the least significant bit in the bit field.
643 @param EndBit The ordinal of the most significant bit in the bit field.
645 @param Value The new value of the bit field.
647 @return The value written back to the PCI configuration register.
659 return mRunningOnQ35
?
660 PciExpressBitFieldWrite16 (Address
, StartBit
, EndBit
, Value
) :
661 PciCf8BitFieldWrite16 (Address
, StartBit
, EndBit
, Value
);
665 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
666 writes the result back to the bit field in the 16-bit port.
668 Reads the 16-bit PCI configuration register specified by Address, performs a
669 bitwise OR between the read result and the value specified by
670 OrData, and writes the result to the 16-bit PCI configuration register
671 specified by Address. The value written to the PCI configuration register is
672 returned. This function must guarantee that all PCI read and write operations
673 are serialized. Extra left bits in OrData are stripped.
675 If Address > 0x0FFFFFFF, then ASSERT().
676 If Address is not aligned on a 16-bit boundary, then ASSERT().
677 If StartBit is greater than 15, then ASSERT().
678 If EndBit is greater than 15, then ASSERT().
679 If EndBit is less than StartBit, then ASSERT().
680 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
682 @param Address The PCI configuration register to write.
683 @param StartBit The ordinal of the least significant bit in the bit field.
685 @param EndBit The ordinal of the most significant bit in the bit field.
687 @param OrData The value to OR with the PCI configuration register.
689 @return The value written back to the PCI configuration register.
701 return mRunningOnQ35
?
702 PciExpressBitFieldOr16 (Address
, StartBit
, EndBit
, OrData
) :
703 PciCf8BitFieldOr16 (Address
, StartBit
, EndBit
, OrData
);
707 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
708 AND, and writes the result back to the bit field in the 16-bit register.
710 Reads the 16-bit PCI configuration register specified by Address, performs a
711 bitwise AND between the read result and the value specified by AndData, and
712 writes the result to the 16-bit PCI configuration register specified by
713 Address. The value written to the PCI configuration register is returned.
714 This function must guarantee that all PCI read and write operations are
715 serialized. Extra left bits in AndData are stripped.
717 If Address > 0x0FFFFFFF, then ASSERT().
718 If Address is not aligned on a 16-bit boundary, then ASSERT().
719 If StartBit is greater than 15, then ASSERT().
720 If EndBit is greater than 15, then ASSERT().
721 If EndBit is less than StartBit, then ASSERT().
722 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
724 @param Address The PCI configuration register to write.
725 @param StartBit The ordinal of the least significant bit in the bit field.
727 @param EndBit The ordinal of the most significant bit in the bit field.
729 @param AndData The value to AND with the PCI configuration register.
731 @return The value written back to the PCI configuration register.
743 return mRunningOnQ35
?
744 PciExpressBitFieldAnd16 (Address
, StartBit
, EndBit
, AndData
) :
745 PciCf8BitFieldAnd16 (Address
, StartBit
, EndBit
, AndData
);
749 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
750 bitwise OR, and writes the result back to the bit field in the
753 Reads the 16-bit PCI configuration register specified by Address, performs a
754 bitwise AND followed by a bitwise OR between the read result and
755 the value specified by AndData, and writes the result to the 16-bit PCI
756 configuration register specified by Address. The value written to the PCI
757 configuration register is returned. This function must guarantee that all PCI
758 read and write operations are serialized. Extra left bits in both AndData and
761 If Address > 0x0FFFFFFF, then ASSERT().
762 If Address is not aligned on a 16-bit boundary, then ASSERT().
763 If StartBit is greater than 15, then ASSERT().
764 If EndBit is greater than 15, then ASSERT().
765 If EndBit is less than StartBit, then ASSERT().
766 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
767 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
769 @param Address The PCI configuration register to write.
770 @param StartBit The ordinal of the least significant bit in the bit field.
772 @param EndBit The ordinal of the most significant bit in the bit field.
774 @param AndData The value to AND with the PCI configuration register.
775 @param OrData The value to OR with the result of the AND operation.
777 @return The value written back to the PCI configuration register.
782 PciBitFieldAndThenOr16 (
790 return mRunningOnQ35
?
791 PciExpressBitFieldAndThenOr16 (Address
, StartBit
, EndBit
, AndData
, OrData
) :
792 PciCf8BitFieldAndThenOr16 (Address
, StartBit
, EndBit
, AndData
, OrData
);
796 Reads a 32-bit PCI configuration register.
798 Reads and returns the 32-bit PCI configuration register specified by Address.
799 This function must guarantee that all PCI read and write operations are
802 If Address > 0x0FFFFFFF, then ASSERT().
803 If Address is not aligned on a 32-bit boundary, then ASSERT().
805 @param Address The address that encodes the PCI Bus, Device, Function and
808 @return The read value from the PCI configuration register.
817 return mRunningOnQ35
?
818 PciExpressRead32 (Address
) :
819 PciCf8Read32 (Address
);
823 Writes a 32-bit PCI configuration register.
825 Writes the 32-bit PCI configuration register specified by Address with the
826 value specified by Value. Value is returned. This function must guarantee
827 that all PCI read and write operations are serialized.
829 If Address > 0x0FFFFFFF, then ASSERT().
830 If Address is not aligned on a 32-bit boundary, then ASSERT().
832 @param Address The address that encodes the PCI Bus, Device, Function and
834 @param Value The value to write.
836 @return The value written to the PCI configuration register.
846 return mRunningOnQ35
?
847 PciExpressWrite32 (Address
, Value
) :
848 PciCf8Write32 (Address
, Value
);
852 Performs a bitwise OR of a 32-bit PCI configuration register with
855 Reads the 32-bit PCI configuration register specified by Address, performs a
856 bitwise OR between the read result and the value specified by
857 OrData, and writes the result to the 32-bit PCI configuration register
858 specified by Address. The value written to the PCI configuration register is
859 returned. This function must guarantee that all PCI read and write operations
862 If Address > 0x0FFFFFFF, then ASSERT().
863 If Address is not aligned on a 32-bit boundary, then ASSERT().
865 @param Address The address that encodes the PCI Bus, Device, Function and
867 @param OrData The value to OR with the PCI configuration register.
869 @return The value written back to the PCI configuration register.
879 return mRunningOnQ35
?
880 PciExpressOr32 (Address
, OrData
) :
881 PciCf8Or32 (Address
, OrData
);
885 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
888 Reads the 32-bit PCI configuration register specified by Address, performs a
889 bitwise AND between the read result and the value specified by AndData, and
890 writes the result to the 32-bit PCI configuration register specified by
891 Address. The value written to the PCI configuration register is returned.
892 This function must guarantee that all PCI read and write operations are
895 If Address > 0x0FFFFFFF, then ASSERT().
896 If Address is not aligned on a 32-bit boundary, then ASSERT().
898 @param Address The address that encodes the PCI Bus, Device, Function and
900 @param AndData The value to AND with the PCI configuration register.
902 @return The value written back to the PCI configuration register.
912 return mRunningOnQ35
?
913 PciExpressAnd32 (Address
, AndData
) :
914 PciCf8And32 (Address
, AndData
);
918 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
919 value, followed a bitwise OR with another 32-bit value.
921 Reads the 32-bit PCI configuration register specified by Address, performs a
922 bitwise AND between the read result and the value specified by AndData,
923 performs a bitwise OR between the result of the AND operation and
924 the value specified by OrData, and writes the result to the 32-bit PCI
925 configuration register specified by Address. The value written to the PCI
926 configuration register is returned. This function must guarantee that all PCI
927 read and write operations are serialized.
929 If Address > 0x0FFFFFFF, then ASSERT().
930 If Address is not aligned on a 32-bit boundary, then ASSERT().
932 @param Address The address that encodes the PCI Bus, Device, Function and
934 @param AndData The value to AND with the PCI configuration register.
935 @param OrData The value to OR with the result of the AND operation.
937 @return The value written back to the PCI configuration register.
948 return mRunningOnQ35
?
949 PciExpressAndThenOr32 (Address
, AndData
, OrData
) :
950 PciCf8AndThenOr32 (Address
, AndData
, OrData
);
954 Reads a bit field of a PCI configuration register.
956 Reads the bit field in a 32-bit PCI configuration register. The bit field is
957 specified by the StartBit and the EndBit. The value of the bit field is
960 If Address > 0x0FFFFFFF, then ASSERT().
961 If Address is not aligned on a 32-bit boundary, then ASSERT().
962 If StartBit is greater than 31, then ASSERT().
963 If EndBit is greater than 31, then ASSERT().
964 If EndBit is less than StartBit, then ASSERT().
966 @param Address The PCI configuration register to read.
967 @param StartBit The ordinal of the least significant bit in the bit field.
969 @param EndBit The ordinal of the most significant bit in the bit field.
972 @return The value of the bit field read from the PCI configuration register.
983 return mRunningOnQ35
?
984 PciExpressBitFieldRead32 (Address
, StartBit
, EndBit
) :
985 PciCf8BitFieldRead32 (Address
, StartBit
, EndBit
);
989 Writes a bit field to a PCI configuration register.
991 Writes Value to the bit field of the PCI configuration register. The bit
992 field is specified by the StartBit and the EndBit. All other bits in the
993 destination PCI configuration register are preserved. The new value of the
994 32-bit register is returned.
996 If Address > 0x0FFFFFFF, then ASSERT().
997 If Address is not aligned on a 32-bit boundary, then ASSERT().
998 If StartBit is greater than 31, then ASSERT().
999 If EndBit is greater than 31, then ASSERT().
1000 If EndBit is less than StartBit, then ASSERT().
1001 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1003 @param Address The PCI configuration register to write.
1004 @param StartBit The ordinal of the least significant bit in the bit field.
1006 @param EndBit The ordinal of the most significant bit in the bit field.
1008 @param Value The new value of the bit field.
1010 @return The value written back to the PCI configuration register.
1015 PciBitFieldWrite32 (
1022 return mRunningOnQ35
?
1023 PciExpressBitFieldWrite32 (Address
, StartBit
, EndBit
, Value
) :
1024 PciCf8BitFieldWrite32 (Address
, StartBit
, EndBit
, Value
);
1028 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1029 writes the result back to the bit field in the 32-bit port.
1031 Reads the 32-bit PCI configuration register specified by Address, performs a
1032 bitwise OR between the read result and the value specified by
1033 OrData, and writes the result to the 32-bit PCI configuration register
1034 specified by Address. The value written to the PCI configuration register is
1035 returned. This function must guarantee that all PCI read and write operations
1036 are serialized. Extra left bits in OrData are stripped.
1038 If Address > 0x0FFFFFFF, then ASSERT().
1039 If Address is not aligned on a 32-bit boundary, then ASSERT().
1040 If StartBit is greater than 31, then ASSERT().
1041 If EndBit is greater than 31, then ASSERT().
1042 If EndBit is less than StartBit, then ASSERT().
1043 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1045 @param Address The PCI configuration register to write.
1046 @param StartBit The ordinal of the least significant bit in the bit field.
1048 @param EndBit The ordinal of the most significant bit in the bit field.
1050 @param OrData The value to OR with the PCI configuration register.
1052 @return The value written back to the PCI configuration register.
1064 return mRunningOnQ35
?
1065 PciExpressBitFieldOr32 (Address
, StartBit
, EndBit
, OrData
) :
1066 PciCf8BitFieldOr32 (Address
, StartBit
, EndBit
, OrData
);
1070 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1071 AND, and writes the result back to the bit field in the 32-bit register.
1073 Reads the 32-bit PCI configuration register specified by Address, performs a
1074 bitwise AND between the read result and the value specified by AndData, and
1075 writes the result to the 32-bit PCI configuration register specified by
1076 Address. The value written to the PCI configuration register is returned.
1077 This function must guarantee that all PCI read and write operations are
1078 serialized. Extra left bits in AndData are stripped.
1080 If Address > 0x0FFFFFFF, then ASSERT().
1081 If Address is not aligned on a 32-bit boundary, then ASSERT().
1082 If StartBit is greater than 31, then ASSERT().
1083 If EndBit is greater than 31, then ASSERT().
1084 If EndBit is less than StartBit, then ASSERT().
1085 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1087 @param Address The PCI configuration register to write.
1088 @param StartBit The ordinal of the least significant bit in the bit field.
1090 @param EndBit The ordinal of the most significant bit in the bit field.
1092 @param AndData The value to AND with the PCI configuration register.
1094 @return The value written back to the PCI configuration register.
1106 return mRunningOnQ35
?
1107 PciExpressBitFieldAnd32 (Address
, StartBit
, EndBit
, AndData
) :
1108 PciCf8BitFieldAnd32 (Address
, StartBit
, EndBit
, AndData
);
1112 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1113 bitwise OR, and writes the result back to the bit field in the
1116 Reads the 32-bit PCI configuration register specified by Address, performs a
1117 bitwise AND followed by a bitwise OR between the read result and
1118 the value specified by AndData, and writes the result to the 32-bit PCI
1119 configuration register specified by Address. The value written to the PCI
1120 configuration register is returned. This function must guarantee that all PCI
1121 read and write operations are serialized. Extra left bits in both AndData and
1122 OrData are stripped.
1124 If Address > 0x0FFFFFFF, then ASSERT().
1125 If Address is not aligned on a 32-bit boundary, then ASSERT().
1126 If StartBit is greater than 31, then ASSERT().
1127 If EndBit is greater than 31, then ASSERT().
1128 If EndBit is less than StartBit, then ASSERT().
1129 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1130 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1132 @param Address The PCI configuration register to write.
1133 @param StartBit The ordinal of the least significant bit in the bit field.
1135 @param EndBit The ordinal of the most significant bit in the bit field.
1137 @param AndData The value to AND with the PCI configuration register.
1138 @param OrData The value to OR with the result of the AND operation.
1140 @return The value written back to the PCI configuration register.
1145 PciBitFieldAndThenOr32 (
1153 return mRunningOnQ35
?
1154 PciExpressBitFieldAndThenOr32 (Address
, StartBit
, EndBit
, AndData
, OrData
) :
1155 PciCf8BitFieldAndThenOr32 (Address
, StartBit
, EndBit
, AndData
, OrData
);
1159 Reads a range of PCI configuration registers into a caller supplied buffer.
1161 Reads the range of PCI configuration registers specified by StartAddress and
1162 Size into the buffer specified by Buffer. This function only allows the PCI
1163 configuration registers from a single PCI function to be read. Size is
1164 returned. When possible 32-bit PCI configuration read cycles are used to read
1165 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1166 and 16-bit PCI configuration read cycles may be used at the beginning and the
1169 If StartAddress > 0x0FFFFFFF, then ASSERT().
1170 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1171 If Size > 0 and Buffer is NULL, then ASSERT().
1173 @param StartAddress The starting address that encodes the PCI Bus, Device,
1174 Function and Register.
1175 @param Size The size in bytes of the transfer.
1176 @param Buffer The pointer to a buffer receiving the data read.
1184 IN UINTN StartAddress
,
1189 return mRunningOnQ35
?
1190 PciExpressReadBuffer (StartAddress
, Size
, Buffer
) :
1191 PciCf8ReadBuffer (StartAddress
, Size
, Buffer
);
1195 Copies the data in a caller supplied buffer to a specified range of PCI
1196 configuration space.
1198 Writes the range of PCI configuration registers specified by StartAddress and
1199 Size from the buffer specified by Buffer. This function only allows the PCI
1200 configuration registers from a single PCI function to be written. Size is
1201 returned. When possible 32-bit PCI configuration write cycles are used to
1202 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1203 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1204 and the end of the range.
1206 If StartAddress > 0x0FFFFFFF, then ASSERT().
1207 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1208 If Size > 0 and Buffer is NULL, then ASSERT().
1210 @param StartAddress The starting address that encodes the PCI Bus, Device,
1211 Function and Register.
1212 @param Size The size in bytes of the transfer.
1213 @param Buffer The pointer to a buffer containing the data to write.
1215 @return Size written to StartAddress.
1221 IN UINTN StartAddress
,
1226 return mRunningOnQ35
?
1227 PciExpressWriteBuffer (StartAddress
, Size
, Buffer
) :
1228 PciCf8WriteBuffer (StartAddress
, Size
, Buffer
);