2 Memory Detection for Virtual Machines.
4 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
14 // The package level header files this module uses
16 #include <IndustryStandard/E820.h>
17 #include <IndustryStandard/I440FxPiix4.h>
18 #include <IndustryStandard/Q35MchIch9.h>
19 #include <IndustryStandard/CloudHv.h>
20 #include <IndustryStandard/Xen/arch-x86/hvm/start_info.h>
22 #include <Register/Intel/SmramSaveStateMap.h>
25 // The Library classes this module consumes
27 #include <Library/BaseLib.h>
28 #include <Library/BaseMemoryLib.h>
29 #include <Library/DebugLib.h>
30 #include <Library/HardwareInfoLib.h>
31 #include <Library/HobLib.h>
32 #include <Library/IoLib.h>
33 #include <Library/MemEncryptSevLib.h>
34 #include <Library/PcdLib.h>
35 #include <Library/PciLib.h>
36 #include <Library/PeimEntryPoint.h>
37 #include <Library/ResourcePublicationLib.h>
38 #include <Library/MtrrLib.h>
39 #include <Library/QemuFwCfgLib.h>
40 #include <Library/QemuFwCfgSimpleParserLib.h>
41 #include <Library/TdxLib.h>
43 #include <Library/PlatformInitLib.h>
47 PlatformQemuUc32BaseInitialization (
48 IN OUT EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
51 UINT32 LowerMemorySize
;
53 if (PlatformInfoHob
->HostBridgeDevId
== 0xffff /* microvm */) {
57 if (PlatformInfoHob
->HostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
58 LowerMemorySize
= PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob
);
59 ASSERT (PcdGet64 (PcdPciExpressBaseAddress
) <= MAX_UINT32
);
60 ASSERT (PcdGet64 (PcdPciExpressBaseAddress
) >= LowerMemorySize
);
62 if (LowerMemorySize
<= BASE_2GB
) {
63 // Newer qemu with gigabyte aligned memory,
64 // 32-bit pci mmio window is 2G -> 4G then.
65 PlatformInfoHob
->Uc32Base
= BASE_2GB
;
68 // On q35, the 32-bit area that we'll mark as UC, through variable MTRRs,
69 // starts at PcdPciExpressBaseAddress. The platform DSC is responsible for
70 // setting PcdPciExpressBaseAddress such that describing the
71 // [PcdPciExpressBaseAddress, 4GB) range require a very small number of
72 // variable MTRRs (preferably 1 or 2).
74 PlatformInfoHob
->Uc32Base
= (UINT32
)PcdGet64 (PcdPciExpressBaseAddress
);
80 if (PlatformInfoHob
->HostBridgeDevId
== CLOUDHV_DEVICE_ID
) {
81 PlatformInfoHob
->Uc32Size
= CLOUDHV_MMIO_HOLE_SIZE
;
82 PlatformInfoHob
->Uc32Base
= CLOUDHV_MMIO_HOLE_ADDRESS
;
86 ASSERT (PlatformInfoHob
->HostBridgeDevId
== INTEL_82441_DEVICE_ID
);
88 // On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one
89 // variable MTRR suffices by truncating the size to a whole power of two,
90 // while keeping the end affixed to 4GB. This will round the base up.
92 LowerMemorySize
= PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob
);
93 PlatformInfoHob
->Uc32Size
= GetPowerOfTwo32 ((UINT32
)(SIZE_4GB
- LowerMemorySize
));
94 PlatformInfoHob
->Uc32Base
= (UINT32
)(SIZE_4GB
- PlatformInfoHob
->Uc32Size
);
96 // Assuming that LowerMemorySize is at least 1 byte, Uc32Size is at most 2GB.
97 // Therefore Uc32Base is at least 2GB.
99 ASSERT (PlatformInfoHob
->Uc32Base
>= BASE_2GB
);
101 if (PlatformInfoHob
->Uc32Base
!= LowerMemorySize
) {
104 "%a: rounded UC32 base from 0x%x up to 0x%x, for "
105 "an UC32 size of 0x%x\n",
108 PlatformInfoHob
->Uc32Base
,
109 PlatformInfoHob
->Uc32Size
115 Iterate over the RAM entries in QEMU's fw_cfg E820 RAM map that start outside
116 of the 32-bit address range.
118 Find the highest exclusive >=4GB RAM address, or produce memory resource
119 descriptor HOBs for RAM entries that start at or above 4GB.
121 @param[out] MaxAddress If MaxAddress is NULL, then PlatformScanOrAdd64BitE820Ram()
122 produces memory resource descriptor HOBs for RAM
123 entries that start at or above 4GB.
125 Otherwise, MaxAddress holds the highest exclusive
126 >=4GB RAM address on output. If QEMU's fw_cfg E820
127 RAM map contains no RAM entry that starts outside of
128 the 32-bit address range, then MaxAddress is exactly
131 @retval EFI_SUCCESS The fw_cfg E820 RAM map was found and processed.
133 @retval EFI_PROTOCOL_ERROR The RAM map was found, but its size wasn't a
134 whole multiple of sizeof(EFI_E820_ENTRY64). No
135 RAM entry was processed.
137 @return Error codes from QemuFwCfgFindFile(). No RAM
142 PlatformScanOrAdd64BitE820Ram (
143 IN BOOLEAN AddHighHob
,
144 OUT UINT64
*LowMemory OPTIONAL
,
145 OUT UINT64
*MaxAddress OPTIONAL
149 FIRMWARE_CONFIG_ITEM FwCfgItem
;
151 EFI_E820_ENTRY64 E820Entry
;
154 Status
= QemuFwCfgFindFile ("etc/e820", &FwCfgItem
, &FwCfgSize
);
155 if (EFI_ERROR (Status
)) {
159 if (FwCfgSize
% sizeof E820Entry
!= 0) {
160 return EFI_PROTOCOL_ERROR
;
163 if (LowMemory
!= NULL
) {
167 if (MaxAddress
!= NULL
) {
168 *MaxAddress
= BASE_4GB
;
171 QemuFwCfgSelectItem (FwCfgItem
);
172 for (Processed
= 0; Processed
< FwCfgSize
; Processed
+= sizeof E820Entry
) {
173 QemuFwCfgReadBytes (sizeof E820Entry
, &E820Entry
);
176 "%a: Base=0x%Lx Length=0x%Lx Type=%u\n",
182 if (E820Entry
.Type
== EfiAcpiAddressRangeMemory
) {
183 if (AddHighHob
&& (E820Entry
.BaseAddr
>= BASE_4GB
)) {
188 // Round up the start address, and round down the end address.
190 Base
= ALIGN_VALUE (E820Entry
.BaseAddr
, (UINT64
)EFI_PAGE_SIZE
);
191 End
= (E820Entry
.BaseAddr
+ E820Entry
.Length
) &
192 ~(UINT64
)EFI_PAGE_MASK
;
194 PlatformAddMemoryRangeHob (Base
, End
);
197 "%a: PlatformAddMemoryRangeHob [0x%Lx, 0x%Lx)\n",
205 if (MaxAddress
|| LowMemory
) {
208 Candidate
= E820Entry
.BaseAddr
+ E820Entry
.Length
;
209 if (MaxAddress
&& (Candidate
> *MaxAddress
)) {
210 *MaxAddress
= Candidate
;
213 "%a: MaxAddress=0x%Lx\n",
219 if (LowMemory
&& (Candidate
> *LowMemory
) && (Candidate
< BASE_4GB
)) {
220 *LowMemory
= Candidate
;
223 "%a: LowMemory=0x%Lx\n",
238 @param Entries Pointer to PVH memmap
239 @param Count Number of entries
244 GetPvhMemmapEntries (
245 struct hvm_memmap_table_entry
**Entries
,
249 UINT32
*PVHResetVectorData
;
250 struct hvm_start_info
*pvh_start_info
;
252 PVHResetVectorData
= (VOID
*)(UINTN
)PcdGet32 (PcdXenPvhStartOfDayStructPtr
);
253 if (PVHResetVectorData
== 0) {
254 return EFI_NOT_FOUND
;
257 pvh_start_info
= (struct hvm_start_info
*)(UINTN
)PVHResetVectorData
[0];
259 *Entries
= (struct hvm_memmap_table_entry
*)(UINTN
)pvh_start_info
->memmap_paddr
;
260 *Count
= pvh_start_info
->memmap_entries
;
267 GetHighestSystemMemoryAddressFromPvhMemmap (
271 struct hvm_memmap_table_entry
*Memmap
;
272 UINT32 MemmapEntriesCount
;
273 struct hvm_memmap_table_entry
*Entry
;
276 UINT64 HighestAddress
;
281 Status
= GetPvhMemmapEntries (&Memmap
, &MemmapEntriesCount
);
282 ASSERT_EFI_ERROR (Status
);
284 for (Loop
= 0; Loop
< MemmapEntriesCount
; Loop
++) {
285 Entry
= Memmap
+ Loop
;
286 EntryEnd
= Entry
->addr
+ Entry
->size
;
288 if ((Entry
->type
== XEN_HVM_MEMMAP_TYPE_RAM
) &&
289 (EntryEnd
> HighestAddress
))
291 if (Below4gb
&& (EntryEnd
<= BASE_4GB
)) {
292 HighestAddress
= EntryEnd
;
293 } else if (!Below4gb
&& (EntryEnd
>= BASE_4GB
)) {
294 HighestAddress
= EntryEnd
;
299 return HighestAddress
;
304 PlatformGetSystemMemorySizeBelow4gb (
305 IN EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
309 UINT64 LowerMemorySize
= 0;
313 if (PlatformInfoHob
->HostBridgeDevId
== CLOUDHV_DEVICE_ID
) {
314 // Get the information from PVH memmap
315 return (UINT32
)GetHighestSystemMemoryAddressFromPvhMemmap (TRUE
);
318 Status
= PlatformScanOrAdd64BitE820Ram (FALSE
, &LowerMemorySize
, NULL
);
319 if ((Status
== EFI_SUCCESS
) && (LowerMemorySize
> 0)) {
320 return (UINT32
)LowerMemorySize
;
324 // CMOS 0x34/0x35 specifies the system memory above 16 MB.
325 // * CMOS(0x35) is the high byte
326 // * CMOS(0x34) is the low byte
327 // * The size is specified in 64kb chunks
328 // * Since this is memory above 16MB, the 16MB must be added
329 // into the calculation to get the total memory size.
332 Cmos0x34
= (UINT8
)PlatformCmosRead8 (0x34);
333 Cmos0x35
= (UINT8
)PlatformCmosRead8 (0x35);
335 return (UINT32
)(((UINTN
)((Cmos0x35
<< 8) + Cmos0x34
) << 16) + SIZE_16MB
);
340 PlatformGetSystemMemorySizeAbove4gb (
347 // CMOS 0x5b-0x5d specifies the system memory above 4GB MB.
348 // * CMOS(0x5d) is the most significant size byte
349 // * CMOS(0x5c) is the middle size byte
350 // * CMOS(0x5b) is the least significant size byte
351 // * The size is specified in 64kb chunks
355 for (CmosIndex
= 0x5d; CmosIndex
>= 0x5b; CmosIndex
--) {
356 Size
= (UINT32
)(Size
<< 8) + (UINT32
)PlatformCmosRead8 (CmosIndex
);
359 return LShiftU64 (Size
, 16);
363 Return the highest address that DXE could possibly use, plus one.
367 PlatformGetFirstNonAddress (
368 IN OUT EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
371 UINT64 FirstNonAddress
;
372 UINT32 FwCfgPciMmio64Mb
;
374 FIRMWARE_CONFIG_ITEM FwCfgItem
;
376 UINT64 HotPlugMemoryEnd
;
379 // set FirstNonAddress to suppress incorrect compiler/analyzer warnings
384 // If QEMU presents an E820 map, then get the highest exclusive >=4GB RAM
385 // address from it. This can express an address >= 4GB+1TB.
387 // Otherwise, get the flat size of the memory above 4GB from the CMOS (which
388 // can only express a size smaller than 1TB), and add it to 4GB.
390 Status
= PlatformScanOrAdd64BitE820Ram (FALSE
, NULL
, &FirstNonAddress
);
391 if (EFI_ERROR (Status
)) {
392 FirstNonAddress
= BASE_4GB
+ PlatformGetSystemMemorySizeAbove4gb ();
396 // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO
397 // resources to 32-bit anyway. See DegradeResource() in
398 // "PciResourceSupport.c".
401 if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode
)) {
402 return FirstNonAddress
;
408 // See if the user specified the number of megabytes for the 64-bit PCI host
409 // aperture. Accept an aperture size up to 16TB.
411 // As signaled by the "X-" prefix, this knob is experimental, and might go
414 Status
= QemuFwCfgParseUint32 (
415 "opt/ovmf/X-PciMmio64Mb",
420 case EFI_UNSUPPORTED
:
424 if (FwCfgPciMmio64Mb
<= 0x1000000) {
425 PlatformInfoHob
->PcdPciMmio64Size
= LShiftU64 (FwCfgPciMmio64Mb
, 20);
435 "%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\n",
441 if (PlatformInfoHob
->PcdPciMmio64Size
== 0) {
442 if (PlatformInfoHob
->BootMode
!= BOOT_ON_S3_RESUME
) {
445 "%a: disabling 64-bit PCI host aperture\n",
451 // There's nothing more to do; the amount of memory above 4GB fully
452 // determines the highest address plus one. The memory hotplug area (see
453 // below) plays no role for the firmware in this case.
455 return FirstNonAddress
;
459 // The "etc/reserved-memory-end" fw_cfg file, when present, contains an
460 // absolute, exclusive end address for the memory hotplug area. This area
461 // starts right at the end of the memory above 4GB. The 64-bit PCI host
462 // aperture must be placed above it.
464 Status
= QemuFwCfgFindFile (
465 "etc/reserved-memory-end",
469 if (!EFI_ERROR (Status
) && (FwCfgSize
== sizeof HotPlugMemoryEnd
)) {
470 QemuFwCfgSelectItem (FwCfgItem
);
471 QemuFwCfgReadBytes (FwCfgSize
, &HotPlugMemoryEnd
);
474 "%a: HotPlugMemoryEnd=0x%Lx\n",
479 ASSERT (HotPlugMemoryEnd
>= FirstNonAddress
);
480 FirstNonAddress
= HotPlugMemoryEnd
;
484 // SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB, so
485 // that the host can map it with 1GB hugepages. Follow suit.
487 PlatformInfoHob
->PcdPciMmio64Base
= ALIGN_VALUE (FirstNonAddress
, (UINT64
)SIZE_1GB
);
488 PlatformInfoHob
->PcdPciMmio64Size
= ALIGN_VALUE (PlatformInfoHob
->PcdPciMmio64Size
, (UINT64
)SIZE_1GB
);
491 // The 64-bit PCI host aperture should also be "naturally" aligned. The
492 // alignment is determined by rounding the size of the aperture down to the
493 // next smaller or equal power of two. That is, align the aperture by the
494 // largest BAR size that can fit into it.
496 PlatformInfoHob
->PcdPciMmio64Base
= ALIGN_VALUE (PlatformInfoHob
->PcdPciMmio64Base
, GetPowerOfTwo64 (PlatformInfoHob
->PcdPciMmio64Size
));
499 // The useful address space ends with the 64-bit PCI host aperture.
501 FirstNonAddress
= PlatformInfoHob
->PcdPciMmio64Base
+ PlatformInfoHob
->PcdPciMmio64Size
;
502 return FirstNonAddress
;
506 * Use CPUID to figure physical address width. Does *not* work
507 * reliable on qemu. For historical reasons qemu returns phys-bits=40
508 * even in case the host machine supports less than that.
510 * qemu has a cpu property (host-phys-bits={on,off}) to change that
511 * and make sure guest phys-bits are not larger than host phys-bits.,
512 * but it is off by default. Exception: microvm machine type
513 * hard-wires that property to on.
517 PlatformAddressWidthFromCpuid (
518 IN OUT EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
523 AsmCpuid (0x80000000, &RegEax
, NULL
, NULL
, NULL
);
524 if (RegEax
>= 0x80000008) {
525 AsmCpuid (0x80000008, &RegEax
, NULL
, NULL
, NULL
);
526 PlatformInfoHob
->PhysMemAddressWidth
= (UINT8
)RegEax
;
528 PlatformInfoHob
->PhysMemAddressWidth
= 36;
531 PlatformInfoHob
->FirstNonAddress
= LShiftU64 (1, PlatformInfoHob
->PhysMemAddressWidth
);
535 "%a: cpuid: phys-bits is %d\n",
537 PlatformInfoHob
->PhysMemAddressWidth
542 Iterate over the PCI host bridges resources information optionally provided
543 in fw-cfg and find the highest address contained in the PCI MMIO windows. If
544 the information is found, return the exclusive end; one past the last usable
547 @param[out] PciMmioAddressEnd Pointer to one-after End Address updated with
548 information extracted from host-provided data
549 or zero if no information available or an
552 @retval EFI_SUCCESS PCI information was read and the output
553 parameter updated with the last valid
554 address in the 64-bit MMIO range.
555 @retval EFI_INVALID_PARAMETER Pointer parameter is invalid
556 @retval EFI_INCOMPATIBLE_VERSION Hardware information found in fw-cfg
557 has an incompatible format
558 @retval EFI_UNSUPPORTED Fw-cfg is not supported, thus host
559 provided information, if any, cannot be
561 @retval EFI_NOT_FOUND No PCI host bridge information provided
566 PlatformScanHostProvided64BitPciMmioEnd (
567 OUT UINT64
*PciMmioAddressEnd
571 HOST_BRIDGE_INFO HostBridge
;
572 FIRMWARE_CONFIG_ITEM FwCfgItem
;
574 UINTN FwCfgReadIndex
;
576 UINT64 Above4GMmioEnd
;
578 if (PciMmioAddressEnd
== NULL
) {
579 return EFI_INVALID_PARAMETER
;
582 *PciMmioAddressEnd
= 0;
585 Status
= QemuFwCfgFindFile ("etc/hardware-info", &FwCfgItem
, &FwCfgSize
);
586 if (EFI_ERROR (Status
)) {
590 QemuFwCfgSelectItem (FwCfgItem
);
593 while (FwCfgReadIndex
< FwCfgSize
) {
594 Status
= QemuFwCfgReadNextHardwareInfoByType (
595 HardwareInfoTypeHostBridge
,
603 if (Status
!= EFI_SUCCESS
) {
605 // No more data available to read in the file, break
606 // loop and finish process
611 Status
= HardwareInfoPciHostBridgeLastMmioAddress (
618 if (Status
!= EFI_SUCCESS
) {
620 // Error parsing MMIO apertures and extracting last MMIO
621 // address, reset PciMmioAddressEnd as if no information was
622 // found, to avoid moving forward with incomplete data, and
627 "%a: ignoring malformed hardware information from fw_cfg\n",
630 *PciMmioAddressEnd
= 0;
634 if (Above4GMmioEnd
> *PciMmioAddressEnd
) {
635 *PciMmioAddressEnd
= Above4GMmioEnd
;
639 if (*PciMmioAddressEnd
> 0) {
641 // Host-provided PCI information was found and a MMIO window end
643 // Increase the End address by one to have the output pointing to
644 // one after the address in use (exclusive end).
646 *PciMmioAddressEnd
+= 1;
650 "%a: Pci64End=0x%Lx\n",
658 return EFI_NOT_FOUND
;
662 Initialize the PhysMemAddressWidth field in PlatformInfoHob based on guest RAM size.
666 PlatformAddressWidthInitialization (
667 IN OUT EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
670 UINT64 FirstNonAddress
;
671 UINT8 PhysMemAddressWidth
;
674 if (PlatformInfoHob
->HostBridgeDevId
== 0xffff /* microvm */) {
675 PlatformAddressWidthFromCpuid (PlatformInfoHob
);
680 // First scan host-provided hardware information to assess if the address
681 // space is already known. If so, guest must use those values.
683 Status
= PlatformScanHostProvided64BitPciMmioEnd (&FirstNonAddress
);
685 if (EFI_ERROR (Status
)) {
687 // If the host did not provide valid hardware information leading to a
688 // hard-defined 64-bit MMIO end, fold back to calculating the minimum range
690 // As guest-physical memory size grows, the permanent PEI RAM requirements
691 // are dominated by the identity-mapping page tables built by the DXE IPL.
692 // The DXL IPL keys off of the physical address bits advertized in the CPU
693 // HOB. To conserve memory, we calculate the minimum address width here.
695 FirstNonAddress
= PlatformGetFirstNonAddress (PlatformInfoHob
);
698 PhysMemAddressWidth
= (UINT8
)HighBitSet64 (FirstNonAddress
);
701 // If FirstNonAddress is not an integral power of two, then we need an
704 if ((FirstNonAddress
& (FirstNonAddress
- 1)) != 0) {
705 ++PhysMemAddressWidth
;
709 // The minimum address width is 36 (covers up to and excluding 64 GB, which
710 // is the maximum for Ia32 + PAE). The theoretical architecture maximum for
711 // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We
712 // can simply assert that here, since 48 bits are good enough for 256 TB.
714 if (PhysMemAddressWidth
<= 36) {
715 PhysMemAddressWidth
= 36;
718 #if defined (MDE_CPU_X64)
719 if (TdIsEnabled ()) {
720 if (TdSharedPageMask () == (1ULL << 47)) {
721 PhysMemAddressWidth
= 48;
723 PhysMemAddressWidth
= 52;
727 ASSERT (PhysMemAddressWidth
<= 52);
729 ASSERT (PhysMemAddressWidth
<= 48);
732 PlatformInfoHob
->FirstNonAddress
= FirstNonAddress
;
733 PlatformInfoHob
->PhysMemAddressWidth
= PhysMemAddressWidth
;
738 QemuInitializeRamBelow1gb (
739 IN EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
742 if (PlatformInfoHob
->SmmSmramRequire
&& PlatformInfoHob
->Q35SmramAtDefaultSmbase
) {
743 PlatformAddMemoryRangeHob (0, SMM_DEFAULT_SMBASE
);
744 PlatformAddReservedMemoryBaseSizeHob (
746 MCH_DEFAULT_SMBASE_SIZE
,
750 SMM_DEFAULT_SMBASE
+ MCH_DEFAULT_SMBASE_SIZE
< BASE_512KB
+ BASE_128KB
,
751 "end of SMRAM at default SMBASE ends at, or exceeds, 640KB"
753 PlatformAddMemoryRangeHob (
754 SMM_DEFAULT_SMBASE
+ MCH_DEFAULT_SMBASE_SIZE
,
755 BASE_512KB
+ BASE_128KB
758 PlatformAddMemoryRangeHob (0, BASE_512KB
+ BASE_128KB
);
763 Peform Memory Detection for QEMU / KVM
768 PlatformQemuInitializeRam (
769 IN EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
772 UINT64 LowerMemorySize
;
773 UINT64 UpperMemorySize
;
774 MTRR_SETTINGS MtrrSettings
;
777 DEBUG ((DEBUG_INFO
, "%a called\n", __FUNCTION__
));
780 // Determine total memory size available
782 LowerMemorySize
= PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob
);
784 if (PlatformInfoHob
->BootMode
== BOOT_ON_S3_RESUME
) {
786 // Create the following memory HOB as an exception on the S3 boot path.
788 // Normally we'd create memory HOBs only on the normal boot path. However,
789 // CpuMpPei specifically needs such a low-memory HOB on the S3 path as
790 // well, for "borrowing" a subset of it temporarily, for the AP startup
793 // CpuMpPei saves the original contents of the borrowed area in permanent
794 // PEI RAM, in a backup buffer allocated with the normal PEI services.
795 // CpuMpPei restores the original contents ("returns" the borrowed area) at
796 // End-of-PEI. End-of-PEI in turn is emitted by S3Resume2Pei before
797 // transferring control to the OS's wakeup vector in the FACS.
799 // We expect any other PEIMs that "borrow" memory similarly to CpuMpPei to
800 // restore the original contents. Furthermore, we expect all such PEIMs
801 // (CpuMpPei included) to claim the borrowed areas by producing memory
802 // allocation HOBs, and to honor preexistent memory allocation HOBs when
803 // looking for an area to borrow.
805 QemuInitializeRamBelow1gb (PlatformInfoHob
);
808 // Create memory HOBs
810 QemuInitializeRamBelow1gb (PlatformInfoHob
);
812 if (PlatformInfoHob
->SmmSmramRequire
) {
815 TsegSize
= PlatformInfoHob
->Q35TsegMbytes
* SIZE_1MB
;
816 PlatformAddMemoryRangeHob (BASE_1MB
, LowerMemorySize
- TsegSize
);
817 PlatformAddReservedMemoryBaseSizeHob (
818 LowerMemorySize
- TsegSize
,
823 PlatformAddMemoryRangeHob (BASE_1MB
, LowerMemorySize
);
827 // If QEMU presents an E820 map, then create memory HOBs for the >=4GB RAM
828 // entries. Otherwise, create a single memory HOB with the flat >=4GB
829 // memory size read from the CMOS.
831 Status
= PlatformScanOrAdd64BitE820Ram (TRUE
, NULL
, NULL
);
832 if (EFI_ERROR (Status
)) {
833 UpperMemorySize
= PlatformGetSystemMemorySizeAbove4gb ();
834 if (UpperMemorySize
!= 0) {
835 PlatformAddMemoryBaseSizeHob (BASE_4GB
, UpperMemorySize
);
841 // We'd like to keep the following ranges uncached:
843 // - [LowerMemorySize, 4 GB)
845 // Everything else should be WB. Unfortunately, programming the inverse (ie.
846 // keeping the default UC, and configuring the complement set of the above as
847 // WB) is not reliable in general, because the end of the upper RAM can have
848 // practically any alignment, and we may not have enough variable MTRRs to
851 if (IsMtrrSupported () && (PlatformInfoHob
->HostBridgeDevId
!= CLOUDHV_DEVICE_ID
)) {
852 MtrrGetAllMtrrs (&MtrrSettings
);
855 // MTRRs disabled, fixed MTRRs disabled, default type is uncached
857 ASSERT ((MtrrSettings
.MtrrDefType
& BIT11
) == 0);
858 ASSERT ((MtrrSettings
.MtrrDefType
& BIT10
) == 0);
859 ASSERT ((MtrrSettings
.MtrrDefType
& 0xFF) == 0);
862 // flip default type to writeback
864 SetMem (&MtrrSettings
.Fixed
, sizeof MtrrSettings
.Fixed
, 0x06);
865 ZeroMem (&MtrrSettings
.Variables
, sizeof MtrrSettings
.Variables
);
866 MtrrSettings
.MtrrDefType
|= BIT11
| BIT10
| 6;
867 MtrrSetAllMtrrs (&MtrrSettings
);
870 // Set memory range from 640KB to 1MB to uncacheable
872 Status
= MtrrSetMemoryAttribute (
873 BASE_512KB
+ BASE_128KB
,
874 BASE_1MB
- (BASE_512KB
+ BASE_128KB
),
877 ASSERT_EFI_ERROR (Status
);
880 // Set the memory range from the start of the 32-bit MMIO area (32-bit PCI
881 // MMIO aperture on i440fx, PCIEXBAR on q35) to 4GB as uncacheable.
883 Status
= MtrrSetMemoryAttribute (
884 PlatformInfoHob
->Uc32Base
,
885 SIZE_4GB
- PlatformInfoHob
->Uc32Base
,
888 ASSERT_EFI_ERROR (Status
);
894 PlatformQemuInitializeRamForS3 (
895 IN EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
898 if (PlatformInfoHob
->S3Supported
&& (PlatformInfoHob
->BootMode
!= BOOT_ON_S3_RESUME
)) {
900 // This is the memory range that will be used for PEI on S3 resume
902 BuildMemoryAllocationHob (
903 PlatformInfoHob
->S3AcpiReservedMemoryBase
,
904 PlatformInfoHob
->S3AcpiReservedMemorySize
,
909 // Cover the initial RAM area used as stack and temporary PEI heap.
911 // This is reserved as ACPI NVS so it can be used on S3 resume.
913 BuildMemoryAllocationHob (
914 PcdGet32 (PcdOvmfSecPeiTempRamBase
),
915 PcdGet32 (PcdOvmfSecPeiTempRamSize
),
920 // SEC stores its table of GUIDed section handlers here.
922 BuildMemoryAllocationHob (
923 PcdGet64 (PcdGuidedExtractHandlerTableAddress
),
924 PcdGet32 (PcdGuidedExtractHandlerTableSize
),
930 // Reserve the initial page tables built by the reset vector code.
932 // Since this memory range will be used by the Reset Vector on S3
933 // resume, it must be reserved as ACPI NVS.
935 BuildMemoryAllocationHob (
936 (EFI_PHYSICAL_ADDRESS
)(UINTN
)PcdGet32 (PcdOvmfSecPageTablesBase
),
937 (UINT64
)(UINTN
)PcdGet32 (PcdOvmfSecPageTablesSize
),
941 if (PlatformInfoHob
->SevEsIsEnabled
) {
943 // If SEV-ES is enabled, reserve the GHCB-related memory area. This
944 // includes the extra page table used to break down the 2MB page
945 // mapping into 4KB page entries where the GHCB resides and the
948 // Since this memory range will be used by the Reset Vector on S3
949 // resume, it must be reserved as ACPI NVS.
951 BuildMemoryAllocationHob (
952 (EFI_PHYSICAL_ADDRESS
)(UINTN
)PcdGet32 (PcdOvmfSecGhcbPageTableBase
),
953 (UINT64
)(UINTN
)PcdGet32 (PcdOvmfSecGhcbPageTableSize
),
956 BuildMemoryAllocationHob (
957 (EFI_PHYSICAL_ADDRESS
)(UINTN
)PcdGet32 (PcdOvmfSecGhcbBase
),
958 (UINT64
)(UINTN
)PcdGet32 (PcdOvmfSecGhcbSize
),
961 BuildMemoryAllocationHob (
962 (EFI_PHYSICAL_ADDRESS
)(UINTN
)PcdGet32 (PcdOvmfSecGhcbBackupBase
),
963 (UINT64
)(UINTN
)PcdGet32 (PcdOvmfSecGhcbBackupSize
),
971 if (PlatformInfoHob
->BootMode
!= BOOT_ON_S3_RESUME
) {
972 if (!PlatformInfoHob
->SmmSmramRequire
) {
974 // Reserve the lock box storage area
976 // Since this memory range will be used on S3 resume, it must be
977 // reserved as ACPI NVS.
979 // If S3 is unsupported, then various drivers might still write to the
980 // LockBox area. We ought to prevent DXE from serving allocation requests
981 // such that they would overlap the LockBox storage.
984 (VOID
*)(UINTN
)PcdGet32 (PcdOvmfLockBoxStorageBase
),
985 (UINTN
)PcdGet32 (PcdOvmfLockBoxStorageSize
)
987 BuildMemoryAllocationHob (
988 (EFI_PHYSICAL_ADDRESS
)(UINTN
)PcdGet32 (PcdOvmfLockBoxStorageBase
),
989 (UINT64
)(UINTN
)PcdGet32 (PcdOvmfLockBoxStorageSize
),
990 PlatformInfoHob
->S3Supported
? EfiACPIMemoryNVS
: EfiBootServicesData
994 if (PlatformInfoHob
->SmmSmramRequire
) {
998 // Make sure the TSEG area that we reported as a reserved memory resource
999 // cannot be used for reserved memory allocations.
1001 TsegSize
= PlatformInfoHob
->Q35TsegMbytes
* SIZE_1MB
;
1002 BuildMemoryAllocationHob (
1003 PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob
) - TsegSize
,
1005 EfiReservedMemoryType
1008 // Similarly, allocate away the (already reserved) SMRAM at the default
1009 // SMBASE, if it exists.
1011 if (PlatformInfoHob
->Q35SmramAtDefaultSmbase
) {
1012 BuildMemoryAllocationHob (
1014 MCH_DEFAULT_SMBASE_SIZE
,
1015 EfiReservedMemoryType
1021 if (FixedPcdGet32 (PcdOvmfWorkAreaSize
) != 0) {
1023 // Reserve the work area.
1025 // Since this memory range will be used by the Reset Vector on S3
1026 // resume, it must be reserved as ACPI NVS.
1028 // If S3 is unsupported, then various drivers might still write to the
1029 // work area. We ought to prevent DXE from serving allocation requests
1030 // such that they would overlap the work area.
1032 BuildMemoryAllocationHob (
1033 (EFI_PHYSICAL_ADDRESS
)(UINTN
)FixedPcdGet32 (PcdOvmfWorkAreaBase
),
1034 (UINT64
)(UINTN
)FixedPcdGet32 (PcdOvmfWorkAreaSize
),
1035 PlatformInfoHob
->S3Supported
? EfiACPIMemoryNVS
: EfiBootServicesData