2 Memory Detection for Virtual Machines.
4 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
14 // The package level header files this module uses
16 #include <IndustryStandard/E820.h>
17 #include <IndustryStandard/I440FxPiix4.h>
18 #include <IndustryStandard/Q35MchIch9.h>
19 #include <IndustryStandard/CloudHv.h>
20 #include <IndustryStandard/Xen/arch-x86/hvm/start_info.h>
22 #include <Register/Intel/SmramSaveStateMap.h>
25 // The Library classes this module consumes
27 #include <Library/BaseLib.h>
28 #include <Library/BaseMemoryLib.h>
29 #include <Library/DebugLib.h>
30 #include <Library/HardwareInfoLib.h>
31 #include <Library/HobLib.h>
32 #include <Library/IoLib.h>
33 #include <Library/MemEncryptSevLib.h>
34 #include <Library/PcdLib.h>
35 #include <Library/PciLib.h>
36 #include <Library/PeimEntryPoint.h>
37 #include <Library/ResourcePublicationLib.h>
38 #include <Library/MtrrLib.h>
39 #include <Library/QemuFwCfgLib.h>
40 #include <Library/QemuFwCfgSimpleParserLib.h>
41 #include <Library/TdxLib.h>
43 #include <Library/PlatformInitLib.h>
47 PlatformQemuUc32BaseInitialization (
48 IN OUT EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
51 UINT32 LowerMemorySize
;
53 if (PlatformInfoHob
->HostBridgeDevId
== 0xffff /* microvm */) {
57 if (PlatformInfoHob
->HostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
58 LowerMemorySize
= PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob
);
59 ASSERT (PcdGet64 (PcdPciExpressBaseAddress
) <= MAX_UINT32
);
60 ASSERT (PcdGet64 (PcdPciExpressBaseAddress
) >= LowerMemorySize
);
62 if (LowerMemorySize
<= BASE_2GB
) {
63 // Newer qemu with gigabyte aligned memory,
64 // 32-bit pci mmio window is 2G -> 4G then.
65 PlatformInfoHob
->Uc32Base
= BASE_2GB
;
68 // On q35, the 32-bit area that we'll mark as UC, through variable MTRRs,
69 // starts at PcdPciExpressBaseAddress. The platform DSC is responsible for
70 // setting PcdPciExpressBaseAddress such that describing the
71 // [PcdPciExpressBaseAddress, 4GB) range require a very small number of
72 // variable MTRRs (preferably 1 or 2).
74 PlatformInfoHob
->Uc32Base
= (UINT32
)PcdGet64 (PcdPciExpressBaseAddress
);
80 if (PlatformInfoHob
->HostBridgeDevId
== CLOUDHV_DEVICE_ID
) {
81 PlatformInfoHob
->Uc32Size
= CLOUDHV_MMIO_HOLE_SIZE
;
82 PlatformInfoHob
->Uc32Base
= CLOUDHV_MMIO_HOLE_ADDRESS
;
86 ASSERT (PlatformInfoHob
->HostBridgeDevId
== INTEL_82441_DEVICE_ID
);
88 // On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one
89 // variable MTRR suffices by truncating the size to a whole power of two,
90 // while keeping the end affixed to 4GB. This will round the base up.
92 LowerMemorySize
= PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob
);
93 PlatformInfoHob
->Uc32Size
= GetPowerOfTwo32 ((UINT32
)(SIZE_4GB
- LowerMemorySize
));
94 PlatformInfoHob
->Uc32Base
= (UINT32
)(SIZE_4GB
- PlatformInfoHob
->Uc32Size
);
96 // Assuming that LowerMemorySize is at least 1 byte, Uc32Size is at most 2GB.
97 // Therefore Uc32Base is at least 2GB.
99 ASSERT (PlatformInfoHob
->Uc32Base
>= BASE_2GB
);
101 if (PlatformInfoHob
->Uc32Base
!= LowerMemorySize
) {
104 "%a: rounded UC32 base from 0x%x up to 0x%x, for "
105 "an UC32 size of 0x%x\n",
108 PlatformInfoHob
->Uc32Base
,
109 PlatformInfoHob
->Uc32Size
115 Iterate over the RAM entries in QEMU's fw_cfg E820 RAM map that start outside
116 of the 32-bit address range.
118 Find the highest exclusive >=4GB RAM address, or produce memory resource
119 descriptor HOBs for RAM entries that start at or above 4GB.
121 @param[out] MaxAddress If MaxAddress is NULL, then PlatformScanOrAdd64BitE820Ram()
122 produces memory resource descriptor HOBs for RAM
123 entries that start at or above 4GB.
125 Otherwise, MaxAddress holds the highest exclusive
126 >=4GB RAM address on output. If QEMU's fw_cfg E820
127 RAM map contains no RAM entry that starts outside of
128 the 32-bit address range, then MaxAddress is exactly
131 @retval EFI_SUCCESS The fw_cfg E820 RAM map was found and processed.
133 @retval EFI_PROTOCOL_ERROR The RAM map was found, but its size wasn't a
134 whole multiple of sizeof(EFI_E820_ENTRY64). No
135 RAM entry was processed.
137 @return Error codes from QemuFwCfgFindFile(). No RAM
142 PlatformScanOrAdd64BitE820Ram (
143 IN BOOLEAN AddHighHob
,
144 OUT UINT64
*LowMemory OPTIONAL
,
145 OUT UINT64
*MaxAddress OPTIONAL
149 FIRMWARE_CONFIG_ITEM FwCfgItem
;
151 EFI_E820_ENTRY64 E820Entry
;
154 Status
= QemuFwCfgFindFile ("etc/e820", &FwCfgItem
, &FwCfgSize
);
155 if (EFI_ERROR (Status
)) {
159 if (FwCfgSize
% sizeof E820Entry
!= 0) {
160 return EFI_PROTOCOL_ERROR
;
163 if (LowMemory
!= NULL
) {
167 if (MaxAddress
!= NULL
) {
168 *MaxAddress
= BASE_4GB
;
171 QemuFwCfgSelectItem (FwCfgItem
);
172 for (Processed
= 0; Processed
< FwCfgSize
; Processed
+= sizeof E820Entry
) {
173 QemuFwCfgReadBytes (sizeof E820Entry
, &E820Entry
);
176 "%a: Base=0x%Lx Length=0x%Lx Type=%u\n",
182 if (E820Entry
.Type
== EfiAcpiAddressRangeMemory
) {
183 if (AddHighHob
&& (E820Entry
.BaseAddr
>= BASE_4GB
)) {
188 // Round up the start address, and round down the end address.
190 Base
= ALIGN_VALUE (E820Entry
.BaseAddr
, (UINT64
)EFI_PAGE_SIZE
);
191 End
= (E820Entry
.BaseAddr
+ E820Entry
.Length
) &
192 ~(UINT64
)EFI_PAGE_MASK
;
194 PlatformAddMemoryRangeHob (Base
, End
);
197 "%a: PlatformAddMemoryRangeHob [0x%Lx, 0x%Lx)\n",
205 if (MaxAddress
|| LowMemory
) {
208 Candidate
= E820Entry
.BaseAddr
+ E820Entry
.Length
;
209 if (MaxAddress
&& (Candidate
> *MaxAddress
)) {
210 *MaxAddress
= Candidate
;
213 "%a: MaxAddress=0x%Lx\n",
219 if (LowMemory
&& (Candidate
> *LowMemory
) && (Candidate
< BASE_4GB
)) {
220 *LowMemory
= Candidate
;
223 "%a: LowMemory=0x%Lx\n",
238 @param Entries Pointer to PVH memmap
239 @param Count Number of entries
244 GetPvhMemmapEntries (
245 struct hvm_memmap_table_entry
**Entries
,
249 UINT32
*PVHResetVectorData
;
250 struct hvm_start_info
*pvh_start_info
;
252 PVHResetVectorData
= (VOID
*)(UINTN
)PcdGet32 (PcdXenPvhStartOfDayStructPtr
);
253 if (PVHResetVectorData
== 0) {
254 return EFI_NOT_FOUND
;
257 pvh_start_info
= (struct hvm_start_info
*)(UINTN
)PVHResetVectorData
[0];
259 *Entries
= (struct hvm_memmap_table_entry
*)(UINTN
)pvh_start_info
->memmap_paddr
;
260 *Count
= pvh_start_info
->memmap_entries
;
267 GetHighestSystemMemoryAddressFromPvhMemmap (
271 struct hvm_memmap_table_entry
*Memmap
;
272 UINT32 MemmapEntriesCount
;
273 struct hvm_memmap_table_entry
*Entry
;
276 UINT64 HighestAddress
;
281 Status
= GetPvhMemmapEntries (&Memmap
, &MemmapEntriesCount
);
282 ASSERT_EFI_ERROR (Status
);
284 for (Loop
= 0; Loop
< MemmapEntriesCount
; Loop
++) {
285 Entry
= Memmap
+ Loop
;
286 EntryEnd
= Entry
->addr
+ Entry
->size
;
288 if ((Entry
->type
== XEN_HVM_MEMMAP_TYPE_RAM
) &&
289 (EntryEnd
> HighestAddress
))
291 if (Below4gb
&& (EntryEnd
<= BASE_4GB
)) {
292 HighestAddress
= EntryEnd
;
293 } else if (!Below4gb
&& (EntryEnd
>= BASE_4GB
)) {
294 HighestAddress
= EntryEnd
;
299 return HighestAddress
;
304 PlatformGetSystemMemorySizeBelow4gb (
305 IN EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
309 UINT64 LowerMemorySize
= 0;
313 if (PlatformInfoHob
->HostBridgeDevId
== CLOUDHV_DEVICE_ID
) {
314 // Get the information from PVH memmap
315 return (UINT32
)GetHighestSystemMemoryAddressFromPvhMemmap (TRUE
);
318 Status
= PlatformScanOrAdd64BitE820Ram (FALSE
, &LowerMemorySize
, NULL
);
319 if ((Status
== EFI_SUCCESS
) && (LowerMemorySize
> 0)) {
320 return (UINT32
)LowerMemorySize
;
324 // CMOS 0x34/0x35 specifies the system memory above 16 MB.
325 // * CMOS(0x35) is the high byte
326 // * CMOS(0x34) is the low byte
327 // * The size is specified in 64kb chunks
328 // * Since this is memory above 16MB, the 16MB must be added
329 // into the calculation to get the total memory size.
332 Cmos0x34
= (UINT8
)PlatformCmosRead8 (0x34);
333 Cmos0x35
= (UINT8
)PlatformCmosRead8 (0x35);
335 return (UINT32
)(((UINTN
)((Cmos0x35
<< 8) + Cmos0x34
) << 16) + SIZE_16MB
);
340 PlatformGetSystemMemorySizeAbove4gb (
347 // CMOS 0x5b-0x5d specifies the system memory above 4GB MB.
348 // * CMOS(0x5d) is the most significant size byte
349 // * CMOS(0x5c) is the middle size byte
350 // * CMOS(0x5b) is the least significant size byte
351 // * The size is specified in 64kb chunks
355 for (CmosIndex
= 0x5d; CmosIndex
>= 0x5b; CmosIndex
--) {
356 Size
= (UINT32
)(Size
<< 8) + (UINT32
)PlatformCmosRead8 (CmosIndex
);
359 return LShiftU64 (Size
, 16);
363 Return the highest address that DXE could possibly use, plus one.
367 PlatformGetFirstNonAddress (
368 IN OUT EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
371 UINT64 FirstNonAddress
;
372 UINT32 FwCfgPciMmio64Mb
;
374 FIRMWARE_CONFIG_ITEM FwCfgItem
;
376 UINT64 HotPlugMemoryEnd
;
379 // set FirstNonAddress to suppress incorrect compiler/analyzer warnings
384 // If QEMU presents an E820 map, then get the highest exclusive >=4GB RAM
385 // address from it. This can express an address >= 4GB+1TB.
387 // Otherwise, get the flat size of the memory above 4GB from the CMOS (which
388 // can only express a size smaller than 1TB), and add it to 4GB.
390 Status
= PlatformScanOrAdd64BitE820Ram (FALSE
, NULL
, &FirstNonAddress
);
391 if (EFI_ERROR (Status
)) {
392 FirstNonAddress
= BASE_4GB
+ PlatformGetSystemMemorySizeAbove4gb ();
396 // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO
397 // resources to 32-bit anyway. See DegradeResource() in
398 // "PciResourceSupport.c".
401 if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode
)) {
402 return FirstNonAddress
;
408 // See if the user specified the number of megabytes for the 64-bit PCI host
409 // aperture. Accept an aperture size up to 16TB.
411 // As signaled by the "X-" prefix, this knob is experimental, and might go
414 Status
= QemuFwCfgParseUint32 (
415 "opt/ovmf/X-PciMmio64Mb",
420 case EFI_UNSUPPORTED
:
424 if (FwCfgPciMmio64Mb
<= 0x1000000) {
425 PlatformInfoHob
->PcdPciMmio64Size
= LShiftU64 (FwCfgPciMmio64Mb
, 20);
435 "%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\n",
441 if (PlatformInfoHob
->PcdPciMmio64Size
== 0) {
442 if (PlatformInfoHob
->BootMode
!= BOOT_ON_S3_RESUME
) {
445 "%a: disabling 64-bit PCI host aperture\n",
451 // There's nothing more to do; the amount of memory above 4GB fully
452 // determines the highest address plus one. The memory hotplug area (see
453 // below) plays no role for the firmware in this case.
455 return FirstNonAddress
;
459 // The "etc/reserved-memory-end" fw_cfg file, when present, contains an
460 // absolute, exclusive end address for the memory hotplug area. This area
461 // starts right at the end of the memory above 4GB. The 64-bit PCI host
462 // aperture must be placed above it.
464 Status
= QemuFwCfgFindFile (
465 "etc/reserved-memory-end",
469 if (!EFI_ERROR (Status
) && (FwCfgSize
== sizeof HotPlugMemoryEnd
)) {
470 QemuFwCfgSelectItem (FwCfgItem
);
471 QemuFwCfgReadBytes (FwCfgSize
, &HotPlugMemoryEnd
);
474 "%a: HotPlugMemoryEnd=0x%Lx\n",
479 ASSERT (HotPlugMemoryEnd
>= FirstNonAddress
);
480 FirstNonAddress
= HotPlugMemoryEnd
;
484 // SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB, so
485 // that the host can map it with 1GB hugepages. Follow suit.
487 PlatformInfoHob
->PcdPciMmio64Base
= ALIGN_VALUE (FirstNonAddress
, (UINT64
)SIZE_1GB
);
488 PlatformInfoHob
->PcdPciMmio64Size
= ALIGN_VALUE (PlatformInfoHob
->PcdPciMmio64Size
, (UINT64
)SIZE_1GB
);
491 // The 64-bit PCI host aperture should also be "naturally" aligned. The
492 // alignment is determined by rounding the size of the aperture down to the
493 // next smaller or equal power of two. That is, align the aperture by the
494 // largest BAR size that can fit into it.
496 PlatformInfoHob
->PcdPciMmio64Base
= ALIGN_VALUE (PlatformInfoHob
->PcdPciMmio64Base
, GetPowerOfTwo64 (PlatformInfoHob
->PcdPciMmio64Size
));
499 // The useful address space ends with the 64-bit PCI host aperture.
501 FirstNonAddress
= PlatformInfoHob
->PcdPciMmio64Base
+ PlatformInfoHob
->PcdPciMmio64Size
;
502 return FirstNonAddress
;
506 * Use CPUID to figure physical address width.
508 * Does *not* work reliable on qemu. For historical reasons qemu
509 * returns phys-bits=40 by default even in case the host machine
510 * supports less than that.
512 * So we apply the following rules (which can be enabled/disabled
513 * using the QemuQuirk parameter) to figure whenever we can work with
514 * the returned physical address width or not:
516 * (1) If it is 41 or higher consider it valid.
517 * (2) If it is 40 or lower consider it valid in case it matches a
518 * known-good value for the CPU vendor, which is:
519 * -> 36 or 39 for Intel
521 * (3) Otherwise consider it invalid.
523 * Recommendation: Run qemu with host-phys-bits=on. That will make
524 * sure guest phys-bits is not larger than host phys-bits. Some
525 * distro builds do that by default.
529 PlatformAddressWidthFromCpuid (
530 IN OUT EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
,
534 UINT32 RegEax
, RegEbx
, RegEcx
, RegEdx
, Max
;
536 CHAR8 Signature
[13] = { 0 };
537 BOOLEAN Valid
= FALSE
;
538 BOOLEAN Page1GSupport
= FALSE
;
540 AsmCpuid (0x80000000, &RegEax
, &RegEbx
, &RegEcx
, &RegEdx
);
541 *(UINT32
*)(Signature
+ 0) = RegEbx
;
542 *(UINT32
*)(Signature
+ 4) = RegEdx
;
543 *(UINT32
*)(Signature
+ 8) = RegEcx
;
546 if (Max
>= 0x80000001) {
547 AsmCpuid (0x80000001, NULL
, NULL
, NULL
, &RegEdx
);
548 if ((RegEdx
& BIT26
) != 0) {
549 Page1GSupport
= TRUE
;
553 if (Max
>= 0x80000008) {
554 AsmCpuid (0x80000008, &RegEax
, NULL
, NULL
, NULL
);
555 PhysBits
= (UINT8
)RegEax
;
562 } else if (PhysBits
>= 41) {
564 } else if (AsciiStrCmp (Signature
, "GenuineIntel") == 0) {
565 if ((PhysBits
== 36) || (PhysBits
== 39)) {
568 } else if (AsciiStrCmp (Signature
, "AuthenticAMD") == 0) {
569 if (PhysBits
== 40) {
576 "%a: Signature: '%a', PhysBits: %d, QemuQuirk: %a, Valid: %a\n",
580 QemuQuirk
? "On" : "Off",
587 * Avoid 5-level paging altogether for now, which limits
588 * PhysBits to 48. Also avoid using address bit 48, due to sign
589 * extension we can't identity-map these addresses (and lots of
590 * places in edk2 assume we have everything identity-mapped).
591 * So the actual limit is 47.
593 DEBUG ((DEBUG_INFO
, "%a: limit PhysBits to 47 (avoid 5-level paging)\n", __func__
));
597 if (!Page1GSupport
&& (PhysBits
> 40)) {
598 DEBUG ((DEBUG_INFO
, "%a: limit PhysBits to 40 (no 1G pages available)\n", __func__
));
602 PlatformInfoHob
->PhysMemAddressWidth
= PhysBits
;
603 PlatformInfoHob
->FirstNonAddress
= LShiftU64 (1, PlatformInfoHob
->PhysMemAddressWidth
);
609 PlatformDynamicMmioWindow (
610 IN OUT EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
613 UINT64 AddrSpace
, MmioSpace
;
615 AddrSpace
= LShiftU64 (1, PlatformInfoHob
->PhysMemAddressWidth
);
616 MmioSpace
= LShiftU64 (1, PlatformInfoHob
->PhysMemAddressWidth
- 3);
618 if ((PlatformInfoHob
->PcdPciMmio64Size
< MmioSpace
) &&
619 (PlatformInfoHob
->PcdPciMmio64Base
+ MmioSpace
< AddrSpace
))
621 DEBUG ((DEBUG_INFO
, "%a: using dynamic mmio window\n", __func__
));
622 DEBUG ((DEBUG_INFO
, "%a: Addr Space 0x%Lx (%Ld GB)\n", __func__
, AddrSpace
, RShiftU64 (AddrSpace
, 30)));
623 DEBUG ((DEBUG_INFO
, "%a: MMIO Space 0x%Lx (%Ld GB)\n", __func__
, MmioSpace
, RShiftU64 (MmioSpace
, 30)));
624 PlatformInfoHob
->PcdPciMmio64Size
= MmioSpace
;
625 PlatformInfoHob
->PcdPciMmio64Base
= AddrSpace
- MmioSpace
;
627 DEBUG ((DEBUG_INFO
, "%a: using classic mmio window\n", __func__
));
630 DEBUG ((DEBUG_INFO
, "%a: Pci64 Base 0x%Lx\n", __func__
, PlatformInfoHob
->PcdPciMmio64Base
));
631 DEBUG ((DEBUG_INFO
, "%a: Pci64 Size 0x%Lx\n", __func__
, PlatformInfoHob
->PcdPciMmio64Size
));
635 Iterate over the PCI host bridges resources information optionally provided
636 in fw-cfg and find the highest address contained in the PCI MMIO windows. If
637 the information is found, return the exclusive end; one past the last usable
640 @param[out] PciMmioAddressEnd Pointer to one-after End Address updated with
641 information extracted from host-provided data
642 or zero if no information available or an
645 @retval EFI_SUCCESS PCI information was read and the output
646 parameter updated with the last valid
647 address in the 64-bit MMIO range.
648 @retval EFI_INVALID_PARAMETER Pointer parameter is invalid
649 @retval EFI_INCOMPATIBLE_VERSION Hardware information found in fw-cfg
650 has an incompatible format
651 @retval EFI_UNSUPPORTED Fw-cfg is not supported, thus host
652 provided information, if any, cannot be
654 @retval EFI_NOT_FOUND No PCI host bridge information provided
659 PlatformScanHostProvided64BitPciMmioEnd (
660 OUT UINT64
*PciMmioAddressEnd
664 HOST_BRIDGE_INFO HostBridge
;
665 FIRMWARE_CONFIG_ITEM FwCfgItem
;
667 UINTN FwCfgReadIndex
;
669 UINT64 Above4GMmioEnd
;
671 if (PciMmioAddressEnd
== NULL
) {
672 return EFI_INVALID_PARAMETER
;
675 *PciMmioAddressEnd
= 0;
678 Status
= QemuFwCfgFindFile ("etc/hardware-info", &FwCfgItem
, &FwCfgSize
);
679 if (EFI_ERROR (Status
)) {
683 QemuFwCfgSelectItem (FwCfgItem
);
686 while (FwCfgReadIndex
< FwCfgSize
) {
687 Status
= QemuFwCfgReadNextHardwareInfoByType (
688 HardwareInfoTypeHostBridge
,
696 if (Status
!= EFI_SUCCESS
) {
698 // No more data available to read in the file, break
699 // loop and finish process
704 Status
= HardwareInfoPciHostBridgeLastMmioAddress (
711 if (Status
!= EFI_SUCCESS
) {
713 // Error parsing MMIO apertures and extracting last MMIO
714 // address, reset PciMmioAddressEnd as if no information was
715 // found, to avoid moving forward with incomplete data, and
720 "%a: ignoring malformed hardware information from fw_cfg\n",
723 *PciMmioAddressEnd
= 0;
727 if (Above4GMmioEnd
> *PciMmioAddressEnd
) {
728 *PciMmioAddressEnd
= Above4GMmioEnd
;
732 if (*PciMmioAddressEnd
> 0) {
734 // Host-provided PCI information was found and a MMIO window end
736 // Increase the End address by one to have the output pointing to
737 // one after the address in use (exclusive end).
739 *PciMmioAddressEnd
+= 1;
743 "%a: Pci64End=0x%Lx\n",
751 return EFI_NOT_FOUND
;
755 Initialize the PhysMemAddressWidth field in PlatformInfoHob based on guest RAM size.
759 PlatformAddressWidthInitialization (
760 IN OUT EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
763 UINT64 FirstNonAddress
;
764 UINT8 PhysMemAddressWidth
;
767 if (PlatformInfoHob
->HostBridgeDevId
== 0xffff /* microvm */) {
768 PlatformAddressWidthFromCpuid (PlatformInfoHob
, FALSE
);
773 // First scan host-provided hardware information to assess if the address
774 // space is already known. If so, guest must use those values.
776 Status
= PlatformScanHostProvided64BitPciMmioEnd (&FirstNonAddress
);
778 if (EFI_ERROR (Status
)) {
780 // If the host did not provide valid hardware information leading to a
781 // hard-defined 64-bit MMIO end, fold back to calculating the minimum range
783 // As guest-physical memory size grows, the permanent PEI RAM requirements
784 // are dominated by the identity-mapping page tables built by the DXE IPL.
785 // The DXL IPL keys off of the physical address bits advertized in the CPU
786 // HOB. To conserve memory, we calculate the minimum address width here.
788 FirstNonAddress
= PlatformGetFirstNonAddress (PlatformInfoHob
);
791 PlatformAddressWidthFromCpuid (PlatformInfoHob
, TRUE
);
792 if (PlatformInfoHob
->PhysMemAddressWidth
!= 0) {
793 // physical address width is known
794 PlatformInfoHob
->FirstNonAddress
= FirstNonAddress
;
795 PlatformDynamicMmioWindow (PlatformInfoHob
);
800 // physical address width is NOT known
801 // -> do some guess work, mostly based on installed memory
802 // -> try be conservstibe to stay below the guaranteed minimum of
803 // 36 phys bits (aka 64 GB).
805 PhysMemAddressWidth
= (UINT8
)HighBitSet64 (FirstNonAddress
);
808 // If FirstNonAddress is not an integral power of two, then we need an
811 if ((FirstNonAddress
& (FirstNonAddress
- 1)) != 0) {
812 ++PhysMemAddressWidth
;
816 // The minimum address width is 36 (covers up to and excluding 64 GB, which
817 // is the maximum for Ia32 + PAE). The theoretical architecture maximum for
818 // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We
819 // can simply assert that here, since 48 bits are good enough for 256 TB.
821 if (PhysMemAddressWidth
<= 36) {
822 PhysMemAddressWidth
= 36;
825 #if defined (MDE_CPU_X64)
826 if (TdIsEnabled ()) {
827 if (TdSharedPageMask () == (1ULL << 47)) {
828 PhysMemAddressWidth
= 48;
830 PhysMemAddressWidth
= 52;
834 ASSERT (PhysMemAddressWidth
<= 52);
836 ASSERT (PhysMemAddressWidth
<= 48);
839 PlatformInfoHob
->FirstNonAddress
= FirstNonAddress
;
840 PlatformInfoHob
->PhysMemAddressWidth
= PhysMemAddressWidth
;
845 QemuInitializeRamBelow1gb (
846 IN EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
849 if (PlatformInfoHob
->SmmSmramRequire
&& PlatformInfoHob
->Q35SmramAtDefaultSmbase
) {
850 PlatformAddMemoryRangeHob (0, SMM_DEFAULT_SMBASE
);
851 PlatformAddReservedMemoryBaseSizeHob (
853 MCH_DEFAULT_SMBASE_SIZE
,
857 SMM_DEFAULT_SMBASE
+ MCH_DEFAULT_SMBASE_SIZE
< BASE_512KB
+ BASE_128KB
,
858 "end of SMRAM at default SMBASE ends at, or exceeds, 640KB"
860 PlatformAddMemoryRangeHob (
861 SMM_DEFAULT_SMBASE
+ MCH_DEFAULT_SMBASE_SIZE
,
862 BASE_512KB
+ BASE_128KB
865 PlatformAddMemoryRangeHob (0, BASE_512KB
+ BASE_128KB
);
870 Peform Memory Detection for QEMU / KVM
875 PlatformQemuInitializeRam (
876 IN EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
879 UINT64 LowerMemorySize
;
880 UINT64 UpperMemorySize
;
881 MTRR_SETTINGS MtrrSettings
;
884 DEBUG ((DEBUG_INFO
, "%a called\n", __FUNCTION__
));
887 // Determine total memory size available
889 LowerMemorySize
= PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob
);
891 if (PlatformInfoHob
->BootMode
== BOOT_ON_S3_RESUME
) {
893 // Create the following memory HOB as an exception on the S3 boot path.
895 // Normally we'd create memory HOBs only on the normal boot path. However,
896 // CpuMpPei specifically needs such a low-memory HOB on the S3 path as
897 // well, for "borrowing" a subset of it temporarily, for the AP startup
900 // CpuMpPei saves the original contents of the borrowed area in permanent
901 // PEI RAM, in a backup buffer allocated with the normal PEI services.
902 // CpuMpPei restores the original contents ("returns" the borrowed area) at
903 // End-of-PEI. End-of-PEI in turn is emitted by S3Resume2Pei before
904 // transferring control to the OS's wakeup vector in the FACS.
906 // We expect any other PEIMs that "borrow" memory similarly to CpuMpPei to
907 // restore the original contents. Furthermore, we expect all such PEIMs
908 // (CpuMpPei included) to claim the borrowed areas by producing memory
909 // allocation HOBs, and to honor preexistent memory allocation HOBs when
910 // looking for an area to borrow.
912 QemuInitializeRamBelow1gb (PlatformInfoHob
);
915 // Create memory HOBs
917 QemuInitializeRamBelow1gb (PlatformInfoHob
);
919 if (PlatformInfoHob
->SmmSmramRequire
) {
922 TsegSize
= PlatformInfoHob
->Q35TsegMbytes
* SIZE_1MB
;
923 PlatformAddMemoryRangeHob (BASE_1MB
, LowerMemorySize
- TsegSize
);
924 PlatformAddReservedMemoryBaseSizeHob (
925 LowerMemorySize
- TsegSize
,
930 PlatformAddMemoryRangeHob (BASE_1MB
, LowerMemorySize
);
934 // If QEMU presents an E820 map, then create memory HOBs for the >=4GB RAM
935 // entries. Otherwise, create a single memory HOB with the flat >=4GB
936 // memory size read from the CMOS.
938 Status
= PlatformScanOrAdd64BitE820Ram (TRUE
, NULL
, NULL
);
939 if (EFI_ERROR (Status
)) {
940 UpperMemorySize
= PlatformGetSystemMemorySizeAbove4gb ();
941 if (UpperMemorySize
!= 0) {
942 PlatformAddMemoryBaseSizeHob (BASE_4GB
, UpperMemorySize
);
948 // We'd like to keep the following ranges uncached:
950 // - [LowerMemorySize, 4 GB)
952 // Everything else should be WB. Unfortunately, programming the inverse (ie.
953 // keeping the default UC, and configuring the complement set of the above as
954 // WB) is not reliable in general, because the end of the upper RAM can have
955 // practically any alignment, and we may not have enough variable MTRRs to
958 if (IsMtrrSupported () && (PlatformInfoHob
->HostBridgeDevId
!= CLOUDHV_DEVICE_ID
)) {
959 MtrrGetAllMtrrs (&MtrrSettings
);
962 // MTRRs disabled, fixed MTRRs disabled, default type is uncached
964 ASSERT ((MtrrSettings
.MtrrDefType
& BIT11
) == 0);
965 ASSERT ((MtrrSettings
.MtrrDefType
& BIT10
) == 0);
966 ASSERT ((MtrrSettings
.MtrrDefType
& 0xFF) == 0);
969 // flip default type to writeback
971 SetMem (&MtrrSettings
.Fixed
, sizeof MtrrSettings
.Fixed
, 0x06);
972 ZeroMem (&MtrrSettings
.Variables
, sizeof MtrrSettings
.Variables
);
973 MtrrSettings
.MtrrDefType
|= BIT11
| BIT10
| 6;
974 MtrrSetAllMtrrs (&MtrrSettings
);
977 // Set memory range from 640KB to 1MB to uncacheable
979 Status
= MtrrSetMemoryAttribute (
980 BASE_512KB
+ BASE_128KB
,
981 BASE_1MB
- (BASE_512KB
+ BASE_128KB
),
984 ASSERT_EFI_ERROR (Status
);
987 // Set the memory range from the start of the 32-bit MMIO area (32-bit PCI
988 // MMIO aperture on i440fx, PCIEXBAR on q35) to 4GB as uncacheable.
990 Status
= MtrrSetMemoryAttribute (
991 PlatformInfoHob
->Uc32Base
,
992 SIZE_4GB
- PlatformInfoHob
->Uc32Base
,
995 ASSERT_EFI_ERROR (Status
);
1001 PlatformQemuInitializeRamForS3 (
1002 IN EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
1005 if (PlatformInfoHob
->S3Supported
&& (PlatformInfoHob
->BootMode
!= BOOT_ON_S3_RESUME
)) {
1007 // This is the memory range that will be used for PEI on S3 resume
1009 BuildMemoryAllocationHob (
1010 PlatformInfoHob
->S3AcpiReservedMemoryBase
,
1011 PlatformInfoHob
->S3AcpiReservedMemorySize
,
1016 // Cover the initial RAM area used as stack and temporary PEI heap.
1018 // This is reserved as ACPI NVS so it can be used on S3 resume.
1020 BuildMemoryAllocationHob (
1021 PcdGet32 (PcdOvmfSecPeiTempRamBase
),
1022 PcdGet32 (PcdOvmfSecPeiTempRamSize
),
1027 // SEC stores its table of GUIDed section handlers here.
1029 BuildMemoryAllocationHob (
1030 PcdGet64 (PcdGuidedExtractHandlerTableAddress
),
1031 PcdGet32 (PcdGuidedExtractHandlerTableSize
),
1037 // Reserve the initial page tables built by the reset vector code.
1039 // Since this memory range will be used by the Reset Vector on S3
1040 // resume, it must be reserved as ACPI NVS.
1042 BuildMemoryAllocationHob (
1043 (EFI_PHYSICAL_ADDRESS
)(UINTN
)PcdGet32 (PcdOvmfSecPageTablesBase
),
1044 (UINT64
)(UINTN
)PcdGet32 (PcdOvmfSecPageTablesSize
),
1048 if (PlatformInfoHob
->SevEsIsEnabled
) {
1050 // If SEV-ES is enabled, reserve the GHCB-related memory area. This
1051 // includes the extra page table used to break down the 2MB page
1052 // mapping into 4KB page entries where the GHCB resides and the
1053 // GHCB area itself.
1055 // Since this memory range will be used by the Reset Vector on S3
1056 // resume, it must be reserved as ACPI NVS.
1058 BuildMemoryAllocationHob (
1059 (EFI_PHYSICAL_ADDRESS
)(UINTN
)PcdGet32 (PcdOvmfSecGhcbPageTableBase
),
1060 (UINT64
)(UINTN
)PcdGet32 (PcdOvmfSecGhcbPageTableSize
),
1063 BuildMemoryAllocationHob (
1064 (EFI_PHYSICAL_ADDRESS
)(UINTN
)PcdGet32 (PcdOvmfSecGhcbBase
),
1065 (UINT64
)(UINTN
)PcdGet32 (PcdOvmfSecGhcbSize
),
1068 BuildMemoryAllocationHob (
1069 (EFI_PHYSICAL_ADDRESS
)(UINTN
)PcdGet32 (PcdOvmfSecGhcbBackupBase
),
1070 (UINT64
)(UINTN
)PcdGet32 (PcdOvmfSecGhcbBackupSize
),
1078 if (PlatformInfoHob
->BootMode
!= BOOT_ON_S3_RESUME
) {
1079 if (!PlatformInfoHob
->SmmSmramRequire
) {
1081 // Reserve the lock box storage area
1083 // Since this memory range will be used on S3 resume, it must be
1084 // reserved as ACPI NVS.
1086 // If S3 is unsupported, then various drivers might still write to the
1087 // LockBox area. We ought to prevent DXE from serving allocation requests
1088 // such that they would overlap the LockBox storage.
1091 (VOID
*)(UINTN
)PcdGet32 (PcdOvmfLockBoxStorageBase
),
1092 (UINTN
)PcdGet32 (PcdOvmfLockBoxStorageSize
)
1094 BuildMemoryAllocationHob (
1095 (EFI_PHYSICAL_ADDRESS
)(UINTN
)PcdGet32 (PcdOvmfLockBoxStorageBase
),
1096 (UINT64
)(UINTN
)PcdGet32 (PcdOvmfLockBoxStorageSize
),
1097 PlatformInfoHob
->S3Supported
? EfiACPIMemoryNVS
: EfiBootServicesData
1101 if (PlatformInfoHob
->SmmSmramRequire
) {
1105 // Make sure the TSEG area that we reported as a reserved memory resource
1106 // cannot be used for reserved memory allocations.
1108 TsegSize
= PlatformInfoHob
->Q35TsegMbytes
* SIZE_1MB
;
1109 BuildMemoryAllocationHob (
1110 PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob
) - TsegSize
,
1112 EfiReservedMemoryType
1115 // Similarly, allocate away the (already reserved) SMRAM at the default
1116 // SMBASE, if it exists.
1118 if (PlatformInfoHob
->Q35SmramAtDefaultSmbase
) {
1119 BuildMemoryAllocationHob (
1121 MCH_DEFAULT_SMBASE_SIZE
,
1122 EfiReservedMemoryType
1128 if (FixedPcdGet32 (PcdOvmfWorkAreaSize
) != 0) {
1130 // Reserve the work area.
1132 // Since this memory range will be used by the Reset Vector on S3
1133 // resume, it must be reserved as ACPI NVS.
1135 // If S3 is unsupported, then various drivers might still write to the
1136 // work area. We ought to prevent DXE from serving allocation requests
1137 // such that they would overlap the work area.
1139 BuildMemoryAllocationHob (
1140 (EFI_PHYSICAL_ADDRESS
)(UINTN
)FixedPcdGet32 (PcdOvmfWorkAreaBase
),
1141 (UINT64
)(UINTN
)FixedPcdGet32 (PcdOvmfWorkAreaSize
),
1142 PlatformInfoHob
->S3Supported
? EfiACPIMemoryNVS
: EfiBootServicesData