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1 ## @file
2 # EFI/Framework Open Virtual Machine Firmware (OVMF) platform
3 #
4 # Copyright (c) 2020, Rebecca Cran <rebecca@bsdio.com>
5 # Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
6 # Copyright (c) 2014, Pluribus Networks, Inc.
7 #
8 # SPDX-License-Identifier: BSD-2-Clause-Patent
9 #
10 ##
11
12 [Defines]
13 DEC_SPECIFICATION = 0x00010005
14 PACKAGE_NAME = OvmfPkg
15 PACKAGE_GUID = 2daf5f34-50e5-4b9d-b8e3-5562334d87e5
16 PACKAGE_VERSION = 0.1
17
18 [Includes]
19 Include
20 Csm/Include
21
22 [LibraryClasses]
23 ## @libraryclass Access bhyve's firmware control interface.
24 BhyveFwCtlLib|Include/Library/BhyveFwCtlLib.h
25
26 ## @libraryclass Verify blobs read from the VMM
27 BlobVerifierLib|Include/Library/BlobVerifierLib.h
28
29 ## @libraryclass Loads and boots a Linux kernel image
30 #
31 LoadLinuxLib|Include/Library/LoadLinuxLib.h
32
33 ## @libraryclass Declares helper functions for Secure Encrypted
34 # Virtualization (SEV) guests.
35 MemEncryptSevLib|Include/Library/MemEncryptSevLib.h
36
37 ## @libraryclass Declares helper functions for TDX guests.
38 #
39 MemEncryptTdxLib|Include/Library/MemEncryptTdxLib.h
40
41 ## @libraryclass Save and restore variables using a file
42 #
43 NvVarsFileLib|Include/Library/NvVarsFileLib.h
44
45 ## @libraryclass Provides services to work with PCI capabilities in PCI
46 # config space.
47 PciCapLib|Include/Library/PciCapLib.h
48
49 ## @libraryclass Layered on top of PciCapLib, allows clients to plug an
50 # EFI_PCI_IO_PROTOCOL backend into PciCapLib, for config
51 # space access.
52 PciCapPciIoLib|Include/Library/PciCapPciIoLib.h
53
54 ## @libraryclass Layered on top of PciCapLib, allows clients to plug a
55 # PciSegmentLib backend into PciCapLib, for config space
56 # access.
57 PciCapPciSegmentLib|Include/Library/PciCapPciSegmentLib.h
58
59 ## @libraryclass Provide common utility functions to PciHostBridgeLib
60 # instances in ArmVirtPkg and OvmfPkg.
61 PciHostBridgeUtilityLib|Include/Library/PciHostBridgeUtilityLib.h
62
63 ## @libraryclass Register a status code handler for printing the Boot
64 # Manager's LoadImage() and StartImage() preparations, and
65 # return codes, to the UEFI console.
66 PlatformBmPrintScLib|Include/Library/PlatformBmPrintScLib.h
67
68 ## @libraryclass Customize FVB2 protocol member functions for a platform.
69 PlatformFvbLib|Include/Library/PlatformFvbLib.h
70
71 ## @libraryclass Access QEMU's firmware configuration interface
72 #
73 QemuFwCfgLib|Include/Library/QemuFwCfgLib.h
74
75 ## @libraryclass S3 support for QEMU fw_cfg
76 #
77 QemuFwCfgS3Lib|Include/Library/QemuFwCfgS3Lib.h
78
79 ## @libraryclass Parse the contents of named fw_cfg files as simple
80 # (scalar) data types.
81 QemuFwCfgSimpleParserLib|Include/Library/QemuFwCfgSimpleParserLib.h
82
83 ## @libraryclass Rewrite the BootOrder NvVar based on QEMU's "bootorder"
84 # fw_cfg file.
85 #
86 QemuBootOrderLib|Include/Library/QemuBootOrderLib.h
87
88 ## @libraryclass Load a kernel image and command line passed to QEMU via
89 # the command line
90 #
91 QemuLoadImageLib|Include/Library/QemuLoadImageLib.h
92
93 ## @libraryclass Serialize (and deserialize) variables
94 #
95 SerializeVariablesLib|Include/Library/SerializeVariablesLib.h
96
97 ## @libraryclass Declares utility functions for virtio device drivers.
98 VirtioLib|Include/Library/VirtioLib.h
99
100 ## @libraryclass Install Virtio Device Protocol instances on virtio-mmio
101 # transports.
102 VirtioMmioDeviceLib|Include/Library/VirtioMmioDeviceLib.h
103
104 ## @libraryclass Invoke Xen hypercalls
105 #
106 XenHypercallLib|Include/Library/XenHypercallLib.h
107
108 ## @libraryclass Manage XenBus device path and I/O handles
109 #
110 XenIoMmioLib|Include/Library/XenIoMmioLib.h
111
112 ## @libraryclass Get information about Xen
113 #
114 XenPlatformLib|Include/Library/XenPlatformLib.h
115
116 ## @libraryclass TdxMailboxLib
117 #
118 TdxMailboxLib|Include/Library/TdxMailboxLib.h
119
120 ## @libraryclass PlatformInitLib
121 #
122 PlatformInitLib|Include/Library/PlatformInitLib.h
123
124 ## @libraryclass PeilessStartupLib
125 #
126 PeilessStartupLib|Include/Library/PeilessStartupLib.h
127
128 ## @libraryclass HardwareInfoLib
129 #
130 HardwareInfoLib|Include/Library/HardwareInfoLib.h
131
132 [Guids]
133 gUefiOvmfPkgTokenSpaceGuid = {0x93bb96af, 0xb9f2, 0x4eb8, {0x94, 0x62, 0xe0, 0xba, 0x74, 0x56, 0x42, 0x36}}
134 gEfiXenInfoGuid = {0xd3b46f3b, 0xd441, 0x1244, {0x9a, 0x12, 0x0, 0x12, 0x27, 0x3f, 0xc1, 0x4d}}
135 gOvmfPkKek1AppPrefixGuid = {0x4e32566d, 0x8e9e, 0x4f52, {0x81, 0xd3, 0x5b, 0xb9, 0x71, 0x5f, 0x97, 0x27}}
136 gOvmfPlatformConfigGuid = {0x7235c51c, 0x0c80, 0x4cab, {0x87, 0xac, 0x3b, 0x08, 0x4a, 0x63, 0x04, 0xb1}}
137 gVirtioMmioTransportGuid = {0x837dca9e, 0xe874, 0x4d82, {0xb2, 0x9a, 0x23, 0xfe, 0x0e, 0x23, 0xd1, 0xe2}}
138 gQemuRamfbGuid = {0x557423a1, 0x63ab, 0x406c, {0xbe, 0x7e, 0x91, 0xcd, 0xbc, 0x08, 0xc4, 0x57}}
139 gXenBusRootDeviceGuid = {0xa732241f, 0x383d, 0x4d9c, {0x8a, 0xe1, 0x8e, 0x09, 0x83, 0x75, 0x89, 0xd7}}
140 gRootBridgesConnectedEventGroupGuid = {0x24a2d66f, 0xeedd, 0x4086, {0x90, 0x42, 0xf2, 0x6e, 0x47, 0x97, 0xee, 0x69}}
141 gMicrosoftVendorGuid = {0x77fa9abd, 0x0359, 0x4d32, {0xbd, 0x60, 0x28, 0xf4, 0xe7, 0x8f, 0x78, 0x4b}}
142 gEfiLegacyBiosGuid = {0x2E3044AC, 0x879F, 0x490F, {0x97, 0x60, 0xBB, 0xDF, 0xAF, 0x69, 0x5F, 0x50}}
143 gEfiLegacyDevOrderVariableGuid = {0xa56074db, 0x65fe, 0x45f7, {0xbd, 0x21, 0x2d, 0x2b, 0xdd, 0x8e, 0x96, 0x52}}
144 gQemuKernelLoaderFsMediaGuid = {0x1428f772, 0xb64a, 0x441e, {0xb8, 0xc3, 0x9e, 0xbd, 0xd7, 0xf8, 0x93, 0xc7}}
145 gGrubFileGuid = {0xb5ae312c, 0xbc8a, 0x43b1, {0x9c, 0x62, 0xeb, 0xb8, 0x26, 0xdd, 0x5d, 0x07}}
146 gConfidentialComputingSecretGuid = {0xadf956ad, 0xe98c, 0x484c, {0xae, 0x11, 0xb5, 0x1c, 0x7d, 0x33, 0x64, 0x47}}
147 gConfidentialComputingSevSnpBlobGuid = {0x067b1f5f, 0xcf26, 0x44c5, {0x85, 0x54, 0x93, 0xd7, 0x77, 0x91, 0x2d, 0x42}}
148 gUefiOvmfPkgPlatformInfoGuid = {0xdec9b486, 0x1f16, 0x47c7, {0x8f, 0x68, 0xdf, 0x1a, 0x41, 0x88, 0x8b, 0xa5}}
149 gQemuBootOrderGuid = {0x668f4529, 0x63d0, 0x4bb5, {0xb6, 0x5d, 0x6f, 0xbb, 0x9d, 0x36, 0xa4, 0x4a}}
150
151 [Ppis]
152 # PPI whose presence in the PPI database signals that the TPM base address
153 # has been discovered and recorded
154 gOvmfTpmDiscoveredPpiGuid = {0xb9a61ad0, 0x2802, 0x41f3, {0xb5, 0x13, 0x96, 0x51, 0xce, 0x6b, 0xd5, 0x75}}
155
156 # This PPI signals that accessing the MMIO range of the TPM is possible in
157 # the PEI phase, regardless of memory encryption
158 gOvmfTpmMmioAccessiblePpiGuid = {0x35c84ff2, 0x7bfe, 0x453d, {0x84, 0x5f, 0x68, 0x3a, 0x49, 0x2c, 0xf7, 0xb7}}
159
160 gEfiPeiMpInitLibMpDepPpiGuid = {0x138f9cf4, 0xf0e7, 0x4721, { 0x8f, 0x49, 0xf5, 0xff, 0xec, 0xf4, 0x2d, 0x40}}
161 gEfiPeiMpInitLibUpDepPpiGuid = {0xb590774, 0xbc67, 0x49f4, { 0xa7, 0xdb, 0xe8, 0x2e, 0x89, 0xe6, 0xb5, 0xd6}}
162
163 [Protocols]
164 gVirtioDeviceProtocolGuid = {0xfa920010, 0x6785, 0x4941, {0xb6, 0xec, 0x49, 0x8c, 0x57, 0x9f, 0x16, 0x0a}}
165 gXenBusProtocolGuid = {0x3d3ca290, 0xb9a5, 0x11e3, {0xb7, 0x5d, 0xb8, 0xac, 0x6f, 0x7d, 0x65, 0xe6}}
166 gXenIoProtocolGuid = {0x6efac84f, 0x0ab0, 0x4747, {0x81, 0xbe, 0x85, 0x55, 0x62, 0x59, 0x04, 0x49}}
167 gIoMmuAbsentProtocolGuid = {0xf8775d50, 0x8abd, 0x4adf, {0x92, 0xac, 0x85, 0x3e, 0x51, 0xf6, 0xc8, 0xdc}}
168 gEfiLegacy8259ProtocolGuid = {0x38321dba, 0x4fe0, 0x4e17, {0x8a, 0xec, 0x41, 0x30, 0x55, 0xea, 0xed, 0xc1}}
169 gEfiFirmwareVolumeProtocolGuid = {0x389F751F, 0x1838, 0x4388, {0x83, 0x90, 0xcd, 0x81, 0x54, 0xbd, 0x27, 0xf8}}
170 gEfiIsaAcpiProtocolGuid = {0x64a892dc, 0x5561, 0x4536, {0x92, 0xc7, 0x79, 0x9b, 0xfc, 0x18, 0x33, 0x55}}
171 gEfiIsaIoProtocolGuid = {0x7ee2bd44, 0x3da0, 0x11d4, {0x9a, 0x38, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d}}
172 gEfiLegacyBiosProtocolGuid = {0xdb9a1e3d, 0x45cb, 0x4abb, {0x85, 0x3b, 0xe5, 0x38, 0x7f, 0xdb, 0x2e, 0x2d}}
173 gEfiLegacyBiosPlatformProtocolGuid = {0x783658a3, 0x4172, 0x4421, {0xa2, 0x99, 0xe0, 0x09, 0x07, 0x9c, 0x0c, 0xb4}}
174 gEfiLegacyInterruptProtocolGuid = {0x31ce593d, 0x108a, 0x485d, {0xad, 0xb2, 0x78, 0xf2, 0x1f, 0x29, 0x66, 0xbe}}
175 gEfiVgaMiniPortProtocolGuid = {0xc7735a2f, 0x88f5, 0x4882, {0xae, 0x63, 0xfa, 0xac, 0x8c, 0x8b, 0x86, 0xb3}}
176 gOvmfLoadedX86LinuxKernelProtocolGuid = {0xa3edc05d, 0xb618, 0x4ff6, {0x95, 0x52, 0x76, 0xd7, 0x88, 0x63, 0x43, 0xc8}}
177 gQemuAcpiTableNotifyProtocolGuid = {0x928939b2, 0x4235, 0x462f, {0x95, 0x80, 0xf6, 0xa2, 0xb2, 0xc2, 0x1a, 0x4f}}
178 gEfiMpInitLibMpDepProtocolGuid = {0xbb00a5ca, 0x8ce, 0x462f, {0xa5, 0x37, 0x43, 0xc7, 0x4a, 0x82, 0x5c, 0xa4}}
179 gEfiMpInitLibUpDepProtocolGuid = {0xa9e7cef1, 0x5682, 0x42cc, {0xb1, 0x23, 0x99, 0x30, 0x97, 0x3f, 0x4a, 0x9f}}
180
181 [PcdsFixedAtBuild]
182 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase|0x0|UINT32|0
183 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize|0x0|UINT32|1
184 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|0x0|UINT32|0x15
185 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize|0x0|UINT32|0x16
186
187 ## This flag is used to control the destination port for PlatformDebugLibIoPort
188 gUefiOvmfPkgTokenSpaceGuid.PcdDebugIoPort|0x402|UINT16|4
189
190 ## When VirtioScsiDxe is instantiated for a HBA, the numbers of targets and
191 # LUNs are retrieved from the host during virtio-scsi setup.
192 # MdeModulePkg/Bus/Scsi/ScsiBusDxe then scans all MaxTarget * MaxLun
193 # possible devices. This can take extremely long, for example with
194 # MaxTarget=255 and MaxLun=16383. The *inclusive* constants below limit
195 # MaxTarget and MaxLun, independently, should the host report higher values,
196 # so that scanning the number of devices given by their product is still
197 # acceptably fast.
198 gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxTargetLimit|31|UINT16|6
199 gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxLunLimit|7|UINT32|7
200
201 ## Sets the *inclusive* number of targets and LUNs that PvScsi exposes for
202 # scan by ScsiBusDxe.
203 # As specified above for VirtioScsi, ScsiBusDxe scans all MaxTarget * MaxLun
204 # possible devices, which can take extremely long. Thus, the below constants
205 # are used so that scanning the number of devices given by their product
206 # is still acceptably fast.
207 gUefiOvmfPkgTokenSpaceGuid.PcdPvScsiMaxTargetLimit|64|UINT8|0x36
208 gUefiOvmfPkgTokenSpaceGuid.PcdPvScsiMaxLunLimit|0|UINT8|0x37
209
210 ## After PvScsiDxe sends a SCSI request to the device, it waits for
211 # the request completion in a polling loop.
212 # This constant defines how many micro-seconds to wait between each
213 # polling loop iteration.
214 gUefiOvmfPkgTokenSpaceGuid.PcdPvScsiWaitForCmpStallInUsecs|5|UINT32|0x38
215
216 ## Set the *inclusive* number of targets that MptScsi exposes for scan
217 # by ScsiBusDxe.
218 gUefiOvmfPkgTokenSpaceGuid.PcdMptScsiMaxTargetLimit|7|UINT8|0x39
219
220 ## Microseconds to stall between polling for MptScsi request result
221 gUefiOvmfPkgTokenSpaceGuid.PcdMptScsiStallPerPollUsec|5|UINT32|0x3a
222
223 ## Set the *inclusive* number of targets and LUNs that LsiScsi exposes for
224 # scan by ScsiBusDxe.
225 gUefiOvmfPkgTokenSpaceGuid.PcdLsiScsiMaxTargetLimit|7|UINT8|0x3b
226 gUefiOvmfPkgTokenSpaceGuid.PcdLsiScsiMaxLunLimit|0|UINT8|0x3c
227
228 ## Microseconds to stall between polling for LsiScsi request result
229 gUefiOvmfPkgTokenSpaceGuid.PcdLsiScsiStallPerPollUsec|5|UINT32|0x3d
230
231 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogBase|0x0|UINT32|0x8
232 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogSize|0x0|UINT32|0x9
233 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize|0x0|UINT32|0xa
234 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareBlockSize|0|UINT32|0xb
235 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase|0x0|UINT32|0xc
236 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwSpareBase|0x0|UINT32|0xd
237 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase|0x0|UINT32|0xe
238 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress|0x0|UINT32|0xf
239 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase|0x0|UINT32|0x11
240 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize|0x0|UINT32|0x12
241 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase|0x0|UINT32|0x13
242 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize|0x0|UINT32|0x14
243 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageBase|0x0|UINT32|0x18
244 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageSize|0x0|UINT32|0x19
245 gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize|0x0|UINT32|0x1a
246 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd|0x0|UINT32|0x1f
247
248 ## Pcd8259LegacyModeMask defines the default mask value for platform. This
249 # value is determined.
250 # 1) If platform only support pure UEFI, value should be set to 0xFFFF or
251 # 0xFFFE; Because only clock interrupt is allowed in legacy mode in pure
252 # UEFI platform.
253 # 2) If platform install CSM and use thunk module:
254 # a) If thunk call provided by CSM binary requires some legacy interrupt
255 # support, the corresponding bit should be opened as 0.
256 # For example, if keyboard interfaces provided CSM binary use legacy
257 # keyboard interrupt in 8259 bit 1, then the value should be set to
258 # 0xFFFC.
259 # b) If all thunk call provied by CSM binary do not require legacy
260 # interrupt support, value should be set to 0xFFFF or 0xFFFE.
261 #
262 # The default value of legacy mode mask could be changed by
263 # EFI_LEGACY_8259_PROTOCOL->SetMask(). But it is rarely need change it
264 # except some special cases such as when initializing the CSM binary, it
265 # should be set to 0xFFFF to mask all legacy interrupt. Please restore the
266 # original legacy mask value if changing is made for these special case.
267 gUefiOvmfPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0xFFFF|UINT16|0x3
268
269 ## Pcd8259LegacyModeEdgeLevel defines the default edge level for legacy
270 # mode's interrrupt controller.
271 # For the corresponding bits, 0 = Edge triggered and 1 = Level triggered.
272 gUefiOvmfPkgTokenSpaceGuid.Pcd8259LegacyModeEdgeLevel|0x0000|UINT16|0x5
273
274 ## Indicates if BiosVideo driver will switch to 80x25 Text VGA Mode when
275 # exiting boot service.
276 # TRUE - Switch to Text VGA Mode.
277 # FALSE - Does not switch to Text VGA Mode.
278 gUefiOvmfPkgTokenSpaceGuid.PcdBiosVideoSetTextVgaModeEnable|FALSE|BOOLEAN|0x28
279
280 ## Indicates if BiosVideo driver will check for VESA BIOS Extension service
281 # support.
282 # TRUE - Check for VESA BIOS Extension service.
283 # FALSE - Does not check for VESA BIOS Extension service.
284 gUefiOvmfPkgTokenSpaceGuid.PcdBiosVideoCheckVbeEnable|TRUE|BOOLEAN|0x29
285
286 ## Indicates if BiosVideo driver will check for VGA service support.
287 # NOTE: If both PcdBiosVideoCheckVbeEnable and PcdBiosVideoCheckVgaEnable
288 # are set to FALSE, that means Graphics Output protocol will not be
289 # installed, the VGA miniport protocol will be installed instead.
290 # TRUE - Check for VGA service.<BR>
291 # FALSE - Does not check for VGA service.<BR>
292 gUefiOvmfPkgTokenSpaceGuid.PcdBiosVideoCheckVgaEnable|TRUE|BOOLEAN|0x2a
293
294 ## Indicates if memory space for legacy region will be set as cacheable.
295 # TRUE - Set cachebility for legacy region.
296 # FALSE - Does not set cachebility for legacy region.
297 gUefiOvmfPkgTokenSpaceGuid.PcdLegacyBiosCacheLegacyRegion|TRUE|BOOLEAN|0x2b
298
299 ## Specify memory size with bytes to reserve EBDA below 640K for OPROM.
300 # The value should be a multiple of 4KB.
301 gUefiOvmfPkgTokenSpaceGuid.PcdEbdaReservedMemorySize|0x8000|UINT32|0x2c
302
303 ## Specify memory base address for OPROM to find free memory.
304 # Some OPROMs do not use EBDA or PMM to allocate memory for its usage,
305 # instead they find the memory filled with zero from 0x20000.
306 # The value should be a multiple of 4KB.
307 # The range should be below the EBDA reserved range from
308 # (CONVENTIONAL_MEMORY_TOP - Reserved EBDA Memory Size) to
309 # CONVENTIONAL_MEMORY_TOP.
310 gUefiOvmfPkgTokenSpaceGuid.PcdOpromReservedMemoryBase|0x60000|UINT32|0x2d
311
312 ## Specify memory size with bytes for OPROM to find free memory.
313 # The value should be a multiple of 4KB. And the range should be below the
314 # EBDA reserved range from
315 # (CONVENTIONAL_MEMORY_TOP - Reserved EBDA Memory Size) to
316 # CONVENTIONAL_MEMORY_TOP.
317 gUefiOvmfPkgTokenSpaceGuid.PcdOpromReservedMemorySize|0x28000|UINT32|0x2e
318
319 ## Specify the end of address below 1MB for the OPROM.
320 # The last shadowed OpROM should not exceed this address.
321 gUefiOvmfPkgTokenSpaceGuid.PcdEndOpromShadowAddress|0xdffff|UINT32|0x2f
322
323 ## Specify the low PMM (Post Memory Manager) size with bytes below 1MB.
324 # The value should be a multiple of 4KB.
325 # @Prompt Low PMM (Post Memory Manager) Size
326 gUefiOvmfPkgTokenSpaceGuid.PcdLowPmmMemorySize|0x10000|UINT32|0x30
327
328 ## Specify the high PMM (Post Memory Manager) size with bytes above 1MB.
329 # The value should be a multiple of 4KB.
330 gUefiOvmfPkgTokenSpaceGuid.PcdHighPmmMemorySize|0x400000|UINT32|0x31
331
332 gUefiOvmfPkgTokenSpaceGuid.PcdXenPvhStartOfDayStructPtr|0x0|UINT32|0x17
333 gUefiOvmfPkgTokenSpaceGuid.PcdXenPvhStartOfDayStructPtrSize|0x0|UINT32|0x32
334
335 ## Number of page frames to use for storing grant table entries.
336 gUefiOvmfPkgTokenSpaceGuid.PcdXenGrantFrames|4|UINT32|0x33
337
338 ## Specify the extra page table needed to mark the GHCB as unencrypted.
339 # The value should be a multiple of 4KB for each.
340 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableBase|0x0|UINT32|0x3e
341 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableSize|0x0|UINT32|0x3f
342
343 ## The base address of the SEC GHCB page used by SEV-ES.
344 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBase|0|UINT32|0x40
345 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbSize|0|UINT32|0x41
346 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupBase|0|UINT32|0x44
347 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupSize|0|UINT32|0x45
348
349 ## The base address and size of the SEV Launch Secret Area provisioned
350 # after remote attestation. If this is set in the .fdf, the platform
351 # is responsible for protecting the area from DXE phase overwrites.
352 gUefiOvmfPkgTokenSpaceGuid.PcdSevLaunchSecretBase|0x0|UINT32|0x42
353 gUefiOvmfPkgTokenSpaceGuid.PcdSevLaunchSecretSize|0x0|UINT32|0x43
354
355 ## The base address and size of a hash table confirming allowed
356 # parameters to be passed in via the Qemu firmware configuration
357 # device
358 gUefiOvmfPkgTokenSpaceGuid.PcdQemuHashTableBase|0x0|UINT32|0x47
359 gUefiOvmfPkgTokenSpaceGuid.PcdQemuHashTableSize|0x0|UINT32|0x48
360
361 ## The base address and size of the work area used during the SEC
362 # phase by the SEV and TDX supports.
363 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase|0|UINT32|0x49
364 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaSize|0|UINT32|0x50
365
366 ## The work area contains a fixed size header in the Include/WorkArea.h.
367 # The size of this header is used early boot, and is provided through
368 # a fixed PCD. It need to be kept in sync with any changes to the
369 # header definition.
370 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentialComputingWorkAreaHeader|4|UINT32|0x51
371
372 ## The base address and size of the TDX Cfv base and size.
373 gUefiOvmfPkgTokenSpaceGuid.PcdCfvBase|0|UINT32|0x52
374 gUefiOvmfPkgTokenSpaceGuid.PcdCfvRawDataOffset|0|UINT32|0x53
375 gUefiOvmfPkgTokenSpaceGuid.PcdCfvRawDataSize|0|UINT32|0x54
376
377 ## The base address and size of the TDX Bfv base and size.
378 gUefiOvmfPkgTokenSpaceGuid.PcdBfvBase|0|UINT32|0x55
379 gUefiOvmfPkgTokenSpaceGuid.PcdBfvRawDataOffset|0|UINT32|0x56
380 gUefiOvmfPkgTokenSpaceGuid.PcdBfvRawDataSize|0|UINT32|0x57
381
382 ## The base address and size of the SEV-SNP Secrets Area that contains
383 # the VM platform communication key used to send and recieve the
384 # messages to the PSP. If this is set in the .fdf, the platform
385 # is responsible to reserve this area from DXE phase overwrites.
386 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSnpSecretsBase|0|UINT32|0x58
387 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSnpSecretsSize|0|UINT32|0x59
388
389 ## The base address and size of a CPUID Area that contains the hypervisor
390 # provided CPUID results. In the case of SEV-SNP, the CPUID results are
391 # filtered by the SEV-SNP firmware. If this is set in the .fdf, the
392 # platform is responsible to reserve this area from DXE phase overwrites.
393 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidBase|0|UINT32|0x60
394 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidSize|0|UINT32|0x61
395
396 ## The range of memory that is validated by the SEC phase.
397 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecValidatedStart|0|UINT32|0x62
398 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecValidatedEnd|0|UINT32|0x63
399
400 ## The Tdx accept page size. 0x1000(4k),0x200000(2M)
401 gUefiOvmfPkgTokenSpaceGuid.PcdTdxAcceptPageSize|0x200000|UINT32|0x65
402
403 ## The QEMU fw_cfg variable that UefiDriverEntryPointFwCfgOverrideLib will
404 # check to decide whether to abort dispatch of the driver it is linked into.
405 gUefiOvmfPkgTokenSpaceGuid.PcdEntryPointOverrideFwCfgVarName|""|VOID*|0x68
406
407 [PcdsDynamic, PcdsDynamicEx]
408 gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|2
409 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BOOLEAN|0x10
410 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId|0|UINT16|0x1b
411 gUefiOvmfPkgTokenSpaceGuid.PcdQemuSmbiosValidated|FALSE|BOOLEAN|0x21
412
413 ## The IO port aperture shared by all PCI root bridges.
414 #
415 gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x22
416 gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x23
417
418 ## The 32-bit MMIO aperture shared by all PCI root bridges.
419 #
420 gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT64|0x24
421 gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT64|0x25
422
423 ## The 64-bit MMIO aperture shared by all PCI root bridges.
424 #
425 gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x26
426 gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x27
427
428 ## The following setting controls how many megabytes we configure as TSEG on
429 # Q35, for SMRAM purposes. Permitted defaults are: 1, 2, 8. Other defaults
430 # cause undefined behavior. During boot, the PCD is updated by PlatformPei
431 # to reflect the extended TSEG size, if one is advertized by QEMU.
432 #
433 # This PCD is only accessed if PcdSmmSmramRequire is TRUE (see below).
434 gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8|UINT16|0x20
435
436 ## Set to TRUE by PlatformPei if the Q35 board supports the "SMRAM at default
437 # SMBASE" feature.
438 #
439 # This PCD is only accessed if PcdSmmSmramRequire is TRUE (see below).
440 gUefiOvmfPkgTokenSpaceGuid.PcdQ35SmramAtDefaultSmbase|FALSE|BOOLEAN|0x34
441
442 ## This PCD adds a communication channel between OVMF's SmmCpuFeaturesLib
443 # instance in PiSmmCpuDxeSmm, and CpuHotplugSmm.
444 gUefiOvmfPkgTokenSpaceGuid.PcdCpuHotEjectDataAddress|0|UINT64|0x46
445
446 ## This PCD tracks where PcdVideo{Horizontal,Vertical}Resolution
447 # values are coming from.
448 # 0 - unset (defaults from platform dsc)
449 # 1 - set from PlatformConfig
450 # 2 - set by GOP Driver.
451 gUefiOvmfPkgTokenSpaceGuid.PcdVideoResolutionSource|0|UINT8|0x64
452
453 ## This PCD records LAML field in CC EVENTLOG ACPI table.
454 gUefiOvmfPkgTokenSpaceGuid.PcdCcEventlogAcpiTableLaml|0|UINT32|0x66
455
456 ## This PCD records LASA field in CC EVENTLOG ACPI table.
457 gUefiOvmfPkgTokenSpaceGuid.PcdCcEventlogAcpiTableLasa|0|UINT64|0x67
458
459 [PcdsFeatureFlag]
460 gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE|BOOLEAN|0x1c
461 gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|FALSE|BOOLEAN|0x1d
462
463 ## This feature flag enables SMM/SMRAM support. Note that it also requires
464 # such support from the underlying QEMU instance; if that support is not
465 # present, the firmware will reject continuing after a certain point.
466 #
467 # The flag also acts as a general "security switch"; when TRUE, many
468 # components will change behavior, with the goal of preventing a malicious
469 # runtime OS from tampering with firmware structures (special memory ranges
470 # used by OVMF, the varstore pflash chip, LockBox etc).
471 gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire|FALSE|BOOLEAN|0x1e
472
473 ## Informs modules (including pre-DXE-phase modules) whether the platform
474 # firmware contains a CSM (Compatibility Support Module).
475 #
476 gUefiOvmfPkgTokenSpaceGuid.PcdCsmEnable|FALSE|BOOLEAN|0x35