2 Memory Detection for Virtual Machines.
4 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
20 // The package level header files this module uses
25 // The Library classes this module consumes
27 #include <Library/BaseMemoryLib.h>
28 #include <Library/DebugLib.h>
29 #include <Library/HobLib.h>
30 #include <Library/IoLib.h>
31 #include <Library/PcdLib.h>
32 #include <Library/PeimEntryPoint.h>
33 #include <Library/ResourcePublicationLib.h>
34 #include <Library/MtrrLib.h>
35 #include <Library/QemuFwCfgLib.h>
40 UINT8 mPhysMemAddressWidth
;
43 GetSystemMemorySizeBelow4gb (
51 // CMOS 0x34/0x35 specifies the system memory above 16 MB.
52 // * CMOS(0x35) is the high byte
53 // * CMOS(0x34) is the low byte
54 // * The size is specified in 64kb chunks
55 // * Since this is memory above 16MB, the 16MB must be added
56 // into the calculation to get the total memory size.
59 Cmos0x34
= (UINT8
) CmosRead8 (0x34);
60 Cmos0x35
= (UINT8
) CmosRead8 (0x35);
62 return (UINT32
) (((UINTN
)((Cmos0x35
<< 8) + Cmos0x34
) << 16) + SIZE_16MB
);
68 GetSystemMemorySizeAbove4gb (
75 // CMOS 0x5b-0x5d specifies the system memory above 4GB MB.
76 // * CMOS(0x5d) is the most significant size byte
77 // * CMOS(0x5c) is the middle size byte
78 // * CMOS(0x5b) is the least significant size byte
79 // * The size is specified in 64kb chunks
83 for (CmosIndex
= 0x5d; CmosIndex
>= 0x5b; CmosIndex
--) {
84 Size
= (UINT32
) (Size
<< 8) + (UINT32
) CmosRead8 (CmosIndex
);
87 return LShiftU64 (Size
, 16);
92 Return the highest address that DXE could possibly use, plus one.
100 UINT64 FirstNonAddress
;
101 UINT64 Pci64Base
, Pci64Size
;
102 CHAR8 MbString
[7 + 1];
104 FIRMWARE_CONFIG_ITEM FwCfgItem
;
106 UINT64 HotPlugMemoryEnd
;
108 FirstNonAddress
= BASE_4GB
+ GetSystemMemorySizeAbove4gb ();
111 // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO
112 // resources to 32-bit anyway. See DegradeResource() in
113 // "PciResourceSupport.c".
116 if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode
)) {
117 return FirstNonAddress
;
122 // Otherwise, in order to calculate the highest address plus one, we must
123 // consider the 64-bit PCI host aperture too. Fetch the default size.
125 Pci64Size
= PcdGet64 (PcdPciMmio64Size
);
128 // See if the user specified the number of megabytes for the 64-bit PCI host
129 // aperture. The number of non-NUL characters in MbString allows for
130 // 9,999,999 MB, which is approximately 10 TB.
132 // As signaled by the "X-" prefix, this knob is experimental, and might go
135 Status
= QemuFwCfgFindFile ("opt/ovmf/X-PciMmio64Mb", &FwCfgItem
,
137 if (!EFI_ERROR (Status
)) {
138 if (FwCfgSize
>= sizeof MbString
) {
140 "%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\n",
143 QemuFwCfgSelectItem (FwCfgItem
);
144 QemuFwCfgReadBytes (FwCfgSize
, MbString
);
145 MbString
[FwCfgSize
] = '\0';
146 Pci64Size
= LShiftU64 (AsciiStrDecimalToUint64 (MbString
), 20);
150 if (Pci64Size
== 0) {
151 if (mBootMode
!= BOOT_ON_S3_RESUME
) {
152 DEBUG ((EFI_D_INFO
, "%a: disabling 64-bit PCI host aperture\n",
154 PcdSet64 (PcdPciMmio64Size
, 0);
158 // There's nothing more to do; the amount of memory above 4GB fully
159 // determines the highest address plus one. The memory hotplug area (see
160 // below) plays no role for the firmware in this case.
162 return FirstNonAddress
;
166 // The "etc/reserved-memory-end" fw_cfg file, when present, contains an
167 // absolute, exclusive end address for the memory hotplug area. This area
168 // starts right at the end of the memory above 4GB. The 64-bit PCI host
169 // aperture must be placed above it.
171 Status
= QemuFwCfgFindFile ("etc/reserved-memory-end", &FwCfgItem
,
173 if (!EFI_ERROR (Status
) && FwCfgSize
== sizeof HotPlugMemoryEnd
) {
174 QemuFwCfgSelectItem (FwCfgItem
);
175 QemuFwCfgReadBytes (FwCfgSize
, &HotPlugMemoryEnd
);
177 ASSERT (HotPlugMemoryEnd
>= FirstNonAddress
);
178 FirstNonAddress
= HotPlugMemoryEnd
;
182 // SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB, so
183 // that the host can map it with 1GB hugepages. Follow suit.
185 Pci64Base
= ALIGN_VALUE (FirstNonAddress
, (UINT64
)SIZE_1GB
);
186 Pci64Size
= ALIGN_VALUE (Pci64Size
, (UINT64
)SIZE_1GB
);
189 // The 64-bit PCI host aperture should also be "naturally" aligned. The
190 // alignment is determined by rounding the size of the aperture down to the
191 // next smaller or equal power of two. That is, align the aperture by the
192 // largest BAR size that can fit into it.
194 Pci64Base
= ALIGN_VALUE (Pci64Base
, GetPowerOfTwo64 (Pci64Size
));
196 if (mBootMode
!= BOOT_ON_S3_RESUME
) {
198 // The core PciHostBridgeDxe driver will automatically add this range to
199 // the GCD memory space map through our PciHostBridgeLib instance; here we
200 // only need to set the PCDs.
202 PcdSet64 (PcdPciMmio64Base
, Pci64Base
);
203 PcdSet64 (PcdPciMmio64Size
, Pci64Size
);
204 DEBUG ((EFI_D_INFO
, "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",
205 __FUNCTION__
, Pci64Base
, Pci64Size
));
209 // The useful address space ends with the 64-bit PCI host aperture.
211 FirstNonAddress
= Pci64Base
+ Pci64Size
;
212 return FirstNonAddress
;
217 Initialize the mPhysMemAddressWidth variable, based on guest RAM size.
220 AddressWidthInitialization (
224 UINT64 FirstNonAddress
;
227 // As guest-physical memory size grows, the permanent PEI RAM requirements
228 // are dominated by the identity-mapping page tables built by the DXE IPL.
229 // The DXL IPL keys off of the physical address bits advertized in the CPU
230 // HOB. To conserve memory, we calculate the minimum address width here.
232 FirstNonAddress
= GetFirstNonAddress ();
233 mPhysMemAddressWidth
= (UINT8
)HighBitSet64 (FirstNonAddress
);
236 // If FirstNonAddress is not an integral power of two, then we need an
239 if ((FirstNonAddress
& (FirstNonAddress
- 1)) != 0) {
240 ++mPhysMemAddressWidth
;
244 // The minimum address width is 36 (covers up to and excluding 64 GB, which
245 // is the maximum for Ia32 + PAE). The theoretical architecture maximum for
246 // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We
247 // can simply assert that here, since 48 bits are good enough for 256 TB.
249 if (mPhysMemAddressWidth
<= 36) {
250 mPhysMemAddressWidth
= 36;
252 ASSERT (mPhysMemAddressWidth
<= 48);
257 Calculate the cap for the permanent PEI memory.
265 BOOLEAN Page1GSupport
;
273 // If DXE is 32-bit, then just return the traditional 64 MB cap.
276 if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode
)) {
282 // Dependent on physical address width, PEI memory allocations can be
283 // dominated by the page tables built for 64-bit DXE. So we key the cap off
284 // of those. The code below is based on CreateIdentityMappingPageTables() in
285 // "MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c".
287 Page1GSupport
= FALSE
;
288 if (PcdGetBool (PcdUse1GPageTable
)) {
289 AsmCpuid (0x80000000, &RegEax
, NULL
, NULL
, NULL
);
290 if (RegEax
>= 0x80000001) {
291 AsmCpuid (0x80000001, NULL
, NULL
, NULL
, &RegEdx
);
292 if ((RegEdx
& BIT26
) != 0) {
293 Page1GSupport
= TRUE
;
298 if (mPhysMemAddressWidth
<= 39) {
300 PdpEntries
= 1 << (mPhysMemAddressWidth
- 30);
301 ASSERT (PdpEntries
<= 0x200);
303 Pml4Entries
= 1 << (mPhysMemAddressWidth
- 39);
304 ASSERT (Pml4Entries
<= 0x200);
308 TotalPages
= Page1GSupport
? Pml4Entries
+ 1 :
309 (PdpEntries
+ 1) * Pml4Entries
+ 1;
310 ASSERT (TotalPages
<= 0x40201);
313 // Add 64 MB for miscellaneous allocations. Note that for
314 // mPhysMemAddressWidth values close to 36, the cap will actually be
315 // dominated by this increment.
317 return (UINT32
)(EFI_PAGES_TO_SIZE (TotalPages
) + SIZE_64MB
);
322 Publish PEI core memory
324 @return EFI_SUCCESS The PEIM initialized successfully.
333 EFI_PHYSICAL_ADDRESS MemoryBase
;
335 UINT64 LowerMemorySize
;
338 if (mBootMode
== BOOT_ON_S3_RESUME
) {
339 MemoryBase
= PcdGet32 (PcdS3AcpiReservedMemoryBase
);
340 MemorySize
= PcdGet32 (PcdS3AcpiReservedMemorySize
);
342 LowerMemorySize
= GetSystemMemorySizeBelow4gb ();
343 if (FeaturePcdGet (PcdSmmSmramRequire
)) {
345 // TSEG is chipped from the end of low RAM
347 LowerMemorySize
-= FixedPcdGet8 (PcdQ35TsegMbytes
) * SIZE_1MB
;
350 PeiMemoryCap
= GetPeiMemoryCap ();
351 DEBUG ((EFI_D_INFO
, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",
352 __FUNCTION__
, mPhysMemAddressWidth
, PeiMemoryCap
>> 10));
355 // Determine the range of memory to use during PEI
357 // Technically we could lay the permanent PEI RAM over SEC's temporary
358 // decompression and scratch buffer even if "secure S3" is needed, since
359 // their lifetimes don't overlap. However, PeiFvInitialization() will cover
360 // RAM up to PcdOvmfDecompressionScratchEnd with an EfiACPIMemoryNVS memory
361 // allocation HOB, and other allocations served from the permanent PEI RAM
362 // shouldn't overlap with that HOB.
364 MemoryBase
= mS3Supported
&& FeaturePcdGet (PcdSmmSmramRequire
) ?
365 PcdGet32 (PcdOvmfDecompressionScratchEnd
) :
366 PcdGet32 (PcdOvmfDxeMemFvBase
) + PcdGet32 (PcdOvmfDxeMemFvSize
);
367 MemorySize
= LowerMemorySize
- MemoryBase
;
368 if (MemorySize
> PeiMemoryCap
) {
369 MemoryBase
= LowerMemorySize
- PeiMemoryCap
;
370 MemorySize
= PeiMemoryCap
;
375 // Publish this memory to the PEI Core
377 Status
= PublishSystemMemory(MemoryBase
, MemorySize
);
378 ASSERT_EFI_ERROR (Status
);
385 Peform Memory Detection for QEMU / KVM
394 UINT64 LowerMemorySize
;
395 UINT64 UpperMemorySize
;
396 MTRR_SETTINGS MtrrSettings
;
399 DEBUG ((EFI_D_INFO
, "%a called\n", __FUNCTION__
));
402 // Determine total memory size available
404 LowerMemorySize
= GetSystemMemorySizeBelow4gb ();
405 UpperMemorySize
= GetSystemMemorySizeAbove4gb ();
407 if (mBootMode
!= BOOT_ON_S3_RESUME
) {
409 // Create memory HOBs
411 AddMemoryRangeHob (0, BASE_512KB
+ BASE_128KB
);
413 if (FeaturePcdGet (PcdSmmSmramRequire
)) {
416 TsegSize
= FixedPcdGet8 (PcdQ35TsegMbytes
) * SIZE_1MB
;
417 AddMemoryRangeHob (BASE_1MB
, LowerMemorySize
- TsegSize
);
418 AddReservedMemoryBaseSizeHob (LowerMemorySize
- TsegSize
, TsegSize
,
421 AddMemoryRangeHob (BASE_1MB
, LowerMemorySize
);
424 if (UpperMemorySize
!= 0) {
425 AddMemoryBaseSizeHob (BASE_4GB
, UpperMemorySize
);
430 // We'd like to keep the following ranges uncached:
432 // - [LowerMemorySize, 4 GB)
434 // Everything else should be WB. Unfortunately, programming the inverse (ie.
435 // keeping the default UC, and configuring the complement set of the above as
436 // WB) is not reliable in general, because the end of the upper RAM can have
437 // practically any alignment, and we may not have enough variable MTRRs to
440 if (IsMtrrSupported ()) {
441 MtrrGetAllMtrrs (&MtrrSettings
);
444 // MTRRs disabled, fixed MTRRs disabled, default type is uncached
446 ASSERT ((MtrrSettings
.MtrrDefType
& BIT11
) == 0);
447 ASSERT ((MtrrSettings
.MtrrDefType
& BIT10
) == 0);
448 ASSERT ((MtrrSettings
.MtrrDefType
& 0xFF) == 0);
451 // flip default type to writeback
453 SetMem (&MtrrSettings
.Fixed
, sizeof MtrrSettings
.Fixed
, 0x06);
454 ZeroMem (&MtrrSettings
.Variables
, sizeof MtrrSettings
.Variables
);
455 MtrrSettings
.MtrrDefType
|= BIT11
| BIT10
| 6;
456 MtrrSetAllMtrrs (&MtrrSettings
);
459 // Set memory range from 640KB to 1MB to uncacheable
461 Status
= MtrrSetMemoryAttribute (BASE_512KB
+ BASE_128KB
,
462 BASE_1MB
- (BASE_512KB
+ BASE_128KB
), CacheUncacheable
);
463 ASSERT_EFI_ERROR (Status
);
466 // Set memory range from the "top of lower RAM" (RAM below 4GB) to 4GB as
469 Status
= MtrrSetMemoryAttribute (LowerMemorySize
,
470 SIZE_4GB
- LowerMemorySize
, CacheUncacheable
);
471 ASSERT_EFI_ERROR (Status
);
476 Publish system RAM and reserve memory regions
480 InitializeRamRegions (
485 QemuInitializeRam ();
487 XenPublishRamRegions ();
490 if (mS3Supported
&& mBootMode
!= BOOT_ON_S3_RESUME
) {
492 // This is the memory range that will be used for PEI on S3 resume
494 BuildMemoryAllocationHob (
495 (EFI_PHYSICAL_ADDRESS
)(UINTN
) PcdGet32 (PcdS3AcpiReservedMemoryBase
),
496 (UINT64
)(UINTN
) PcdGet32 (PcdS3AcpiReservedMemorySize
),
501 // Cover the initial RAM area used as stack and temporary PEI heap.
503 // This is reserved as ACPI NVS so it can be used on S3 resume.
505 BuildMemoryAllocationHob (
506 PcdGet32 (PcdOvmfSecPeiTempRamBase
),
507 PcdGet32 (PcdOvmfSecPeiTempRamSize
),
512 // SEC stores its table of GUIDed section handlers here.
514 BuildMemoryAllocationHob (
515 PcdGet64 (PcdGuidedExtractHandlerTableAddress
),
516 PcdGet32 (PcdGuidedExtractHandlerTableSize
),
522 // Reserve the initial page tables built by the reset vector code.
524 // Since this memory range will be used by the Reset Vector on S3
525 // resume, it must be reserved as ACPI NVS.
527 BuildMemoryAllocationHob (
528 (EFI_PHYSICAL_ADDRESS
)(UINTN
) PcdGet32 (PcdOvmfSecPageTablesBase
),
529 (UINT64
)(UINTN
) PcdGet32 (PcdOvmfSecPageTablesSize
),
535 if (mBootMode
!= BOOT_ON_S3_RESUME
) {
536 if (!FeaturePcdGet (PcdSmmSmramRequire
)) {
538 // Reserve the lock box storage area
540 // Since this memory range will be used on S3 resume, it must be
541 // reserved as ACPI NVS.
543 // If S3 is unsupported, then various drivers might still write to the
544 // LockBox area. We ought to prevent DXE from serving allocation requests
545 // such that they would overlap the LockBox storage.
548 (VOID
*)(UINTN
) PcdGet32 (PcdOvmfLockBoxStorageBase
),
549 (UINTN
) PcdGet32 (PcdOvmfLockBoxStorageSize
)
551 BuildMemoryAllocationHob (
552 (EFI_PHYSICAL_ADDRESS
)(UINTN
) PcdGet32 (PcdOvmfLockBoxStorageBase
),
553 (UINT64
)(UINTN
) PcdGet32 (PcdOvmfLockBoxStorageSize
),
554 mS3Supported
? EfiACPIMemoryNVS
: EfiBootServicesData
558 if (FeaturePcdGet (PcdSmmSmramRequire
)) {
562 // Make sure the TSEG area that we reported as a reserved memory resource
563 // cannot be used for reserved memory allocations.
565 TsegSize
= FixedPcdGet8 (PcdQ35TsegMbytes
) * SIZE_1MB
;
566 BuildMemoryAllocationHob (
567 GetSystemMemorySizeBelow4gb() - TsegSize
,
569 EfiReservedMemoryType