2 Memory Detection for Virtual Machines.
4 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
14 // The package level header files this module uses
16 #include <IndustryStandard/E820.h>
17 #include <IndustryStandard/I440FxPiix4.h>
18 #include <IndustryStandard/Q35MchIch9.h>
20 #include <Register/Intel/SmramSaveStateMap.h>
23 // The Library classes this module consumes
25 #include <Library/BaseLib.h>
26 #include <Library/BaseMemoryLib.h>
27 #include <Library/DebugLib.h>
28 #include <Library/HobLib.h>
29 #include <Library/IoLib.h>
30 #include <Library/MemEncryptSevLib.h>
31 #include <Library/PcdLib.h>
32 #include <Library/PciLib.h>
33 #include <Library/PeimEntryPoint.h>
34 #include <Library/ResourcePublicationLib.h>
35 #include <Library/MtrrLib.h>
36 #include <Library/QemuFwCfgLib.h>
37 #include <Library/QemuFwCfgSimpleParserLib.h>
42 UINT8 mPhysMemAddressWidth
;
44 STATIC UINT32 mS3AcpiReservedMemoryBase
;
45 STATIC UINT32 mS3AcpiReservedMemorySize
;
47 STATIC UINT16 mQ35TsegMbytes
;
49 BOOLEAN mQ35SmramAtDefaultSmbase
;
54 Q35TsegMbytesInitialization (
58 UINT16 ExtendedTsegMbytes
;
59 RETURN_STATUS PcdStatus
;
61 ASSERT (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
);
64 // Check if QEMU offers an extended TSEG.
66 // This can be seen from writing MCH_EXT_TSEG_MB_QUERY to the MCH_EXT_TSEG_MB
67 // register, and reading back the register.
69 // On a QEMU machine type that does not offer an extended TSEG, the initial
70 // write overwrites whatever value a malicious guest OS may have placed in
71 // the (unimplemented) register, before entering S3 or rebooting.
72 // Subsequently, the read returns MCH_EXT_TSEG_MB_QUERY unchanged.
74 // On a QEMU machine type that offers an extended TSEG, the initial write
75 // triggers an update to the register. Subsequently, the value read back
76 // (which is guaranteed to differ from MCH_EXT_TSEG_MB_QUERY) tells us the
77 // number of megabytes.
79 PciWrite16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB
), MCH_EXT_TSEG_MB_QUERY
);
80 ExtendedTsegMbytes
= PciRead16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB
));
81 if (ExtendedTsegMbytes
== MCH_EXT_TSEG_MB_QUERY
) {
82 mQ35TsegMbytes
= PcdGet16 (PcdQ35TsegMbytes
);
88 "%a: QEMU offers an extended TSEG (%d MB)\n",
92 PcdStatus
= PcdSet16S (PcdQ35TsegMbytes
, ExtendedTsegMbytes
);
93 ASSERT_RETURN_ERROR (PcdStatus
);
94 mQ35TsegMbytes
= ExtendedTsegMbytes
;
99 Q35SmramAtDefaultSmbaseInitialization (
103 RETURN_STATUS PcdStatus
;
105 ASSERT (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
);
107 mQ35SmramAtDefaultSmbase
= FALSE
;
108 if (FeaturePcdGet (PcdCsmEnable
)) {
109 DEBUG ((DEBUG_INFO
, "%a: SMRAM at default SMBASE not checked due to CSM\n",
115 CtlReg
= DRAMC_REGISTER_Q35 (MCH_DEFAULT_SMBASE_CTL
);
116 PciWrite8 (CtlReg
, MCH_DEFAULT_SMBASE_QUERY
);
117 CtlRegVal
= PciRead8 (CtlReg
);
118 mQ35SmramAtDefaultSmbase
= (BOOLEAN
)(CtlRegVal
==
119 MCH_DEFAULT_SMBASE_IN_RAM
);
120 DEBUG ((DEBUG_INFO
, "%a: SMRAM at default SMBASE %a\n", __FUNCTION__
,
121 mQ35SmramAtDefaultSmbase
? "found" : "not found"));
124 PcdStatus
= PcdSetBoolS (PcdQ35SmramAtDefaultSmbase
,
125 mQ35SmramAtDefaultSmbase
);
126 ASSERT_RETURN_ERROR (PcdStatus
);
131 QemuUc32BaseInitialization (
135 UINT32 LowerMemorySize
;
138 if (mHostBridgeDevId
== 0xffff /* microvm */) {
142 if (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
144 // On q35, the 32-bit area that we'll mark as UC, through variable MTRRs,
145 // starts at PcdPciExpressBaseAddress. The platform DSC is responsible for
146 // setting PcdPciExpressBaseAddress such that describing the
147 // [PcdPciExpressBaseAddress, 4GB) range require a very small number of
148 // variable MTRRs (preferably 1 or 2).
150 ASSERT (FixedPcdGet64 (PcdPciExpressBaseAddress
) <= MAX_UINT32
);
151 mQemuUc32Base
= (UINT32
)FixedPcdGet64 (PcdPciExpressBaseAddress
);
155 ASSERT (mHostBridgeDevId
== INTEL_82441_DEVICE_ID
);
157 // On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one
158 // variable MTRR suffices by truncating the size to a whole power of two,
159 // while keeping the end affixed to 4GB. This will round the base up.
161 LowerMemorySize
= GetSystemMemorySizeBelow4gb ();
162 Uc32Size
= GetPowerOfTwo32 ((UINT32
)(SIZE_4GB
- LowerMemorySize
));
163 mQemuUc32Base
= (UINT32
)(SIZE_4GB
- Uc32Size
);
165 // Assuming that LowerMemorySize is at least 1 byte, Uc32Size is at most 2GB.
166 // Therefore mQemuUc32Base is at least 2GB.
168 ASSERT (mQemuUc32Base
>= BASE_2GB
);
170 if (mQemuUc32Base
!= LowerMemorySize
) {
171 DEBUG ((DEBUG_VERBOSE
, "%a: rounded UC32 base from 0x%x up to 0x%x, for "
172 "an UC32 size of 0x%x\n", __FUNCTION__
, LowerMemorySize
, mQemuUc32Base
,
179 Iterate over the RAM entries in QEMU's fw_cfg E820 RAM map that start outside
180 of the 32-bit address range.
182 Find the highest exclusive >=4GB RAM address, or produce memory resource
183 descriptor HOBs for RAM entries that start at or above 4GB.
185 @param[out] MaxAddress If MaxAddress is NULL, then ScanOrAdd64BitE820Ram()
186 produces memory resource descriptor HOBs for RAM
187 entries that start at or above 4GB.
189 Otherwise, MaxAddress holds the highest exclusive
190 >=4GB RAM address on output. If QEMU's fw_cfg E820
191 RAM map contains no RAM entry that starts outside of
192 the 32-bit address range, then MaxAddress is exactly
195 @retval EFI_SUCCESS The fw_cfg E820 RAM map was found and processed.
197 @retval EFI_PROTOCOL_ERROR The RAM map was found, but its size wasn't a
198 whole multiple of sizeof(EFI_E820_ENTRY64). No
199 RAM entry was processed.
201 @return Error codes from QemuFwCfgFindFile(). No RAM
206 ScanOrAdd64BitE820Ram (
207 OUT UINT64
*MaxAddress OPTIONAL
211 FIRMWARE_CONFIG_ITEM FwCfgItem
;
213 EFI_E820_ENTRY64 E820Entry
;
216 Status
= QemuFwCfgFindFile ("etc/e820", &FwCfgItem
, &FwCfgSize
);
217 if (EFI_ERROR (Status
)) {
220 if (FwCfgSize
% sizeof E820Entry
!= 0) {
221 return EFI_PROTOCOL_ERROR
;
224 if (MaxAddress
!= NULL
) {
225 *MaxAddress
= BASE_4GB
;
228 QemuFwCfgSelectItem (FwCfgItem
);
229 for (Processed
= 0; Processed
< FwCfgSize
; Processed
+= sizeof E820Entry
) {
230 QemuFwCfgReadBytes (sizeof E820Entry
, &E820Entry
);
233 "%a: Base=0x%Lx Length=0x%Lx Type=%u\n",
239 if (E820Entry
.Type
== EfiAcpiAddressRangeMemory
&&
240 E820Entry
.BaseAddr
>= BASE_4GB
) {
241 if (MaxAddress
== NULL
) {
246 // Round up the start address, and round down the end address.
248 Base
= ALIGN_VALUE (E820Entry
.BaseAddr
, (UINT64
)EFI_PAGE_SIZE
);
249 End
= (E820Entry
.BaseAddr
+ E820Entry
.Length
) &
250 ~(UINT64
)EFI_PAGE_MASK
;
252 AddMemoryRangeHob (Base
, End
);
255 "%a: AddMemoryRangeHob [0x%Lx, 0x%Lx)\n",
264 Candidate
= E820Entry
.BaseAddr
+ E820Entry
.Length
;
265 if (Candidate
> *MaxAddress
) {
266 *MaxAddress
= Candidate
;
269 "%a: MaxAddress=0x%Lx\n",
282 GetSystemMemorySizeBelow4gb (
290 // CMOS 0x34/0x35 specifies the system memory above 16 MB.
291 // * CMOS(0x35) is the high byte
292 // * CMOS(0x34) is the low byte
293 // * The size is specified in 64kb chunks
294 // * Since this is memory above 16MB, the 16MB must be added
295 // into the calculation to get the total memory size.
298 Cmos0x34
= (UINT8
) CmosRead8 (0x34);
299 Cmos0x35
= (UINT8
) CmosRead8 (0x35);
301 return (UINT32
) (((UINTN
)((Cmos0x35
<< 8) + Cmos0x34
) << 16) + SIZE_16MB
);
307 GetSystemMemorySizeAbove4gb (
314 // CMOS 0x5b-0x5d specifies the system memory above 4GB MB.
315 // * CMOS(0x5d) is the most significant size byte
316 // * CMOS(0x5c) is the middle size byte
317 // * CMOS(0x5b) is the least significant size byte
318 // * The size is specified in 64kb chunks
322 for (CmosIndex
= 0x5d; CmosIndex
>= 0x5b; CmosIndex
--) {
323 Size
= (UINT32
) (Size
<< 8) + (UINT32
) CmosRead8 (CmosIndex
);
326 return LShiftU64 (Size
, 16);
331 Return the highest address that DXE could possibly use, plus one.
339 UINT64 FirstNonAddress
;
340 UINT64 Pci64Base
, Pci64Size
;
341 UINT32 FwCfgPciMmio64Mb
;
343 FIRMWARE_CONFIG_ITEM FwCfgItem
;
345 UINT64 HotPlugMemoryEnd
;
346 RETURN_STATUS PcdStatus
;
349 // set FirstNonAddress to suppress incorrect compiler/analyzer warnings
354 // If QEMU presents an E820 map, then get the highest exclusive >=4GB RAM
355 // address from it. This can express an address >= 4GB+1TB.
357 // Otherwise, get the flat size of the memory above 4GB from the CMOS (which
358 // can only express a size smaller than 1TB), and add it to 4GB.
360 Status
= ScanOrAdd64BitE820Ram (&FirstNonAddress
);
361 if (EFI_ERROR (Status
)) {
362 FirstNonAddress
= BASE_4GB
+ GetSystemMemorySizeAbove4gb ();
366 // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO
367 // resources to 32-bit anyway. See DegradeResource() in
368 // "PciResourceSupport.c".
371 if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode
)) {
372 return FirstNonAddress
;
377 // Otherwise, in order to calculate the highest address plus one, we must
378 // consider the 64-bit PCI host aperture too. Fetch the default size.
380 Pci64Size
= PcdGet64 (PcdPciMmio64Size
);
383 // See if the user specified the number of megabytes for the 64-bit PCI host
384 // aperture. Accept an aperture size up to 16TB.
386 // As signaled by the "X-" prefix, this knob is experimental, and might go
389 Status
= QemuFwCfgParseUint32 ("opt/ovmf/X-PciMmio64Mb", FALSE
,
392 case EFI_UNSUPPORTED
:
396 if (FwCfgPciMmio64Mb
<= 0x1000000) {
397 Pci64Size
= LShiftU64 (FwCfgPciMmio64Mb
, 20);
405 "%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\n",
410 if (Pci64Size
== 0) {
411 if (mBootMode
!= BOOT_ON_S3_RESUME
) {
412 DEBUG ((DEBUG_INFO
, "%a: disabling 64-bit PCI host aperture\n",
414 PcdStatus
= PcdSet64S (PcdPciMmio64Size
, 0);
415 ASSERT_RETURN_ERROR (PcdStatus
);
419 // There's nothing more to do; the amount of memory above 4GB fully
420 // determines the highest address plus one. The memory hotplug area (see
421 // below) plays no role for the firmware in this case.
423 return FirstNonAddress
;
427 // The "etc/reserved-memory-end" fw_cfg file, when present, contains an
428 // absolute, exclusive end address for the memory hotplug area. This area
429 // starts right at the end of the memory above 4GB. The 64-bit PCI host
430 // aperture must be placed above it.
432 Status
= QemuFwCfgFindFile ("etc/reserved-memory-end", &FwCfgItem
,
434 if (!EFI_ERROR (Status
) && FwCfgSize
== sizeof HotPlugMemoryEnd
) {
435 QemuFwCfgSelectItem (FwCfgItem
);
436 QemuFwCfgReadBytes (FwCfgSize
, &HotPlugMemoryEnd
);
437 DEBUG ((DEBUG_VERBOSE
, "%a: HotPlugMemoryEnd=0x%Lx\n", __FUNCTION__
,
440 ASSERT (HotPlugMemoryEnd
>= FirstNonAddress
);
441 FirstNonAddress
= HotPlugMemoryEnd
;
445 // SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB, so
446 // that the host can map it with 1GB hugepages. Follow suit.
448 Pci64Base
= ALIGN_VALUE (FirstNonAddress
, (UINT64
)SIZE_1GB
);
449 Pci64Size
= ALIGN_VALUE (Pci64Size
, (UINT64
)SIZE_1GB
);
452 // The 64-bit PCI host aperture should also be "naturally" aligned. The
453 // alignment is determined by rounding the size of the aperture down to the
454 // next smaller or equal power of two. That is, align the aperture by the
455 // largest BAR size that can fit into it.
457 Pci64Base
= ALIGN_VALUE (Pci64Base
, GetPowerOfTwo64 (Pci64Size
));
459 if (mBootMode
!= BOOT_ON_S3_RESUME
) {
461 // The core PciHostBridgeDxe driver will automatically add this range to
462 // the GCD memory space map through our PciHostBridgeLib instance; here we
463 // only need to set the PCDs.
465 PcdStatus
= PcdSet64S (PcdPciMmio64Base
, Pci64Base
);
466 ASSERT_RETURN_ERROR (PcdStatus
);
467 PcdStatus
= PcdSet64S (PcdPciMmio64Size
, Pci64Size
);
468 ASSERT_RETURN_ERROR (PcdStatus
);
470 DEBUG ((DEBUG_INFO
, "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",
471 __FUNCTION__
, Pci64Base
, Pci64Size
));
475 // The useful address space ends with the 64-bit PCI host aperture.
477 FirstNonAddress
= Pci64Base
+ Pci64Size
;
478 return FirstNonAddress
;
483 Initialize the mPhysMemAddressWidth variable, based on guest RAM size.
486 AddressWidthInitialization (
490 UINT64 FirstNonAddress
;
493 // As guest-physical memory size grows, the permanent PEI RAM requirements
494 // are dominated by the identity-mapping page tables built by the DXE IPL.
495 // The DXL IPL keys off of the physical address bits advertized in the CPU
496 // HOB. To conserve memory, we calculate the minimum address width here.
498 FirstNonAddress
= GetFirstNonAddress ();
499 mPhysMemAddressWidth
= (UINT8
)HighBitSet64 (FirstNonAddress
);
502 // If FirstNonAddress is not an integral power of two, then we need an
505 if ((FirstNonAddress
& (FirstNonAddress
- 1)) != 0) {
506 ++mPhysMemAddressWidth
;
510 // The minimum address width is 36 (covers up to and excluding 64 GB, which
511 // is the maximum for Ia32 + PAE). The theoretical architecture maximum for
512 // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We
513 // can simply assert that here, since 48 bits are good enough for 256 TB.
515 if (mPhysMemAddressWidth
<= 36) {
516 mPhysMemAddressWidth
= 36;
518 ASSERT (mPhysMemAddressWidth
<= 48);
523 Calculate the cap for the permanent PEI memory.
531 BOOLEAN Page1GSupport
;
539 // If DXE is 32-bit, then just return the traditional 64 MB cap.
542 if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode
)) {
548 // Dependent on physical address width, PEI memory allocations can be
549 // dominated by the page tables built for 64-bit DXE. So we key the cap off
550 // of those. The code below is based on CreateIdentityMappingPageTables() in
551 // "MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c".
553 Page1GSupport
= FALSE
;
554 if (PcdGetBool (PcdUse1GPageTable
)) {
555 AsmCpuid (0x80000000, &RegEax
, NULL
, NULL
, NULL
);
556 if (RegEax
>= 0x80000001) {
557 AsmCpuid (0x80000001, NULL
, NULL
, NULL
, &RegEdx
);
558 if ((RegEdx
& BIT26
) != 0) {
559 Page1GSupport
= TRUE
;
564 if (mPhysMemAddressWidth
<= 39) {
566 PdpEntries
= 1 << (mPhysMemAddressWidth
- 30);
567 ASSERT (PdpEntries
<= 0x200);
569 Pml4Entries
= 1 << (mPhysMemAddressWidth
- 39);
570 ASSERT (Pml4Entries
<= 0x200);
574 TotalPages
= Page1GSupport
? Pml4Entries
+ 1 :
575 (PdpEntries
+ 1) * Pml4Entries
+ 1;
576 ASSERT (TotalPages
<= 0x40201);
579 // Add 64 MB for miscellaneous allocations. Note that for
580 // mPhysMemAddressWidth values close to 36, the cap will actually be
581 // dominated by this increment.
583 return (UINT32
)(EFI_PAGES_TO_SIZE (TotalPages
) + SIZE_64MB
);
588 Publish PEI core memory
590 @return EFI_SUCCESS The PEIM initialized successfully.
599 EFI_PHYSICAL_ADDRESS MemoryBase
;
601 UINT32 LowerMemorySize
;
604 LowerMemorySize
= GetSystemMemorySizeBelow4gb ();
605 if (FeaturePcdGet (PcdSmmSmramRequire
)) {
607 // TSEG is chipped from the end of low RAM
609 LowerMemorySize
-= mQ35TsegMbytes
* SIZE_1MB
;
613 // If S3 is supported, then the S3 permanent PEI memory is placed next,
614 // downwards. Its size is primarily dictated by CpuMpPei. The formula below
615 // is an approximation.
618 mS3AcpiReservedMemorySize
= SIZE_512KB
+
620 PcdGet32 (PcdCpuApStackSize
);
621 mS3AcpiReservedMemoryBase
= LowerMemorySize
- mS3AcpiReservedMemorySize
;
622 LowerMemorySize
= mS3AcpiReservedMemoryBase
;
625 if (mBootMode
== BOOT_ON_S3_RESUME
) {
626 MemoryBase
= mS3AcpiReservedMemoryBase
;
627 MemorySize
= mS3AcpiReservedMemorySize
;
629 PeiMemoryCap
= GetPeiMemoryCap ();
630 DEBUG ((DEBUG_INFO
, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",
631 __FUNCTION__
, mPhysMemAddressWidth
, PeiMemoryCap
>> 10));
634 // Determine the range of memory to use during PEI
636 // Technically we could lay the permanent PEI RAM over SEC's temporary
637 // decompression and scratch buffer even if "secure S3" is needed, since
638 // their lifetimes don't overlap. However, PeiFvInitialization() will cover
639 // RAM up to PcdOvmfDecompressionScratchEnd with an EfiACPIMemoryNVS memory
640 // allocation HOB, and other allocations served from the permanent PEI RAM
641 // shouldn't overlap with that HOB.
643 MemoryBase
= mS3Supported
&& FeaturePcdGet (PcdSmmSmramRequire
) ?
644 PcdGet32 (PcdOvmfDecompressionScratchEnd
) :
645 PcdGet32 (PcdOvmfDxeMemFvBase
) + PcdGet32 (PcdOvmfDxeMemFvSize
);
646 MemorySize
= LowerMemorySize
- MemoryBase
;
647 if (MemorySize
> PeiMemoryCap
) {
648 MemoryBase
= LowerMemorySize
- PeiMemoryCap
;
649 MemorySize
= PeiMemoryCap
;
654 // MEMFD_BASE_ADDRESS separates the SMRAM at the default SMBASE from the
655 // normal boot permanent PEI RAM. Regarding the S3 boot path, the S3
656 // permanent PEI RAM is located even higher.
658 if (FeaturePcdGet (PcdSmmSmramRequire
) && mQ35SmramAtDefaultSmbase
) {
659 ASSERT (SMM_DEFAULT_SMBASE
+ MCH_DEFAULT_SMBASE_SIZE
<= MemoryBase
);
663 // Publish this memory to the PEI Core
665 Status
= PublishSystemMemory(MemoryBase
, MemorySize
);
666 ASSERT_EFI_ERROR (Status
);
674 QemuInitializeRamBelow1gb (
678 if (FeaturePcdGet (PcdSmmSmramRequire
) && mQ35SmramAtDefaultSmbase
) {
679 AddMemoryRangeHob (0, SMM_DEFAULT_SMBASE
);
680 AddReservedMemoryBaseSizeHob (SMM_DEFAULT_SMBASE
, MCH_DEFAULT_SMBASE_SIZE
,
681 TRUE
/* Cacheable */);
683 SMM_DEFAULT_SMBASE
+ MCH_DEFAULT_SMBASE_SIZE
< BASE_512KB
+ BASE_128KB
,
684 "end of SMRAM at default SMBASE ends at, or exceeds, 640KB"
686 AddMemoryRangeHob (SMM_DEFAULT_SMBASE
+ MCH_DEFAULT_SMBASE_SIZE
,
687 BASE_512KB
+ BASE_128KB
);
689 AddMemoryRangeHob (0, BASE_512KB
+ BASE_128KB
);
695 Peform Memory Detection for QEMU / KVM
704 UINT64 LowerMemorySize
;
705 UINT64 UpperMemorySize
;
706 MTRR_SETTINGS MtrrSettings
;
709 DEBUG ((DEBUG_INFO
, "%a called\n", __FUNCTION__
));
712 // Determine total memory size available
714 LowerMemorySize
= GetSystemMemorySizeBelow4gb ();
715 UpperMemorySize
= GetSystemMemorySizeAbove4gb ();
717 if (mBootMode
== BOOT_ON_S3_RESUME
) {
719 // Create the following memory HOB as an exception on the S3 boot path.
721 // Normally we'd create memory HOBs only on the normal boot path. However,
722 // CpuMpPei specifically needs such a low-memory HOB on the S3 path as
723 // well, for "borrowing" a subset of it temporarily, for the AP startup
726 // CpuMpPei saves the original contents of the borrowed area in permanent
727 // PEI RAM, in a backup buffer allocated with the normal PEI services.
728 // CpuMpPei restores the original contents ("returns" the borrowed area) at
729 // End-of-PEI. End-of-PEI in turn is emitted by S3Resume2Pei before
730 // transferring control to the OS's wakeup vector in the FACS.
732 // We expect any other PEIMs that "borrow" memory similarly to CpuMpPei to
733 // restore the original contents. Furthermore, we expect all such PEIMs
734 // (CpuMpPei included) to claim the borrowed areas by producing memory
735 // allocation HOBs, and to honor preexistent memory allocation HOBs when
736 // looking for an area to borrow.
738 QemuInitializeRamBelow1gb ();
741 // Create memory HOBs
743 QemuInitializeRamBelow1gb ();
745 if (FeaturePcdGet (PcdSmmSmramRequire
)) {
748 TsegSize
= mQ35TsegMbytes
* SIZE_1MB
;
749 AddMemoryRangeHob (BASE_1MB
, LowerMemorySize
- TsegSize
);
750 AddReservedMemoryBaseSizeHob (LowerMemorySize
- TsegSize
, TsegSize
,
753 AddMemoryRangeHob (BASE_1MB
, LowerMemorySize
);
757 // If QEMU presents an E820 map, then create memory HOBs for the >=4GB RAM
758 // entries. Otherwise, create a single memory HOB with the flat >=4GB
759 // memory size read from the CMOS.
761 Status
= ScanOrAdd64BitE820Ram (NULL
);
762 if (EFI_ERROR (Status
) && UpperMemorySize
!= 0) {
763 AddMemoryBaseSizeHob (BASE_4GB
, UpperMemorySize
);
768 // We'd like to keep the following ranges uncached:
770 // - [LowerMemorySize, 4 GB)
772 // Everything else should be WB. Unfortunately, programming the inverse (ie.
773 // keeping the default UC, and configuring the complement set of the above as
774 // WB) is not reliable in general, because the end of the upper RAM can have
775 // practically any alignment, and we may not have enough variable MTRRs to
778 if (IsMtrrSupported ()) {
779 MtrrGetAllMtrrs (&MtrrSettings
);
782 // MTRRs disabled, fixed MTRRs disabled, default type is uncached
784 ASSERT ((MtrrSettings
.MtrrDefType
& BIT11
) == 0);
785 ASSERT ((MtrrSettings
.MtrrDefType
& BIT10
) == 0);
786 ASSERT ((MtrrSettings
.MtrrDefType
& 0xFF) == 0);
789 // flip default type to writeback
791 SetMem (&MtrrSettings
.Fixed
, sizeof MtrrSettings
.Fixed
, 0x06);
792 ZeroMem (&MtrrSettings
.Variables
, sizeof MtrrSettings
.Variables
);
793 MtrrSettings
.MtrrDefType
|= BIT11
| BIT10
| 6;
794 MtrrSetAllMtrrs (&MtrrSettings
);
797 // Set memory range from 640KB to 1MB to uncacheable
799 Status
= MtrrSetMemoryAttribute (BASE_512KB
+ BASE_128KB
,
800 BASE_1MB
- (BASE_512KB
+ BASE_128KB
), CacheUncacheable
);
801 ASSERT_EFI_ERROR (Status
);
804 // Set the memory range from the start of the 32-bit MMIO area (32-bit PCI
805 // MMIO aperture on i440fx, PCIEXBAR on q35) to 4GB as uncacheable.
807 Status
= MtrrSetMemoryAttribute (mQemuUc32Base
, SIZE_4GB
- mQemuUc32Base
,
809 ASSERT_EFI_ERROR (Status
);
814 Publish system RAM and reserve memory regions
818 InitializeRamRegions (
822 QemuInitializeRam ();
824 if (mS3Supported
&& mBootMode
!= BOOT_ON_S3_RESUME
) {
826 // This is the memory range that will be used for PEI on S3 resume
828 BuildMemoryAllocationHob (
829 mS3AcpiReservedMemoryBase
,
830 mS3AcpiReservedMemorySize
,
835 // Cover the initial RAM area used as stack and temporary PEI heap.
837 // This is reserved as ACPI NVS so it can be used on S3 resume.
839 BuildMemoryAllocationHob (
840 PcdGet32 (PcdOvmfSecPeiTempRamBase
),
841 PcdGet32 (PcdOvmfSecPeiTempRamSize
),
846 // SEC stores its table of GUIDed section handlers here.
848 BuildMemoryAllocationHob (
849 PcdGet64 (PcdGuidedExtractHandlerTableAddress
),
850 PcdGet32 (PcdGuidedExtractHandlerTableSize
),
856 // Reserve the initial page tables built by the reset vector code.
858 // Since this memory range will be used by the Reset Vector on S3
859 // resume, it must be reserved as ACPI NVS.
861 BuildMemoryAllocationHob (
862 (EFI_PHYSICAL_ADDRESS
)(UINTN
) PcdGet32 (PcdOvmfSecPageTablesBase
),
863 (UINT64
)(UINTN
) PcdGet32 (PcdOvmfSecPageTablesSize
),
867 if (MemEncryptSevEsIsEnabled ()) {
869 // If SEV-ES is enabled, reserve the GHCB-related memory area. This
870 // includes the extra page table used to break down the 2MB page
871 // mapping into 4KB page entries where the GHCB resides and the
874 // Since this memory range will be used by the Reset Vector on S3
875 // resume, it must be reserved as ACPI NVS.
877 BuildMemoryAllocationHob (
878 (EFI_PHYSICAL_ADDRESS
)(UINTN
) PcdGet32 (PcdOvmfSecGhcbPageTableBase
),
879 (UINT64
)(UINTN
) PcdGet32 (PcdOvmfSecGhcbPageTableSize
),
882 BuildMemoryAllocationHob (
883 (EFI_PHYSICAL_ADDRESS
)(UINTN
) PcdGet32 (PcdOvmfSecGhcbBase
),
884 (UINT64
)(UINTN
) PcdGet32 (PcdOvmfSecGhcbSize
),
887 BuildMemoryAllocationHob (
888 (EFI_PHYSICAL_ADDRESS
)(UINTN
) PcdGet32 (PcdOvmfSecGhcbBackupBase
),
889 (UINT64
)(UINTN
) PcdGet32 (PcdOvmfSecGhcbBackupSize
),
896 if (mBootMode
!= BOOT_ON_S3_RESUME
) {
897 if (!FeaturePcdGet (PcdSmmSmramRequire
)) {
899 // Reserve the lock box storage area
901 // Since this memory range will be used on S3 resume, it must be
902 // reserved as ACPI NVS.
904 // If S3 is unsupported, then various drivers might still write to the
905 // LockBox area. We ought to prevent DXE from serving allocation requests
906 // such that they would overlap the LockBox storage.
909 (VOID
*)(UINTN
) PcdGet32 (PcdOvmfLockBoxStorageBase
),
910 (UINTN
) PcdGet32 (PcdOvmfLockBoxStorageSize
)
912 BuildMemoryAllocationHob (
913 (EFI_PHYSICAL_ADDRESS
)(UINTN
) PcdGet32 (PcdOvmfLockBoxStorageBase
),
914 (UINT64
)(UINTN
) PcdGet32 (PcdOvmfLockBoxStorageSize
),
915 mS3Supported
? EfiACPIMemoryNVS
: EfiBootServicesData
919 if (FeaturePcdGet (PcdSmmSmramRequire
)) {
923 // Make sure the TSEG area that we reported as a reserved memory resource
924 // cannot be used for reserved memory allocations.
926 TsegSize
= mQ35TsegMbytes
* SIZE_1MB
;
927 BuildMemoryAllocationHob (
928 GetSystemMemorySizeBelow4gb() - TsegSize
,
930 EfiReservedMemoryType
933 // Similarly, allocate away the (already reserved) SMRAM at the default
934 // SMBASE, if it exists.
936 if (mQ35SmramAtDefaultSmbase
) {
937 BuildMemoryAllocationHob (
939 MCH_DEFAULT_SMBASE_SIZE
,
940 EfiReservedMemoryType
946 if (FixedPcdGet32 (PcdOvmfWorkAreaSize
) != 0) {
948 // Reserve the work area.
950 // Since this memory range will be used by the Reset Vector on S3
951 // resume, it must be reserved as ACPI NVS.
953 // If S3 is unsupported, then various drivers might still write to the
954 // work area. We ought to prevent DXE from serving allocation requests
955 // such that they would overlap the work area.
957 BuildMemoryAllocationHob (
958 (EFI_PHYSICAL_ADDRESS
)(UINTN
) FixedPcdGet32 (PcdOvmfWorkAreaBase
),
959 (UINT64
)(UINTN
) FixedPcdGet32 (PcdOvmfWorkAreaSize
),
960 mS3Supported
? EfiACPIMemoryNVS
: EfiBootServicesData