2 Memory Detection for Virtual Machines.
4 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
14 // The package level header files this module uses
16 #include <IndustryStandard/E820.h>
17 #include <IndustryStandard/I440FxPiix4.h>
18 #include <IndustryStandard/Q35MchIch9.h>
20 #include <Register/Intel/SmramSaveStateMap.h>
23 // The Library classes this module consumes
25 #include <Library/BaseLib.h>
26 #include <Library/BaseMemoryLib.h>
27 #include <Library/DebugLib.h>
28 #include <Library/HobLib.h>
29 #include <Library/IoLib.h>
30 #include <Library/MemEncryptSevLib.h>
31 #include <Library/PcdLib.h>
32 #include <Library/PciLib.h>
33 #include <Library/PeimEntryPoint.h>
34 #include <Library/ResourcePublicationLib.h>
35 #include <Library/MtrrLib.h>
36 #include <Library/QemuFwCfgLib.h>
37 #include <Library/QemuFwCfgSimpleParserLib.h>
42 UINT8 mPhysMemAddressWidth
;
44 STATIC UINT32 mS3AcpiReservedMemoryBase
;
45 STATIC UINT32 mS3AcpiReservedMemorySize
;
47 STATIC UINT16 mQ35TsegMbytes
;
49 BOOLEAN mQ35SmramAtDefaultSmbase
;
54 Q35TsegMbytesInitialization (
58 UINT16 ExtendedTsegMbytes
;
59 RETURN_STATUS PcdStatus
;
61 ASSERT (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
);
64 // Check if QEMU offers an extended TSEG.
66 // This can be seen from writing MCH_EXT_TSEG_MB_QUERY to the MCH_EXT_TSEG_MB
67 // register, and reading back the register.
69 // On a QEMU machine type that does not offer an extended TSEG, the initial
70 // write overwrites whatever value a malicious guest OS may have placed in
71 // the (unimplemented) register, before entering S3 or rebooting.
72 // Subsequently, the read returns MCH_EXT_TSEG_MB_QUERY unchanged.
74 // On a QEMU machine type that offers an extended TSEG, the initial write
75 // triggers an update to the register. Subsequently, the value read back
76 // (which is guaranteed to differ from MCH_EXT_TSEG_MB_QUERY) tells us the
77 // number of megabytes.
79 PciWrite16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB
), MCH_EXT_TSEG_MB_QUERY
);
80 ExtendedTsegMbytes
= PciRead16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB
));
81 if (ExtendedTsegMbytes
== MCH_EXT_TSEG_MB_QUERY
) {
82 mQ35TsegMbytes
= PcdGet16 (PcdQ35TsegMbytes
);
88 "%a: QEMU offers an extended TSEG (%d MB)\n",
92 PcdStatus
= PcdSet16S (PcdQ35TsegMbytes
, ExtendedTsegMbytes
);
93 ASSERT_RETURN_ERROR (PcdStatus
);
94 mQ35TsegMbytes
= ExtendedTsegMbytes
;
99 Q35SmramAtDefaultSmbaseInitialization (
103 RETURN_STATUS PcdStatus
;
105 ASSERT (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
);
107 mQ35SmramAtDefaultSmbase
= FALSE
;
108 if (FeaturePcdGet (PcdCsmEnable
)) {
109 DEBUG ((DEBUG_INFO
, "%a: SMRAM at default SMBASE not checked due to CSM\n",
115 CtlReg
= DRAMC_REGISTER_Q35 (MCH_DEFAULT_SMBASE_CTL
);
116 PciWrite8 (CtlReg
, MCH_DEFAULT_SMBASE_QUERY
);
117 CtlRegVal
= PciRead8 (CtlReg
);
118 mQ35SmramAtDefaultSmbase
= (BOOLEAN
)(CtlRegVal
==
119 MCH_DEFAULT_SMBASE_IN_RAM
);
120 DEBUG ((DEBUG_INFO
, "%a: SMRAM at default SMBASE %a\n", __FUNCTION__
,
121 mQ35SmramAtDefaultSmbase
? "found" : "not found"));
124 PcdStatus
= PcdSetBoolS (PcdQ35SmramAtDefaultSmbase
,
125 mQ35SmramAtDefaultSmbase
);
126 ASSERT_RETURN_ERROR (PcdStatus
);
131 QemuUc32BaseInitialization (
135 UINT32 LowerMemorySize
;
138 if (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
140 // On q35, the 32-bit area that we'll mark as UC, through variable MTRRs,
141 // starts at PcdPciExpressBaseAddress. The platform DSC is responsible for
142 // setting PcdPciExpressBaseAddress such that describing the
143 // [PcdPciExpressBaseAddress, 4GB) range require a very small number of
144 // variable MTRRs (preferably 1 or 2).
146 ASSERT (FixedPcdGet64 (PcdPciExpressBaseAddress
) <= MAX_UINT32
);
147 mQemuUc32Base
= (UINT32
)FixedPcdGet64 (PcdPciExpressBaseAddress
);
151 ASSERT (mHostBridgeDevId
== INTEL_82441_DEVICE_ID
);
153 // On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one
154 // variable MTRR suffices by truncating the size to a whole power of two,
155 // while keeping the end affixed to 4GB. This will round the base up.
157 LowerMemorySize
= GetSystemMemorySizeBelow4gb ();
158 Uc32Size
= GetPowerOfTwo32 ((UINT32
)(SIZE_4GB
- LowerMemorySize
));
159 mQemuUc32Base
= (UINT32
)(SIZE_4GB
- Uc32Size
);
161 // Assuming that LowerMemorySize is at least 1 byte, Uc32Size is at most 2GB.
162 // Therefore mQemuUc32Base is at least 2GB.
164 ASSERT (mQemuUc32Base
>= BASE_2GB
);
166 if (mQemuUc32Base
!= LowerMemorySize
) {
167 DEBUG ((DEBUG_VERBOSE
, "%a: rounded UC32 base from 0x%x up to 0x%x, for "
168 "an UC32 size of 0x%x\n", __FUNCTION__
, LowerMemorySize
, mQemuUc32Base
,
175 Iterate over the RAM entries in QEMU's fw_cfg E820 RAM map that start outside
176 of the 32-bit address range.
178 Find the highest exclusive >=4GB RAM address, or produce memory resource
179 descriptor HOBs for RAM entries that start at or above 4GB.
181 @param[out] MaxAddress If MaxAddress is NULL, then ScanOrAdd64BitE820Ram()
182 produces memory resource descriptor HOBs for RAM
183 entries that start at or above 4GB.
185 Otherwise, MaxAddress holds the highest exclusive
186 >=4GB RAM address on output. If QEMU's fw_cfg E820
187 RAM map contains no RAM entry that starts outside of
188 the 32-bit address range, then MaxAddress is exactly
191 @retval EFI_SUCCESS The fw_cfg E820 RAM map was found and processed.
193 @retval EFI_PROTOCOL_ERROR The RAM map was found, but its size wasn't a
194 whole multiple of sizeof(EFI_E820_ENTRY64). No
195 RAM entry was processed.
197 @return Error codes from QemuFwCfgFindFile(). No RAM
202 ScanOrAdd64BitE820Ram (
203 OUT UINT64
*MaxAddress OPTIONAL
207 FIRMWARE_CONFIG_ITEM FwCfgItem
;
209 EFI_E820_ENTRY64 E820Entry
;
212 Status
= QemuFwCfgFindFile ("etc/e820", &FwCfgItem
, &FwCfgSize
);
213 if (EFI_ERROR (Status
)) {
216 if (FwCfgSize
% sizeof E820Entry
!= 0) {
217 return EFI_PROTOCOL_ERROR
;
220 if (MaxAddress
!= NULL
) {
221 *MaxAddress
= BASE_4GB
;
224 QemuFwCfgSelectItem (FwCfgItem
);
225 for (Processed
= 0; Processed
< FwCfgSize
; Processed
+= sizeof E820Entry
) {
226 QemuFwCfgReadBytes (sizeof E820Entry
, &E820Entry
);
229 "%a: Base=0x%Lx Length=0x%Lx Type=%u\n",
235 if (E820Entry
.Type
== EfiAcpiAddressRangeMemory
&&
236 E820Entry
.BaseAddr
>= BASE_4GB
) {
237 if (MaxAddress
== NULL
) {
242 // Round up the start address, and round down the end address.
244 Base
= ALIGN_VALUE (E820Entry
.BaseAddr
, (UINT64
)EFI_PAGE_SIZE
);
245 End
= (E820Entry
.BaseAddr
+ E820Entry
.Length
) &
246 ~(UINT64
)EFI_PAGE_MASK
;
248 AddMemoryRangeHob (Base
, End
);
251 "%a: AddMemoryRangeHob [0x%Lx, 0x%Lx)\n",
260 Candidate
= E820Entry
.BaseAddr
+ E820Entry
.Length
;
261 if (Candidate
> *MaxAddress
) {
262 *MaxAddress
= Candidate
;
265 "%a: MaxAddress=0x%Lx\n",
278 GetSystemMemorySizeBelow4gb (
286 // CMOS 0x34/0x35 specifies the system memory above 16 MB.
287 // * CMOS(0x35) is the high byte
288 // * CMOS(0x34) is the low byte
289 // * The size is specified in 64kb chunks
290 // * Since this is memory above 16MB, the 16MB must be added
291 // into the calculation to get the total memory size.
294 Cmos0x34
= (UINT8
) CmosRead8 (0x34);
295 Cmos0x35
= (UINT8
) CmosRead8 (0x35);
297 return (UINT32
) (((UINTN
)((Cmos0x35
<< 8) + Cmos0x34
) << 16) + SIZE_16MB
);
303 GetSystemMemorySizeAbove4gb (
310 // CMOS 0x5b-0x5d specifies the system memory above 4GB MB.
311 // * CMOS(0x5d) is the most significant size byte
312 // * CMOS(0x5c) is the middle size byte
313 // * CMOS(0x5b) is the least significant size byte
314 // * The size is specified in 64kb chunks
318 for (CmosIndex
= 0x5d; CmosIndex
>= 0x5b; CmosIndex
--) {
319 Size
= (UINT32
) (Size
<< 8) + (UINT32
) CmosRead8 (CmosIndex
);
322 return LShiftU64 (Size
, 16);
327 Return the highest address that DXE could possibly use, plus one.
335 UINT64 FirstNonAddress
;
336 UINT64 Pci64Base
, Pci64Size
;
337 UINT32 FwCfgPciMmio64Mb
;
339 FIRMWARE_CONFIG_ITEM FwCfgItem
;
341 UINT64 HotPlugMemoryEnd
;
342 RETURN_STATUS PcdStatus
;
345 // set FirstNonAddress to suppress incorrect compiler/analyzer warnings
350 // If QEMU presents an E820 map, then get the highest exclusive >=4GB RAM
351 // address from it. This can express an address >= 4GB+1TB.
353 // Otherwise, get the flat size of the memory above 4GB from the CMOS (which
354 // can only express a size smaller than 1TB), and add it to 4GB.
356 Status
= ScanOrAdd64BitE820Ram (&FirstNonAddress
);
357 if (EFI_ERROR (Status
)) {
358 FirstNonAddress
= BASE_4GB
+ GetSystemMemorySizeAbove4gb ();
362 // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO
363 // resources to 32-bit anyway. See DegradeResource() in
364 // "PciResourceSupport.c".
367 if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode
)) {
368 return FirstNonAddress
;
373 // Otherwise, in order to calculate the highest address plus one, we must
374 // consider the 64-bit PCI host aperture too. Fetch the default size.
376 Pci64Size
= PcdGet64 (PcdPciMmio64Size
);
379 // See if the user specified the number of megabytes for the 64-bit PCI host
380 // aperture. Accept an aperture size up to 16TB.
382 // As signaled by the "X-" prefix, this knob is experimental, and might go
385 Status
= QemuFwCfgParseUint32 ("opt/ovmf/X-PciMmio64Mb", FALSE
,
388 case EFI_UNSUPPORTED
:
392 if (FwCfgPciMmio64Mb
<= 0x1000000) {
393 Pci64Size
= LShiftU64 (FwCfgPciMmio64Mb
, 20);
401 "%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\n",
406 if (Pci64Size
== 0) {
407 if (mBootMode
!= BOOT_ON_S3_RESUME
) {
408 DEBUG ((DEBUG_INFO
, "%a: disabling 64-bit PCI host aperture\n",
410 PcdStatus
= PcdSet64S (PcdPciMmio64Size
, 0);
411 ASSERT_RETURN_ERROR (PcdStatus
);
415 // There's nothing more to do; the amount of memory above 4GB fully
416 // determines the highest address plus one. The memory hotplug area (see
417 // below) plays no role for the firmware in this case.
419 return FirstNonAddress
;
423 // The "etc/reserved-memory-end" fw_cfg file, when present, contains an
424 // absolute, exclusive end address for the memory hotplug area. This area
425 // starts right at the end of the memory above 4GB. The 64-bit PCI host
426 // aperture must be placed above it.
428 Status
= QemuFwCfgFindFile ("etc/reserved-memory-end", &FwCfgItem
,
430 if (!EFI_ERROR (Status
) && FwCfgSize
== sizeof HotPlugMemoryEnd
) {
431 QemuFwCfgSelectItem (FwCfgItem
);
432 QemuFwCfgReadBytes (FwCfgSize
, &HotPlugMemoryEnd
);
433 DEBUG ((DEBUG_VERBOSE
, "%a: HotPlugMemoryEnd=0x%Lx\n", __FUNCTION__
,
436 ASSERT (HotPlugMemoryEnd
>= FirstNonAddress
);
437 FirstNonAddress
= HotPlugMemoryEnd
;
441 // SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB, so
442 // that the host can map it with 1GB hugepages. Follow suit.
444 Pci64Base
= ALIGN_VALUE (FirstNonAddress
, (UINT64
)SIZE_1GB
);
445 Pci64Size
= ALIGN_VALUE (Pci64Size
, (UINT64
)SIZE_1GB
);
448 // The 64-bit PCI host aperture should also be "naturally" aligned. The
449 // alignment is determined by rounding the size of the aperture down to the
450 // next smaller or equal power of two. That is, align the aperture by the
451 // largest BAR size that can fit into it.
453 Pci64Base
= ALIGN_VALUE (Pci64Base
, GetPowerOfTwo64 (Pci64Size
));
455 if (mBootMode
!= BOOT_ON_S3_RESUME
) {
457 // The core PciHostBridgeDxe driver will automatically add this range to
458 // the GCD memory space map through our PciHostBridgeLib instance; here we
459 // only need to set the PCDs.
461 PcdStatus
= PcdSet64S (PcdPciMmio64Base
, Pci64Base
);
462 ASSERT_RETURN_ERROR (PcdStatus
);
463 PcdStatus
= PcdSet64S (PcdPciMmio64Size
, Pci64Size
);
464 ASSERT_RETURN_ERROR (PcdStatus
);
466 DEBUG ((DEBUG_INFO
, "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",
467 __FUNCTION__
, Pci64Base
, Pci64Size
));
471 // The useful address space ends with the 64-bit PCI host aperture.
473 FirstNonAddress
= Pci64Base
+ Pci64Size
;
474 return FirstNonAddress
;
479 Initialize the mPhysMemAddressWidth variable, based on guest RAM size.
482 AddressWidthInitialization (
486 UINT64 FirstNonAddress
;
489 // As guest-physical memory size grows, the permanent PEI RAM requirements
490 // are dominated by the identity-mapping page tables built by the DXE IPL.
491 // The DXL IPL keys off of the physical address bits advertized in the CPU
492 // HOB. To conserve memory, we calculate the minimum address width here.
494 FirstNonAddress
= GetFirstNonAddress ();
495 mPhysMemAddressWidth
= (UINT8
)HighBitSet64 (FirstNonAddress
);
498 // If FirstNonAddress is not an integral power of two, then we need an
501 if ((FirstNonAddress
& (FirstNonAddress
- 1)) != 0) {
502 ++mPhysMemAddressWidth
;
506 // The minimum address width is 36 (covers up to and excluding 64 GB, which
507 // is the maximum for Ia32 + PAE). The theoretical architecture maximum for
508 // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We
509 // can simply assert that here, since 48 bits are good enough for 256 TB.
511 if (mPhysMemAddressWidth
<= 36) {
512 mPhysMemAddressWidth
= 36;
514 ASSERT (mPhysMemAddressWidth
<= 48);
519 Calculate the cap for the permanent PEI memory.
527 BOOLEAN Page1GSupport
;
535 // If DXE is 32-bit, then just return the traditional 64 MB cap.
538 if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode
)) {
544 // Dependent on physical address width, PEI memory allocations can be
545 // dominated by the page tables built for 64-bit DXE. So we key the cap off
546 // of those. The code below is based on CreateIdentityMappingPageTables() in
547 // "MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c".
549 Page1GSupport
= FALSE
;
550 if (PcdGetBool (PcdUse1GPageTable
)) {
551 AsmCpuid (0x80000000, &RegEax
, NULL
, NULL
, NULL
);
552 if (RegEax
>= 0x80000001) {
553 AsmCpuid (0x80000001, NULL
, NULL
, NULL
, &RegEdx
);
554 if ((RegEdx
& BIT26
) != 0) {
555 Page1GSupport
= TRUE
;
560 if (mPhysMemAddressWidth
<= 39) {
562 PdpEntries
= 1 << (mPhysMemAddressWidth
- 30);
563 ASSERT (PdpEntries
<= 0x200);
565 Pml4Entries
= 1 << (mPhysMemAddressWidth
- 39);
566 ASSERT (Pml4Entries
<= 0x200);
570 TotalPages
= Page1GSupport
? Pml4Entries
+ 1 :
571 (PdpEntries
+ 1) * Pml4Entries
+ 1;
572 ASSERT (TotalPages
<= 0x40201);
575 // Add 64 MB for miscellaneous allocations. Note that for
576 // mPhysMemAddressWidth values close to 36, the cap will actually be
577 // dominated by this increment.
579 return (UINT32
)(EFI_PAGES_TO_SIZE (TotalPages
) + SIZE_64MB
);
584 Publish PEI core memory
586 @return EFI_SUCCESS The PEIM initialized successfully.
595 EFI_PHYSICAL_ADDRESS MemoryBase
;
597 UINT32 LowerMemorySize
;
600 LowerMemorySize
= GetSystemMemorySizeBelow4gb ();
601 if (FeaturePcdGet (PcdSmmSmramRequire
)) {
603 // TSEG is chipped from the end of low RAM
605 LowerMemorySize
-= mQ35TsegMbytes
* SIZE_1MB
;
609 // If S3 is supported, then the S3 permanent PEI memory is placed next,
610 // downwards. Its size is primarily dictated by CpuMpPei. The formula below
611 // is an approximation.
614 mS3AcpiReservedMemorySize
= SIZE_512KB
+
616 PcdGet32 (PcdCpuApStackSize
);
617 mS3AcpiReservedMemoryBase
= LowerMemorySize
- mS3AcpiReservedMemorySize
;
618 LowerMemorySize
= mS3AcpiReservedMemoryBase
;
621 if (mBootMode
== BOOT_ON_S3_RESUME
) {
622 MemoryBase
= mS3AcpiReservedMemoryBase
;
623 MemorySize
= mS3AcpiReservedMemorySize
;
625 PeiMemoryCap
= GetPeiMemoryCap ();
626 DEBUG ((DEBUG_INFO
, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",
627 __FUNCTION__
, mPhysMemAddressWidth
, PeiMemoryCap
>> 10));
630 // Determine the range of memory to use during PEI
632 // Technically we could lay the permanent PEI RAM over SEC's temporary
633 // decompression and scratch buffer even if "secure S3" is needed, since
634 // their lifetimes don't overlap. However, PeiFvInitialization() will cover
635 // RAM up to PcdOvmfDecompressionScratchEnd with an EfiACPIMemoryNVS memory
636 // allocation HOB, and other allocations served from the permanent PEI RAM
637 // shouldn't overlap with that HOB.
639 MemoryBase
= mS3Supported
&& FeaturePcdGet (PcdSmmSmramRequire
) ?
640 PcdGet32 (PcdOvmfDecompressionScratchEnd
) :
641 PcdGet32 (PcdOvmfDxeMemFvBase
) + PcdGet32 (PcdOvmfDxeMemFvSize
);
642 MemorySize
= LowerMemorySize
- MemoryBase
;
643 if (MemorySize
> PeiMemoryCap
) {
644 MemoryBase
= LowerMemorySize
- PeiMemoryCap
;
645 MemorySize
= PeiMemoryCap
;
650 // MEMFD_BASE_ADDRESS separates the SMRAM at the default SMBASE from the
651 // normal boot permanent PEI RAM. Regarding the S3 boot path, the S3
652 // permanent PEI RAM is located even higher.
654 if (FeaturePcdGet (PcdSmmSmramRequire
) && mQ35SmramAtDefaultSmbase
) {
655 ASSERT (SMM_DEFAULT_SMBASE
+ MCH_DEFAULT_SMBASE_SIZE
<= MemoryBase
);
659 // Publish this memory to the PEI Core
661 Status
= PublishSystemMemory(MemoryBase
, MemorySize
);
662 ASSERT_EFI_ERROR (Status
);
670 QemuInitializeRamBelow1gb (
674 if (FeaturePcdGet (PcdSmmSmramRequire
) && mQ35SmramAtDefaultSmbase
) {
675 AddMemoryRangeHob (0, SMM_DEFAULT_SMBASE
);
676 AddReservedMemoryBaseSizeHob (SMM_DEFAULT_SMBASE
, MCH_DEFAULT_SMBASE_SIZE
,
677 TRUE
/* Cacheable */);
679 SMM_DEFAULT_SMBASE
+ MCH_DEFAULT_SMBASE_SIZE
< BASE_512KB
+ BASE_128KB
,
680 "end of SMRAM at default SMBASE ends at, or exceeds, 640KB"
682 AddMemoryRangeHob (SMM_DEFAULT_SMBASE
+ MCH_DEFAULT_SMBASE_SIZE
,
683 BASE_512KB
+ BASE_128KB
);
685 AddMemoryRangeHob (0, BASE_512KB
+ BASE_128KB
);
691 Peform Memory Detection for QEMU / KVM
700 UINT64 LowerMemorySize
;
701 UINT64 UpperMemorySize
;
702 MTRR_SETTINGS MtrrSettings
;
705 DEBUG ((DEBUG_INFO
, "%a called\n", __FUNCTION__
));
708 // Determine total memory size available
710 LowerMemorySize
= GetSystemMemorySizeBelow4gb ();
711 UpperMemorySize
= GetSystemMemorySizeAbove4gb ();
713 if (mBootMode
== BOOT_ON_S3_RESUME
) {
715 // Create the following memory HOB as an exception on the S3 boot path.
717 // Normally we'd create memory HOBs only on the normal boot path. However,
718 // CpuMpPei specifically needs such a low-memory HOB on the S3 path as
719 // well, for "borrowing" a subset of it temporarily, for the AP startup
722 // CpuMpPei saves the original contents of the borrowed area in permanent
723 // PEI RAM, in a backup buffer allocated with the normal PEI services.
724 // CpuMpPei restores the original contents ("returns" the borrowed area) at
725 // End-of-PEI. End-of-PEI in turn is emitted by S3Resume2Pei before
726 // transferring control to the OS's wakeup vector in the FACS.
728 // We expect any other PEIMs that "borrow" memory similarly to CpuMpPei to
729 // restore the original contents. Furthermore, we expect all such PEIMs
730 // (CpuMpPei included) to claim the borrowed areas by producing memory
731 // allocation HOBs, and to honor preexistent memory allocation HOBs when
732 // looking for an area to borrow.
734 QemuInitializeRamBelow1gb ();
737 // Create memory HOBs
739 QemuInitializeRamBelow1gb ();
741 if (FeaturePcdGet (PcdSmmSmramRequire
)) {
744 TsegSize
= mQ35TsegMbytes
* SIZE_1MB
;
745 AddMemoryRangeHob (BASE_1MB
, LowerMemorySize
- TsegSize
);
746 AddReservedMemoryBaseSizeHob (LowerMemorySize
- TsegSize
, TsegSize
,
749 AddMemoryRangeHob (BASE_1MB
, LowerMemorySize
);
753 // If QEMU presents an E820 map, then create memory HOBs for the >=4GB RAM
754 // entries. Otherwise, create a single memory HOB with the flat >=4GB
755 // memory size read from the CMOS.
757 Status
= ScanOrAdd64BitE820Ram (NULL
);
758 if (EFI_ERROR (Status
) && UpperMemorySize
!= 0) {
759 AddMemoryBaseSizeHob (BASE_4GB
, UpperMemorySize
);
764 // We'd like to keep the following ranges uncached:
766 // - [LowerMemorySize, 4 GB)
768 // Everything else should be WB. Unfortunately, programming the inverse (ie.
769 // keeping the default UC, and configuring the complement set of the above as
770 // WB) is not reliable in general, because the end of the upper RAM can have
771 // practically any alignment, and we may not have enough variable MTRRs to
774 if (IsMtrrSupported ()) {
775 MtrrGetAllMtrrs (&MtrrSettings
);
778 // MTRRs disabled, fixed MTRRs disabled, default type is uncached
780 ASSERT ((MtrrSettings
.MtrrDefType
& BIT11
) == 0);
781 ASSERT ((MtrrSettings
.MtrrDefType
& BIT10
) == 0);
782 ASSERT ((MtrrSettings
.MtrrDefType
& 0xFF) == 0);
785 // flip default type to writeback
787 SetMem (&MtrrSettings
.Fixed
, sizeof MtrrSettings
.Fixed
, 0x06);
788 ZeroMem (&MtrrSettings
.Variables
, sizeof MtrrSettings
.Variables
);
789 MtrrSettings
.MtrrDefType
|= BIT11
| BIT10
| 6;
790 MtrrSetAllMtrrs (&MtrrSettings
);
793 // Set memory range from 640KB to 1MB to uncacheable
795 Status
= MtrrSetMemoryAttribute (BASE_512KB
+ BASE_128KB
,
796 BASE_1MB
- (BASE_512KB
+ BASE_128KB
), CacheUncacheable
);
797 ASSERT_EFI_ERROR (Status
);
800 // Set the memory range from the start of the 32-bit MMIO area (32-bit PCI
801 // MMIO aperture on i440fx, PCIEXBAR on q35) to 4GB as uncacheable.
803 Status
= MtrrSetMemoryAttribute (mQemuUc32Base
, SIZE_4GB
- mQemuUc32Base
,
805 ASSERT_EFI_ERROR (Status
);
810 Publish system RAM and reserve memory regions
814 InitializeRamRegions (
818 QemuInitializeRam ();
820 if (mS3Supported
&& mBootMode
!= BOOT_ON_S3_RESUME
) {
822 // This is the memory range that will be used for PEI on S3 resume
824 BuildMemoryAllocationHob (
825 mS3AcpiReservedMemoryBase
,
826 mS3AcpiReservedMemorySize
,
831 // Cover the initial RAM area used as stack and temporary PEI heap.
833 // This is reserved as ACPI NVS so it can be used on S3 resume.
835 BuildMemoryAllocationHob (
836 PcdGet32 (PcdOvmfSecPeiTempRamBase
),
837 PcdGet32 (PcdOvmfSecPeiTempRamSize
),
842 // SEC stores its table of GUIDed section handlers here.
844 BuildMemoryAllocationHob (
845 PcdGet64 (PcdGuidedExtractHandlerTableAddress
),
846 PcdGet32 (PcdGuidedExtractHandlerTableSize
),
852 // Reserve the initial page tables built by the reset vector code.
854 // Since this memory range will be used by the Reset Vector on S3
855 // resume, it must be reserved as ACPI NVS.
857 BuildMemoryAllocationHob (
858 (EFI_PHYSICAL_ADDRESS
)(UINTN
) PcdGet32 (PcdOvmfSecPageTablesBase
),
859 (UINT64
)(UINTN
) PcdGet32 (PcdOvmfSecPageTablesSize
),
863 if (MemEncryptSevEsIsEnabled ()) {
865 // If SEV-ES is enabled, reserve the GHCB-related memory area. This
866 // includes the extra page table used to break down the 2MB page
867 // mapping into 4KB page entries where the GHCB resides and the
870 // Since this memory range will be used by the Reset Vector on S3
871 // resume, it must be reserved as ACPI NVS.
873 BuildMemoryAllocationHob (
874 (EFI_PHYSICAL_ADDRESS
)(UINTN
) PcdGet32 (PcdOvmfSecGhcbPageTableBase
),
875 (UINT64
)(UINTN
) PcdGet32 (PcdOvmfSecGhcbPageTableSize
),
878 BuildMemoryAllocationHob (
879 (EFI_PHYSICAL_ADDRESS
)(UINTN
) PcdGet32 (PcdOvmfSecGhcbBase
),
880 (UINT64
)(UINTN
) PcdGet32 (PcdOvmfSecGhcbSize
),
883 BuildMemoryAllocationHob (
884 (EFI_PHYSICAL_ADDRESS
)(UINTN
) PcdGet32 (PcdOvmfSecGhcbBackupBase
),
885 (UINT64
)(UINTN
) PcdGet32 (PcdOvmfSecGhcbBackupSize
),
892 if (mBootMode
!= BOOT_ON_S3_RESUME
) {
893 if (!FeaturePcdGet (PcdSmmSmramRequire
)) {
895 // Reserve the lock box storage area
897 // Since this memory range will be used on S3 resume, it must be
898 // reserved as ACPI NVS.
900 // If S3 is unsupported, then various drivers might still write to the
901 // LockBox area. We ought to prevent DXE from serving allocation requests
902 // such that they would overlap the LockBox storage.
905 (VOID
*)(UINTN
) PcdGet32 (PcdOvmfLockBoxStorageBase
),
906 (UINTN
) PcdGet32 (PcdOvmfLockBoxStorageSize
)
908 BuildMemoryAllocationHob (
909 (EFI_PHYSICAL_ADDRESS
)(UINTN
) PcdGet32 (PcdOvmfLockBoxStorageBase
),
910 (UINT64
)(UINTN
) PcdGet32 (PcdOvmfLockBoxStorageSize
),
911 mS3Supported
? EfiACPIMemoryNVS
: EfiBootServicesData
915 if (FeaturePcdGet (PcdSmmSmramRequire
)) {
919 // Make sure the TSEG area that we reported as a reserved memory resource
920 // cannot be used for reserved memory allocations.
922 TsegSize
= mQ35TsegMbytes
* SIZE_1MB
;
923 BuildMemoryAllocationHob (
924 GetSystemMemorySizeBelow4gb() - TsegSize
,
926 EfiReservedMemoryType
929 // Similarly, allocate away the (already reserved) SMRAM at the default
930 // SMBASE, if it exists.
932 if (mQ35SmramAtDefaultSmbase
) {
933 BuildMemoryAllocationHob (
935 MCH_DEFAULT_SMBASE_SIZE
,
936 EfiReservedMemoryType
942 if (MemEncryptSevEsIsEnabled ()) {
944 // If SEV-ES is enabled, reserve the SEV-ES work area.
946 // Since this memory range will be used by the Reset Vector on S3
947 // resume, it must be reserved as ACPI NVS.
949 // If S3 is unsupported, then various drivers might still write to the
950 // work area. We ought to prevent DXE from serving allocation requests
951 // such that they would overlap the work area.
953 BuildMemoryAllocationHob (
954 (EFI_PHYSICAL_ADDRESS
)(UINTN
) FixedPcdGet32 (PcdSevEsWorkAreaBase
),
955 (UINT64
)(UINTN
) FixedPcdGet32 (PcdSevEsWorkAreaSize
),
956 mS3Supported
? EfiACPIMemoryNVS
: EfiBootServicesData