4 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
5 Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 // The package level header files this module uses
23 // The Library classes this module consumes
25 #include <Library/BaseLib.h>
26 #include <Library/DebugLib.h>
27 #include <Library/HobLib.h>
28 #include <Library/IoLib.h>
29 #include <Library/MemoryAllocationLib.h>
30 #include <Library/PcdLib.h>
31 #include <Library/PciLib.h>
32 #include <Library/PeimEntryPoint.h>
33 #include <Library/PeiServicesLib.h>
34 #include <Library/QemuFwCfgLib.h>
35 #include <Library/QemuFwCfgS3Lib.h>
36 #include <Library/ResourcePublicationLib.h>
37 #include <Guid/MemoryTypeInformation.h>
38 #include <Ppi/MasterBootMode.h>
39 #include <IndustryStandard/Pci22.h>
40 #include <OvmfPlatforms.h>
45 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation
[] = {
46 { EfiACPIMemoryNVS
, 0x004 },
47 { EfiACPIReclaimMemory
, 0x008 },
48 { EfiReservedMemoryType
, 0x004 },
49 { EfiRuntimeServicesData
, 0x024 },
50 { EfiRuntimeServicesCode
, 0x030 },
51 { EfiBootServicesCode
, 0x180 },
52 { EfiBootServicesData
, 0xF00 },
53 { EfiMaxMemoryType
, 0x000 }
57 EFI_PEI_PPI_DESCRIPTOR mPpiBootMode
[] = {
59 EFI_PEI_PPI_DESCRIPTOR_PPI
| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST
,
60 &gEfiPeiMasterBootModePpiGuid
,
66 UINT16 mHostBridgeDevId
;
68 EFI_BOOT_MODE mBootMode
= BOOT_WITH_FULL_CONFIGURATION
;
70 BOOLEAN mS3Supported
= FALSE
;
75 AddIoMemoryBaseSizeHob (
76 EFI_PHYSICAL_ADDRESS MemoryBase
,
80 BuildResourceDescriptorHob (
81 EFI_RESOURCE_MEMORY_MAPPED_IO
,
82 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
83 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
84 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
85 EFI_RESOURCE_ATTRIBUTE_TESTED
,
92 AddReservedMemoryBaseSizeHob (
93 EFI_PHYSICAL_ADDRESS MemoryBase
,
98 BuildResourceDescriptorHob (
99 EFI_RESOURCE_MEMORY_RESERVED
,
100 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
101 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
102 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
104 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE
|
105 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE
|
106 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
:
109 EFI_RESOURCE_ATTRIBUTE_TESTED
,
116 AddIoMemoryRangeHob (
117 EFI_PHYSICAL_ADDRESS MemoryBase
,
118 EFI_PHYSICAL_ADDRESS MemoryLimit
121 AddIoMemoryBaseSizeHob (MemoryBase
, (UINT64
)(MemoryLimit
- MemoryBase
));
126 AddMemoryBaseSizeHob (
127 EFI_PHYSICAL_ADDRESS MemoryBase
,
131 BuildResourceDescriptorHob (
132 EFI_RESOURCE_SYSTEM_MEMORY
,
133 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
134 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
135 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
136 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE
|
137 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE
|
138 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
|
139 EFI_RESOURCE_ATTRIBUTE_TESTED
,
148 EFI_PHYSICAL_ADDRESS MemoryBase
,
149 EFI_PHYSICAL_ADDRESS MemoryLimit
152 AddMemoryBaseSizeHob (MemoryBase
, (UINT64
)(MemoryLimit
- MemoryBase
));
157 MemMapInitialization (
163 RETURN_STATUS PcdStatus
;
169 // Create Memory Type Information HOB
172 &gEfiMemoryTypeInformationGuid
,
173 mDefaultMemoryTypeInformation
,
174 sizeof(mDefaultMemoryTypeInformation
)
178 // Video memory + Legacy BIOS region
180 AddIoMemoryRangeHob (0x0A0000, BASE_1MB
);
188 TopOfLowRam
= GetSystemMemorySizeBelow4gb ();
190 if (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
192 // The MMCONFIG area is expected to fall between the top of low RAM and
193 // the base of the 32-bit PCI host aperture.
195 PciExBarBase
= FixedPcdGet64 (PcdPciExpressBaseAddress
);
196 ASSERT (TopOfLowRam
<= PciExBarBase
);
197 ASSERT (PciExBarBase
<= MAX_UINT32
- SIZE_256MB
);
198 PciBase
= (UINT32
)(PciExBarBase
+ SIZE_256MB
);
200 PciBase
= (TopOfLowRam
< BASE_2GB
) ? BASE_2GB
: TopOfLowRam
;
204 // address purpose size
205 // ------------ -------- -------------------------
206 // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)
207 // 0xFC000000 gap 44 MB
208 // 0xFEC00000 IO-APIC 4 KB
209 // 0xFEC01000 gap 1020 KB
210 // 0xFED00000 HPET 1 KB
211 // 0xFED00400 gap 111 KB
212 // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB
213 // 0xFED20000 gap 896 KB
214 // 0xFEE00000 LAPIC 1 MB
216 PciSize
= 0xFC000000 - PciBase
;
217 AddIoMemoryBaseSizeHob (PciBase
, PciSize
);
218 PcdStatus
= PcdSet64S (PcdPciMmio32Base
, PciBase
);
219 ASSERT_RETURN_ERROR (PcdStatus
);
220 PcdStatus
= PcdSet64S (PcdPciMmio32Size
, PciSize
);
221 ASSERT_RETURN_ERROR (PcdStatus
);
223 AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB
);
224 AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB
);
225 if (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
226 AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE
, SIZE_16KB
);
228 // Note: there should be an
230 // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
232 // call below, just like the one above for RCBA. However, Linux insists
233 // that the MMCONFIG area be marked in the E820 or UEFI memory map as
234 // "reserved memory" -- Linux does not content itself with a simple gap
235 // in the memory map wherever the MCFG ACPI table points to.
237 // This appears to be a safety measure. The PCI Firmware Specification
238 // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
239 // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
240 // [...]". (Emphasis added here.)
242 // Normally we add memory resource descriptor HOBs in
243 // QemuInitializeRam(), and pre-allocate from those with memory
244 // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
245 // is most definitely not RAM; so, as an exception, cover it with
246 // uncacheable reserved memory right here.
248 AddReservedMemoryBaseSizeHob (PciExBarBase
, SIZE_256MB
, FALSE
);
249 BuildMemoryAllocationHob (PciExBarBase
, SIZE_256MB
,
250 EfiReservedMemoryType
);
252 AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress
), SIZE_1MB
);
255 // On Q35, the IO Port space is available for PCI resource allocations from
258 if (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
261 ASSERT ((ICH9_PMBASE_VALUE
& 0xF000) < PciIoBase
);
266 // Add PCI IO Port space available for PCI resource allocations.
268 BuildResourceDescriptorHob (
270 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
271 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
,
275 PcdStatus
= PcdSet64S (PcdPciIoBase
, PciIoBase
);
276 ASSERT_RETURN_ERROR (PcdStatus
);
277 PcdStatus
= PcdSet64S (PcdPciIoSize
, PciIoSize
);
278 ASSERT_RETURN_ERROR (PcdStatus
);
282 GetNamedFwCfgBoolean (
283 IN CHAR8
*FwCfgFileName
,
288 FIRMWARE_CONFIG_ITEM FwCfgItem
;
292 Status
= QemuFwCfgFindFile (FwCfgFileName
, &FwCfgItem
, &FwCfgSize
);
293 if (EFI_ERROR (Status
)) {
296 if (FwCfgSize
> sizeof Value
) {
297 return EFI_BAD_BUFFER_SIZE
;
299 QemuFwCfgSelectItem (FwCfgItem
);
300 QemuFwCfgReadBytes (FwCfgSize
, Value
);
302 if ((FwCfgSize
== 1) ||
303 (FwCfgSize
== 2 && Value
[1] == '\n') ||
304 (FwCfgSize
== 3 && Value
[1] == '\r' && Value
[2] == '\n')) {
322 return EFI_PROTOCOL_ERROR
;
325 #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \
328 RETURN_STATUS PcdStatus; \
330 if (!EFI_ERROR (GetNamedFwCfgBoolean ( \
331 "opt/ovmf/" #TokenName, &Setting))) { \
332 PcdStatus = PcdSetBoolS (TokenName, Setting); \
333 ASSERT_RETURN_ERROR (PcdStatus); \
338 NoexecDxeInitialization (
342 UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable
);
343 UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack
);
347 PciExBarInitialization (
357 // We only support the 256MB size for the MMCONFIG area:
358 // 256 buses * 32 devices * 8 functions * 4096 bytes config space.
360 // The masks used below enforce the Q35 requirements that the MMCONFIG area
361 // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.
363 // Note that (b) also ensures that the minimum address width we have
364 // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice
365 // for DXE's page tables to cover the MMCONFIG area.
367 PciExBarBase
.Uint64
= FixedPcdGet64 (PcdPciExpressBaseAddress
);
368 ASSERT ((PciExBarBase
.Uint32
[1] & MCH_PCIEXBAR_HIGHMASK
) == 0);
369 ASSERT ((PciExBarBase
.Uint32
[0] & MCH_PCIEXBAR_LOWMASK
) == 0);
372 // Clear the PCIEXBAREN bit first, before programming the high register.
374 PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW
), 0);
377 // Program the high register. Then program the low register, setting the
378 // MMCONFIG area size and enabling decoding at once.
380 PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH
), PciExBarBase
.Uint32
[1]);
382 DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW
),
383 PciExBarBase
.Uint32
[0] | MCH_PCIEXBAR_BUS_FF
| MCH_PCIEXBAR_EN
398 RETURN_STATUS PcdStatus
;
406 // Build the CPU HOB with guest RAM size dependent address width and 16-bits
407 // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
408 // S3 resume as well, so we build it unconditionally.)
410 BuildCpuHob (mPhysMemAddressWidth
, 16);
413 // Determine platform type and save Host Bridge DID to PCD
415 switch (mHostBridgeDevId
) {
416 case INTEL_82441_DEVICE_ID
:
417 PmCmd
= POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET
);
418 Pmba
= POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA
);
419 PmbaAndVal
= ~(UINT32
)PIIX4_PMBA_MASK
;
420 PmbaOrVal
= PIIX4_PMBA_VALUE
;
421 AcpiCtlReg
= POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC
);
422 AcpiEnBit
= PIIX4_PMREGMISC_PMIOSE
;
424 case INTEL_Q35_MCH_DEVICE_ID
:
425 PmCmd
= POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET
);
426 Pmba
= POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE
);
427 PmbaAndVal
= ~(UINT32
)ICH9_PMBASE_MASK
;
428 PmbaOrVal
= ICH9_PMBASE_VALUE
;
429 AcpiCtlReg
= POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL
);
430 AcpiEnBit
= ICH9_ACPI_CNTL_ACPI_EN
;
433 DEBUG ((EFI_D_ERROR
, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
434 __FUNCTION__
, mHostBridgeDevId
));
438 PcdStatus
= PcdSet16S (PcdOvmfHostBridgePciDevId
, mHostBridgeDevId
);
439 ASSERT_RETURN_ERROR (PcdStatus
);
442 // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
443 // has been configured (e.g., by Xen) and skip the setup here.
444 // This matches the logic in AcpiTimerLibConstructor ().
446 if ((PciRead8 (AcpiCtlReg
) & AcpiEnBit
) == 0) {
448 // The PEI phase should be exited with fully accessibe ACPI PM IO space:
451 PciAndThenOr32 (Pmba
, PmbaAndVal
, PmbaOrVal
);
454 // 2. set PCICMD/IOSE
456 PciOr8 (PmCmd
, EFI_PCI_COMMAND_IO_SPACE
);
459 // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
461 PciOr8 (AcpiCtlReg
, AcpiEnBit
);
464 if (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
466 // Set Root Complex Register Block BAR
469 POWER_MGMT_REGISTER_Q35 (ICH9_RCBA
),
470 ICH9_ROOT_COMPLEX_BASE
| ICH9_RCBA_EN
474 // Set PCI Express Register Range Base Address
476 PciExBarInitialization ();
482 BootModeInitialization (
488 if (CmosRead8 (0xF) == 0xFE) {
489 mBootMode
= BOOT_ON_S3_RESUME
;
491 CmosWrite8 (0xF, 0x00);
493 Status
= PeiServicesSetBootMode (mBootMode
);
494 ASSERT_EFI_ERROR (Status
);
496 Status
= PeiServicesInstallPpi (mPpiBootMode
);
497 ASSERT_EFI_ERROR (Status
);
502 ReserveEmuVariableNvStore (
505 EFI_PHYSICAL_ADDRESS VariableStore
;
506 RETURN_STATUS PcdStatus
;
509 // Allocate storage for NV variables early on so it will be
510 // at a consistent address. Since VM memory is preserved
511 // across reboots, this allows the NV variable storage to survive
515 (EFI_PHYSICAL_ADDRESS
)(UINTN
)
516 AllocateRuntimePages (
517 EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize
))
520 "Reserved variable store memory: 0x%lX; size: %dkb\n",
522 (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize
)) / 1024
524 PcdStatus
= PcdSet64S (PcdEmuVariableNvStoreReserved
, VariableStore
);
525 ASSERT_RETURN_ERROR (PcdStatus
);
536 DEBUG ((EFI_D_INFO
, "CMOS:\n"));
538 for (Loop
= 0; Loop
< 0x80; Loop
++) {
539 if ((Loop
% 0x10) == 0) {
540 DEBUG ((EFI_D_INFO
, "%02x:", Loop
));
542 DEBUG ((EFI_D_INFO
, " %02x", CmosRead8 (Loop
)));
543 if ((Loop
% 0x10) == 0xf) {
544 DEBUG ((EFI_D_INFO
, "\n"));
555 #if defined (MDE_CPU_X64)
556 if (FeaturePcdGet (PcdSmmSmramRequire
) && mS3Supported
) {
558 "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__
));
560 "%a: Please disable S3 on the QEMU command line (see the README),\n",
563 "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__
));
572 Fetch the number of boot CPUs from QEMU and expose it to UefiCpuPkg modules.
573 Set the mMaxCpuCount variable.
576 MaxCpuCountInitialization (
580 UINT16 ProcessorCount
;
581 RETURN_STATUS PcdStatus
;
583 QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount
);
584 ProcessorCount
= QemuFwCfgRead16 ();
586 // If the fw_cfg key or fw_cfg entirely is unavailable, load mMaxCpuCount
587 // from the PCD default. No change to PCDs.
589 if (ProcessorCount
== 0) {
590 mMaxCpuCount
= PcdGet32 (PcdCpuMaxLogicalProcessorNumber
);
594 // Otherwise, set mMaxCpuCount to the value reported by QEMU.
596 mMaxCpuCount
= ProcessorCount
;
598 // Additionally, tell UefiCpuPkg modules (a) the exact number of VCPUs, (b)
599 // to wait, in the initial AP bringup, exactly as long as it takes for all of
600 // the APs to report in. For this, we set the longest representable timeout
601 // (approx. 71 minutes).
603 PcdStatus
= PcdSet32S (PcdCpuMaxLogicalProcessorNumber
, ProcessorCount
);
604 ASSERT_RETURN_ERROR (PcdStatus
);
605 PcdStatus
= PcdSet32S (PcdCpuApInitTimeOutInMicroSeconds
, MAX_UINT32
);
606 ASSERT_RETURN_ERROR (PcdStatus
);
607 DEBUG ((DEBUG_INFO
, "%a: QEMU reports %d processor(s)\n", __FUNCTION__
,
613 Perform Platform PEI initialization.
615 @param FileHandle Handle of the file being invoked.
616 @param PeiServices Describes the list of possible PEI Services.
618 @return EFI_SUCCESS The PEIM initialized successfully.
624 IN EFI_PEI_FILE_HANDLE FileHandle
,
625 IN CONST EFI_PEI_SERVICES
**PeiServices
630 DEBUG ((DEBUG_INFO
, "Platform PEIM Loaded\n"));
636 if (QemuFwCfgS3Enabled ()) {
637 DEBUG ((EFI_D_INFO
, "S3 support was detected on QEMU\n"));
639 Status
= PcdSetBoolS (PcdAcpiS3Enable
, TRUE
);
640 ASSERT_EFI_ERROR (Status
);
644 BootModeInitialization ();
645 AddressWidthInitialization ();
646 MaxCpuCountInitialization ();
649 // Query Host Bridge DID
651 mHostBridgeDevId
= PciRead16 (OVMF_HOSTBRIDGE_DID
);
653 if (FeaturePcdGet (PcdSmmSmramRequire
)) {
654 Q35TsegMbytesInitialization ();
659 InitializeRamRegions ();
662 DEBUG ((EFI_D_INFO
, "Xen was detected\n"));
666 if (mBootMode
!= BOOT_ON_S3_RESUME
) {
667 if (!FeaturePcdGet (PcdSmmSmramRequire
)) {
668 ReserveEmuVariableNvStore ();
670 PeiFvInitialization ();
671 MemMapInitialization ();
672 NoexecDxeInitialization ();
676 MiscInitialization ();
677 InstallFeatureControlCallback ();