4 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
5 Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
7 SPDX-License-Identifier: BSD-2-Clause-Patent
12 // The package level header files this module uses
17 // The Library classes this module consumes
19 #include <Library/BaseLib.h>
20 #include <Library/DebugLib.h>
21 #include <Library/HobLib.h>
22 #include <Library/IoLib.h>
23 #include <Library/MemoryAllocationLib.h>
24 #include <Library/PcdLib.h>
25 #include <Library/PciLib.h>
26 #include <Library/PeimEntryPoint.h>
27 #include <Library/PeiServicesLib.h>
28 #include <Library/QemuFwCfgLib.h>
29 #include <Library/QemuFwCfgS3Lib.h>
30 #include <Library/ResourcePublicationLib.h>
31 #include <Guid/MemoryTypeInformation.h>
32 #include <Ppi/MasterBootMode.h>
33 #include <IndustryStandard/Pci22.h>
34 #include <OvmfPlatforms.h>
39 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation
[] = {
40 { EfiACPIMemoryNVS
, 0x004 },
41 { EfiACPIReclaimMemory
, 0x008 },
42 { EfiReservedMemoryType
, 0x004 },
43 { EfiRuntimeServicesData
, 0x024 },
44 { EfiRuntimeServicesCode
, 0x030 },
45 { EfiBootServicesCode
, 0x180 },
46 { EfiBootServicesData
, 0xF00 },
47 { EfiMaxMemoryType
, 0x000 }
51 EFI_PEI_PPI_DESCRIPTOR mPpiBootMode
[] = {
53 EFI_PEI_PPI_DESCRIPTOR_PPI
| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST
,
54 &gEfiPeiMasterBootModePpiGuid
,
60 UINT16 mHostBridgeDevId
;
62 EFI_BOOT_MODE mBootMode
= BOOT_WITH_FULL_CONFIGURATION
;
64 BOOLEAN mS3Supported
= FALSE
;
69 AddIoMemoryBaseSizeHob (
70 EFI_PHYSICAL_ADDRESS MemoryBase
,
74 BuildResourceDescriptorHob (
75 EFI_RESOURCE_MEMORY_MAPPED_IO
,
76 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
77 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
78 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
79 EFI_RESOURCE_ATTRIBUTE_TESTED
,
86 AddReservedMemoryBaseSizeHob (
87 EFI_PHYSICAL_ADDRESS MemoryBase
,
92 BuildResourceDescriptorHob (
93 EFI_RESOURCE_MEMORY_RESERVED
,
94 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
95 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
96 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
98 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE
|
99 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE
|
100 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
:
103 EFI_RESOURCE_ATTRIBUTE_TESTED
,
110 AddIoMemoryRangeHob (
111 EFI_PHYSICAL_ADDRESS MemoryBase
,
112 EFI_PHYSICAL_ADDRESS MemoryLimit
115 AddIoMemoryBaseSizeHob (MemoryBase
, (UINT64
)(MemoryLimit
- MemoryBase
));
120 AddMemoryBaseSizeHob (
121 EFI_PHYSICAL_ADDRESS MemoryBase
,
125 BuildResourceDescriptorHob (
126 EFI_RESOURCE_SYSTEM_MEMORY
,
127 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
128 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
129 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
130 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE
|
131 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE
|
132 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
|
133 EFI_RESOURCE_ATTRIBUTE_TESTED
,
142 EFI_PHYSICAL_ADDRESS MemoryBase
,
143 EFI_PHYSICAL_ADDRESS MemoryLimit
146 AddMemoryBaseSizeHob (MemoryBase
, (UINT64
)(MemoryLimit
- MemoryBase
));
151 MemMapInitialization (
157 RETURN_STATUS PcdStatus
;
163 // Create Memory Type Information HOB
166 &gEfiMemoryTypeInformationGuid
,
167 mDefaultMemoryTypeInformation
,
168 sizeof(mDefaultMemoryTypeInformation
)
172 // Video memory + Legacy BIOS region
174 AddIoMemoryRangeHob (0x0A0000, BASE_1MB
);
182 TopOfLowRam
= GetSystemMemorySizeBelow4gb ();
184 if (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
186 // The MMCONFIG area is expected to fall between the top of low RAM and
187 // the base of the 32-bit PCI host aperture.
189 PciExBarBase
= FixedPcdGet64 (PcdPciExpressBaseAddress
);
190 ASSERT (TopOfLowRam
<= PciExBarBase
);
191 ASSERT (PciExBarBase
<= MAX_UINT32
- SIZE_256MB
);
192 PciBase
= (UINT32
)(PciExBarBase
+ SIZE_256MB
);
193 PciSize
= 0xFC000000 - PciBase
;
195 PciBase
= (TopOfLowRam
< BASE_2GB
) ? BASE_2GB
: TopOfLowRam
;
196 PciSize
= 0xFC000000 - PciBase
;
200 // address purpose size
201 // ------------ -------- -------------------------
202 // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)
203 // 0xFC000000 gap 44 MB
204 // 0xFEC00000 IO-APIC 4 KB
205 // 0xFEC01000 gap 1020 KB
206 // 0xFED00000 HPET 1 KB
207 // 0xFED00400 gap 111 KB
208 // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB
209 // 0xFED20000 gap 896 KB
210 // 0xFEE00000 LAPIC 1 MB
212 AddIoMemoryBaseSizeHob (PciBase
, PciSize
);
213 PcdStatus
= PcdSet64S (PcdPciMmio32Base
, PciBase
);
214 ASSERT_RETURN_ERROR (PcdStatus
);
215 PcdStatus
= PcdSet64S (PcdPciMmio32Size
, PciSize
);
216 ASSERT_RETURN_ERROR (PcdStatus
);
218 AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB
);
219 AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB
);
220 if (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
221 AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE
, SIZE_16KB
);
223 // Note: there should be an
225 // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
227 // call below, just like the one above for RCBA. However, Linux insists
228 // that the MMCONFIG area be marked in the E820 or UEFI memory map as
229 // "reserved memory" -- Linux does not content itself with a simple gap
230 // in the memory map wherever the MCFG ACPI table points to.
232 // This appears to be a safety measure. The PCI Firmware Specification
233 // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
234 // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
235 // [...]". (Emphasis added here.)
237 // Normally we add memory resource descriptor HOBs in
238 // QemuInitializeRam(), and pre-allocate from those with memory
239 // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
240 // is most definitely not RAM; so, as an exception, cover it with
241 // uncacheable reserved memory right here.
243 AddReservedMemoryBaseSizeHob (PciExBarBase
, SIZE_256MB
, FALSE
);
244 BuildMemoryAllocationHob (PciExBarBase
, SIZE_256MB
,
245 EfiReservedMemoryType
);
247 AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress
), SIZE_1MB
);
250 // On Q35, the IO Port space is available for PCI resource allocations from
253 if (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
256 ASSERT ((ICH9_PMBASE_VALUE
& 0xF000) < PciIoBase
);
261 // Add PCI IO Port space available for PCI resource allocations.
263 BuildResourceDescriptorHob (
265 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
266 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
,
270 PcdStatus
= PcdSet64S (PcdPciIoBase
, PciIoBase
);
271 ASSERT_RETURN_ERROR (PcdStatus
);
272 PcdStatus
= PcdSet64S (PcdPciIoSize
, PciIoSize
);
273 ASSERT_RETURN_ERROR (PcdStatus
);
277 GetNamedFwCfgBoolean (
278 IN CHAR8
*FwCfgFileName
,
283 FIRMWARE_CONFIG_ITEM FwCfgItem
;
287 Status
= QemuFwCfgFindFile (FwCfgFileName
, &FwCfgItem
, &FwCfgSize
);
288 if (EFI_ERROR (Status
)) {
291 if (FwCfgSize
> sizeof Value
) {
292 return EFI_BAD_BUFFER_SIZE
;
294 QemuFwCfgSelectItem (FwCfgItem
);
295 QemuFwCfgReadBytes (FwCfgSize
, Value
);
297 if ((FwCfgSize
== 1) ||
298 (FwCfgSize
== 2 && Value
[1] == '\n') ||
299 (FwCfgSize
== 3 && Value
[1] == '\r' && Value
[2] == '\n')) {
317 return EFI_PROTOCOL_ERROR
;
320 #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \
323 RETURN_STATUS PcdStatus; \
325 if (!EFI_ERROR (GetNamedFwCfgBoolean ( \
326 "opt/ovmf/" #TokenName, &Setting))) { \
327 PcdStatus = PcdSetBoolS (TokenName, Setting); \
328 ASSERT_RETURN_ERROR (PcdStatus); \
333 NoexecDxeInitialization (
337 UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable
);
338 UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack
);
342 PciExBarInitialization (
352 // We only support the 256MB size for the MMCONFIG area:
353 // 256 buses * 32 devices * 8 functions * 4096 bytes config space.
355 // The masks used below enforce the Q35 requirements that the MMCONFIG area
356 // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.
358 // Note that (b) also ensures that the minimum address width we have
359 // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice
360 // for DXE's page tables to cover the MMCONFIG area.
362 PciExBarBase
.Uint64
= FixedPcdGet64 (PcdPciExpressBaseAddress
);
363 ASSERT ((PciExBarBase
.Uint32
[1] & MCH_PCIEXBAR_HIGHMASK
) == 0);
364 ASSERT ((PciExBarBase
.Uint32
[0] & MCH_PCIEXBAR_LOWMASK
) == 0);
367 // Clear the PCIEXBAREN bit first, before programming the high register.
369 PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW
), 0);
372 // Program the high register. Then program the low register, setting the
373 // MMCONFIG area size and enabling decoding at once.
375 PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH
), PciExBarBase
.Uint32
[1]);
377 DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW
),
378 PciExBarBase
.Uint32
[0] | MCH_PCIEXBAR_BUS_FF
| MCH_PCIEXBAR_EN
393 RETURN_STATUS PcdStatus
;
401 // Build the CPU HOB with guest RAM size dependent address width and 16-bits
402 // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
403 // S3 resume as well, so we build it unconditionally.)
405 BuildCpuHob (mPhysMemAddressWidth
, 16);
408 // Determine platform type and save Host Bridge DID to PCD
410 switch (mHostBridgeDevId
) {
411 case INTEL_82441_DEVICE_ID
:
412 PmCmd
= POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET
);
413 Pmba
= POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA
);
414 PmbaAndVal
= ~(UINT32
)PIIX4_PMBA_MASK
;
415 PmbaOrVal
= PIIX4_PMBA_VALUE
;
416 AcpiCtlReg
= POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC
);
417 AcpiEnBit
= PIIX4_PMREGMISC_PMIOSE
;
419 case INTEL_Q35_MCH_DEVICE_ID
:
420 PmCmd
= POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET
);
421 Pmba
= POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE
);
422 PmbaAndVal
= ~(UINT32
)ICH9_PMBASE_MASK
;
423 PmbaOrVal
= ICH9_PMBASE_VALUE
;
424 AcpiCtlReg
= POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL
);
425 AcpiEnBit
= ICH9_ACPI_CNTL_ACPI_EN
;
428 DEBUG ((EFI_D_ERROR
, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
429 __FUNCTION__
, mHostBridgeDevId
));
433 PcdStatus
= PcdSet16S (PcdOvmfHostBridgePciDevId
, mHostBridgeDevId
);
434 ASSERT_RETURN_ERROR (PcdStatus
);
437 // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
438 // has been configured (e.g., by Xen) and skip the setup here.
439 // This matches the logic in AcpiTimerLibConstructor ().
441 if ((PciRead8 (AcpiCtlReg
) & AcpiEnBit
) == 0) {
443 // The PEI phase should be exited with fully accessibe ACPI PM IO space:
446 PciAndThenOr32 (Pmba
, PmbaAndVal
, PmbaOrVal
);
449 // 2. set PCICMD/IOSE
451 PciOr8 (PmCmd
, EFI_PCI_COMMAND_IO_SPACE
);
454 // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
456 PciOr8 (AcpiCtlReg
, AcpiEnBit
);
459 if (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
461 // Set Root Complex Register Block BAR
464 POWER_MGMT_REGISTER_Q35 (ICH9_RCBA
),
465 ICH9_ROOT_COMPLEX_BASE
| ICH9_RCBA_EN
469 // Set PCI Express Register Range Base Address
471 PciExBarInitialization ();
477 BootModeInitialization (
483 if (CmosRead8 (0xF) == 0xFE) {
484 mBootMode
= BOOT_ON_S3_RESUME
;
486 CmosWrite8 (0xF, 0x00);
488 Status
= PeiServicesSetBootMode (mBootMode
);
489 ASSERT_EFI_ERROR (Status
);
491 Status
= PeiServicesInstallPpi (mPpiBootMode
);
492 ASSERT_EFI_ERROR (Status
);
497 ReserveEmuVariableNvStore (
500 EFI_PHYSICAL_ADDRESS VariableStore
;
501 RETURN_STATUS PcdStatus
;
504 // Allocate storage for NV variables early on so it will be
505 // at a consistent address. Since VM memory is preserved
506 // across reboots, this allows the NV variable storage to survive
510 (EFI_PHYSICAL_ADDRESS
)(UINTN
)
511 AllocateRuntimePages (
512 EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize
))
515 "Reserved variable store memory: 0x%lX; size: %dkb\n",
517 (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize
)) / 1024
519 PcdStatus
= PcdSet64S (PcdEmuVariableNvStoreReserved
, VariableStore
);
520 ASSERT_RETURN_ERROR (PcdStatus
);
531 DEBUG ((EFI_D_INFO
, "CMOS:\n"));
533 for (Loop
= 0; Loop
< 0x80; Loop
++) {
534 if ((Loop
% 0x10) == 0) {
535 DEBUG ((EFI_D_INFO
, "%02x:", Loop
));
537 DEBUG ((EFI_D_INFO
, " %02x", CmosRead8 (Loop
)));
538 if ((Loop
% 0x10) == 0xf) {
539 DEBUG ((EFI_D_INFO
, "\n"));
550 #if defined (MDE_CPU_X64)
551 if (FeaturePcdGet (PcdSmmSmramRequire
) && mS3Supported
) {
553 "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__
));
555 "%a: Please disable S3 on the QEMU command line (see the README),\n",
558 "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__
));
567 Fetch the number of boot CPUs from QEMU and expose it to UefiCpuPkg modules.
568 Set the mMaxCpuCount variable.
571 MaxCpuCountInitialization (
575 UINT16 ProcessorCount
;
576 RETURN_STATUS PcdStatus
;
578 QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount
);
579 ProcessorCount
= QemuFwCfgRead16 ();
581 // If the fw_cfg key or fw_cfg entirely is unavailable, load mMaxCpuCount
582 // from the PCD default. No change to PCDs.
584 if (ProcessorCount
== 0) {
585 mMaxCpuCount
= PcdGet32 (PcdCpuMaxLogicalProcessorNumber
);
589 // Otherwise, set mMaxCpuCount to the value reported by QEMU.
591 mMaxCpuCount
= ProcessorCount
;
593 // Additionally, tell UefiCpuPkg modules (a) the exact number of VCPUs, (b)
594 // to wait, in the initial AP bringup, exactly as long as it takes for all of
595 // the APs to report in. For this, we set the longest representable timeout
596 // (approx. 71 minutes).
598 PcdStatus
= PcdSet32S (PcdCpuMaxLogicalProcessorNumber
, ProcessorCount
);
599 ASSERT_RETURN_ERROR (PcdStatus
);
600 PcdStatus
= PcdSet32S (PcdCpuApInitTimeOutInMicroSeconds
, MAX_UINT32
);
601 ASSERT_RETURN_ERROR (PcdStatus
);
602 DEBUG ((DEBUG_INFO
, "%a: QEMU reports %d processor(s)\n", __FUNCTION__
,
608 Perform Platform PEI initialization.
610 @param FileHandle Handle of the file being invoked.
611 @param PeiServices Describes the list of possible PEI Services.
613 @return EFI_SUCCESS The PEIM initialized successfully.
619 IN EFI_PEI_FILE_HANDLE FileHandle
,
620 IN CONST EFI_PEI_SERVICES
**PeiServices
625 DEBUG ((DEBUG_INFO
, "Platform PEIM Loaded\n"));
631 if (QemuFwCfgS3Enabled ()) {
632 DEBUG ((EFI_D_INFO
, "S3 support was detected on QEMU\n"));
634 Status
= PcdSetBoolS (PcdAcpiS3Enable
, TRUE
);
635 ASSERT_EFI_ERROR (Status
);
639 BootModeInitialization ();
640 AddressWidthInitialization ();
641 MaxCpuCountInitialization ();
644 // Query Host Bridge DID
646 mHostBridgeDevId
= PciRead16 (OVMF_HOSTBRIDGE_DID
);
648 if (FeaturePcdGet (PcdSmmSmramRequire
)) {
649 Q35TsegMbytesInitialization ();
654 InitializeRamRegions ();
657 DEBUG ((EFI_D_INFO
, "Xen was detected\n"));
661 if (mBootMode
!= BOOT_ON_S3_RESUME
) {
662 if (!FeaturePcdGet (PcdSmmSmramRequire
)) {
663 ReserveEmuVariableNvStore ();
665 PeiFvInitialization ();
666 MemMapInitialization ();
667 NoexecDxeInitialization ();
670 InstallClearCacheCallback ();
672 MiscInitialization ();
673 InstallFeatureControlCallback ();