4 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
5 Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 // The package level header files this module uses
23 // The Library classes this module consumes
25 #include <Library/BaseLib.h>
26 #include <Library/DebugLib.h>
27 #include <Library/HobLib.h>
28 #include <Library/IoLib.h>
29 #include <Library/MemoryAllocationLib.h>
30 #include <Library/PcdLib.h>
31 #include <Library/PciLib.h>
32 #include <Library/PeimEntryPoint.h>
33 #include <Library/PeiServicesLib.h>
34 #include <Library/QemuFwCfgLib.h>
35 #include <Library/ResourcePublicationLib.h>
36 #include <Guid/MemoryTypeInformation.h>
37 #include <Ppi/MasterBootMode.h>
38 #include <IndustryStandard/Pci22.h>
39 #include <OvmfPlatforms.h>
44 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation
[] = {
45 { EfiACPIMemoryNVS
, 0x004 },
46 { EfiACPIReclaimMemory
, 0x008 },
47 { EfiReservedMemoryType
, 0x004 },
48 { EfiRuntimeServicesData
, 0x024 },
49 { EfiRuntimeServicesCode
, 0x030 },
50 { EfiBootServicesCode
, 0x180 },
51 { EfiBootServicesData
, 0xF00 },
52 { EfiMaxMemoryType
, 0x000 }
56 EFI_PEI_PPI_DESCRIPTOR mPpiBootMode
[] = {
58 EFI_PEI_PPI_DESCRIPTOR_PPI
| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST
,
59 &gEfiPeiMasterBootModePpiGuid
,
65 UINT16 mHostBridgeDevId
;
67 EFI_BOOT_MODE mBootMode
= BOOT_WITH_FULL_CONFIGURATION
;
69 BOOLEAN mS3Supported
= FALSE
;
73 AddIoMemoryBaseSizeHob (
74 EFI_PHYSICAL_ADDRESS MemoryBase
,
78 BuildResourceDescriptorHob (
79 EFI_RESOURCE_MEMORY_MAPPED_IO
,
80 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
81 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
82 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
83 EFI_RESOURCE_ATTRIBUTE_TESTED
,
90 AddReservedMemoryBaseSizeHob (
91 EFI_PHYSICAL_ADDRESS MemoryBase
,
96 BuildResourceDescriptorHob (
97 EFI_RESOURCE_MEMORY_RESERVED
,
98 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
99 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
100 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
102 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE
|
103 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE
|
104 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
:
107 EFI_RESOURCE_ATTRIBUTE_TESTED
,
114 AddIoMemoryRangeHob (
115 EFI_PHYSICAL_ADDRESS MemoryBase
,
116 EFI_PHYSICAL_ADDRESS MemoryLimit
119 AddIoMemoryBaseSizeHob (MemoryBase
, (UINT64
)(MemoryLimit
- MemoryBase
));
124 AddMemoryBaseSizeHob (
125 EFI_PHYSICAL_ADDRESS MemoryBase
,
129 BuildResourceDescriptorHob (
130 EFI_RESOURCE_SYSTEM_MEMORY
,
131 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
132 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
133 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
134 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE
|
135 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE
|
136 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
|
137 EFI_RESOURCE_ATTRIBUTE_TESTED
,
146 EFI_PHYSICAL_ADDRESS MemoryBase
,
147 EFI_PHYSICAL_ADDRESS MemoryLimit
150 AddMemoryBaseSizeHob (MemoryBase
, (UINT64
)(MemoryLimit
- MemoryBase
));
155 MemMapInitialization (
166 // Create Memory Type Information HOB
169 &gEfiMemoryTypeInformationGuid
,
170 mDefaultMemoryTypeInformation
,
171 sizeof(mDefaultMemoryTypeInformation
)
175 // Video memory + Legacy BIOS region
177 AddIoMemoryRangeHob (0x0A0000, BASE_1MB
);
185 TopOfLowRam
= GetSystemMemorySizeBelow4gb ();
187 if (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
189 // The MMCONFIG area is expected to fall between the top of low RAM and
190 // the base of the 32-bit PCI host aperture.
192 PciExBarBase
= FixedPcdGet64 (PcdPciExpressBaseAddress
);
193 ASSERT (TopOfLowRam
<= PciExBarBase
);
194 ASSERT (PciExBarBase
<= MAX_UINT32
- SIZE_256MB
);
195 PciBase
= (UINT32
)(PciExBarBase
+ SIZE_256MB
);
197 PciBase
= (TopOfLowRam
< BASE_2GB
) ? BASE_2GB
: TopOfLowRam
;
201 // address purpose size
202 // ------------ -------- -------------------------
203 // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)
204 // 0xFC000000 gap 44 MB
205 // 0xFEC00000 IO-APIC 4 KB
206 // 0xFEC01000 gap 1020 KB
207 // 0xFED00000 HPET 1 KB
208 // 0xFED00400 gap 111 KB
209 // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB
210 // 0xFED20000 gap 896 KB
211 // 0xFEE00000 LAPIC 1 MB
213 PciSize
= 0xFC000000 - PciBase
;
214 AddIoMemoryBaseSizeHob (PciBase
, PciSize
);
215 PcdSet64 (PcdPciMmio32Base
, PciBase
);
216 PcdSet64 (PcdPciMmio32Size
, PciSize
);
217 AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB
);
218 AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB
);
219 if (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
220 AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE
, SIZE_16KB
);
222 // Note: there should be an
224 // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
226 // call below, just like the one above for RCBA. However, Linux insists
227 // that the MMCONFIG area be marked in the E820 or UEFI memory map as
228 // "reserved memory" -- Linux does not content itself with a simple gap
229 // in the memory map wherever the MCFG ACPI table points to.
231 // This appears to be a safety measure. The PCI Firmware Specification
232 // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
233 // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
234 // [...]". (Emphasis added here.)
236 // Normally we add memory resource descriptor HOBs in
237 // QemuInitializeRam(), and pre-allocate from those with memory
238 // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
239 // is most definitely not RAM; so, as an exception, cover it with
240 // uncacheable reserved memory right here.
242 AddReservedMemoryBaseSizeHob (PciExBarBase
, SIZE_256MB
, FALSE
);
243 BuildMemoryAllocationHob (PciExBarBase
, SIZE_256MB
,
244 EfiReservedMemoryType
);
246 AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress
), SIZE_1MB
);
249 // On Q35, the IO Port space is available for PCI resource allocations from
252 if (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
255 ASSERT ((ICH9_PMBASE_VALUE
& 0xF000) < PciIoBase
);
260 // Add PCI IO Port space available for PCI resource allocations.
262 BuildResourceDescriptorHob (
264 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
265 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
,
269 PcdSet64 (PcdPciIoBase
, PciIoBase
);
270 PcdSet64 (PcdPciIoSize
, PciIoSize
);
274 GetNamedFwCfgBoolean (
275 IN CHAR8
*FwCfgFileName
,
280 FIRMWARE_CONFIG_ITEM FwCfgItem
;
284 Status
= QemuFwCfgFindFile (FwCfgFileName
, &FwCfgItem
, &FwCfgSize
);
285 if (EFI_ERROR (Status
)) {
288 if (FwCfgSize
> sizeof Value
) {
289 return EFI_BAD_BUFFER_SIZE
;
291 QemuFwCfgSelectItem (FwCfgItem
);
292 QemuFwCfgReadBytes (FwCfgSize
, Value
);
294 if ((FwCfgSize
== 1) ||
295 (FwCfgSize
== 2 && Value
[1] == '\n') ||
296 (FwCfgSize
== 3 && Value
[1] == '\r' && Value
[2] == '\n')) {
314 return EFI_PROTOCOL_ERROR
;
317 #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \
321 if (!EFI_ERROR (GetNamedFwCfgBoolean ( \
322 "opt/ovmf/" #TokenName, &Setting))) { \
323 PcdSetBool (TokenName, Setting); \
328 NoexecDxeInitialization (
332 UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable
);
333 UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack
);
337 PciExBarInitialization (
347 // We only support the 256MB size for the MMCONFIG area:
348 // 256 buses * 32 devices * 8 functions * 4096 bytes config space.
350 // The masks used below enforce the Q35 requirements that the MMCONFIG area
351 // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.
353 // Note that (b) also ensures that the minimum address width we have
354 // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice
355 // for DXE's page tables to cover the MMCONFIG area.
357 PciExBarBase
.Uint64
= FixedPcdGet64 (PcdPciExpressBaseAddress
);
358 ASSERT ((PciExBarBase
.Uint32
[1] & MCH_PCIEXBAR_HIGHMASK
) == 0);
359 ASSERT ((PciExBarBase
.Uint32
[0] & MCH_PCIEXBAR_LOWMASK
) == 0);
362 // Clear the PCIEXBAREN bit first, before programming the high register.
364 PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW
), 0);
367 // Program the high register. Then program the low register, setting the
368 // MMCONFIG area size and enabling decoding at once.
370 PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH
), PciExBarBase
.Uint32
[1]);
372 DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW
),
373 PciExBarBase
.Uint32
[0] | MCH_PCIEXBAR_BUS_FF
| MCH_PCIEXBAR_EN
395 // Build the CPU HOB with guest RAM size dependent address width and 16-bits
396 // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
397 // S3 resume as well, so we build it unconditionally.)
399 BuildCpuHob (mPhysMemAddressWidth
, 16);
402 // Determine platform type and save Host Bridge DID to PCD
404 switch (mHostBridgeDevId
) {
405 case INTEL_82441_DEVICE_ID
:
406 PmCmd
= POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET
);
407 Pmba
= POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA
);
408 PmbaAndVal
= ~(UINT32
)PIIX4_PMBA_MASK
;
409 PmbaOrVal
= PIIX4_PMBA_VALUE
;
410 AcpiCtlReg
= POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC
);
411 AcpiEnBit
= PIIX4_PMREGMISC_PMIOSE
;
413 case INTEL_Q35_MCH_DEVICE_ID
:
414 PmCmd
= POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET
);
415 Pmba
= POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE
);
416 PmbaAndVal
= ~(UINT32
)ICH9_PMBASE_MASK
;
417 PmbaOrVal
= ICH9_PMBASE_VALUE
;
418 AcpiCtlReg
= POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL
);
419 AcpiEnBit
= ICH9_ACPI_CNTL_ACPI_EN
;
422 DEBUG ((EFI_D_ERROR
, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
423 __FUNCTION__
, mHostBridgeDevId
));
427 PcdSet16 (PcdOvmfHostBridgePciDevId
, mHostBridgeDevId
);
430 // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
431 // has been configured (e.g., by Xen) and skip the setup here.
432 // This matches the logic in AcpiTimerLibConstructor ().
434 if ((PciRead8 (AcpiCtlReg
) & AcpiEnBit
) == 0) {
436 // The PEI phase should be exited with fully accessibe ACPI PM IO space:
439 PciAndThenOr32 (Pmba
, PmbaAndVal
, PmbaOrVal
);
442 // 2. set PCICMD/IOSE
444 PciOr8 (PmCmd
, EFI_PCI_COMMAND_IO_SPACE
);
447 // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
449 PciOr8 (AcpiCtlReg
, AcpiEnBit
);
452 if (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
454 // Set Root Complex Register Block BAR
457 POWER_MGMT_REGISTER_Q35 (ICH9_RCBA
),
458 ICH9_ROOT_COMPLEX_BASE
| ICH9_RCBA_EN
462 // Set PCI Express Register Range Base Address
464 PciExBarInitialization ();
470 BootModeInitialization (
476 if (CmosRead8 (0xF) == 0xFE) {
477 mBootMode
= BOOT_ON_S3_RESUME
;
479 CmosWrite8 (0xF, 0x00);
481 Status
= PeiServicesSetBootMode (mBootMode
);
482 ASSERT_EFI_ERROR (Status
);
484 Status
= PeiServicesInstallPpi (mPpiBootMode
);
485 ASSERT_EFI_ERROR (Status
);
490 ReserveEmuVariableNvStore (
493 EFI_PHYSICAL_ADDRESS VariableStore
;
496 // Allocate storage for NV variables early on so it will be
497 // at a consistent address. Since VM memory is preserved
498 // across reboots, this allows the NV variable storage to survive
502 (EFI_PHYSICAL_ADDRESS
)(UINTN
)
503 AllocateAlignedRuntimePages (
504 EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize
)),
505 PcdGet32 (PcdFlashNvStorageFtwSpareSize
)
508 "Reserved variable store memory: 0x%lX; size: %dkb\n",
510 (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize
)) / 1024
512 PcdSet64 (PcdEmuVariableNvStoreReserved
, VariableStore
);
523 DEBUG ((EFI_D_INFO
, "CMOS:\n"));
525 for (Loop
= 0; Loop
< 0x80; Loop
++) {
526 if ((Loop
% 0x10) == 0) {
527 DEBUG ((EFI_D_INFO
, "%02x:", Loop
));
529 DEBUG ((EFI_D_INFO
, " %02x", CmosRead8 (Loop
)));
530 if ((Loop
% 0x10) == 0xf) {
531 DEBUG ((EFI_D_INFO
, "\n"));
542 #if defined (MDE_CPU_X64)
543 if (FeaturePcdGet (PcdSmmSmramRequire
) && mS3Supported
) {
545 "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__
));
547 "%a: Please disable S3 on the QEMU command line (see the README),\n",
550 "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__
));
559 Perform Platform PEI initialization.
561 @param FileHandle Handle of the file being invoked.
562 @param PeiServices Describes the list of possible PEI Services.
564 @return EFI_SUCCESS The PEIM initialized successfully.
570 IN EFI_PEI_FILE_HANDLE FileHandle
,
571 IN CONST EFI_PEI_SERVICES
**PeiServices
576 DEBUG ((EFI_D_ERROR
, "Platform PEIM Loaded\n"));
582 if (QemuFwCfgS3Enabled ()) {
583 DEBUG ((EFI_D_INFO
, "S3 support was detected on QEMU\n"));
585 Status
= PcdSetBoolS (PcdAcpiS3Enable
, TRUE
);
586 ASSERT_EFI_ERROR (Status
);
590 BootModeInitialization ();
591 AddressWidthInitialization ();
595 InitializeRamRegions ();
598 DEBUG ((EFI_D_INFO
, "Xen was detected\n"));
603 // Query Host Bridge DID
605 mHostBridgeDevId
= PciRead16 (OVMF_HOSTBRIDGE_DID
);
607 if (mBootMode
!= BOOT_ON_S3_RESUME
) {
608 ReserveEmuVariableNvStore ();
609 PeiFvInitialization ();
610 MemMapInitialization ();
611 NoexecDxeInitialization ();
614 MiscInitialization ();