4 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
5 Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 // The package level header files this module uses
23 // The Library classes this module consumes
25 #include <Library/BaseLib.h>
26 #include <Library/DebugLib.h>
27 #include <Library/HobLib.h>
28 #include <Library/IoLib.h>
29 #include <Library/MemoryAllocationLib.h>
30 #include <Library/PcdLib.h>
31 #include <Library/PciLib.h>
32 #include <Library/PeimEntryPoint.h>
33 #include <Library/PeiServicesLib.h>
34 #include <Library/QemuFwCfgLib.h>
35 #include <Library/ResourcePublicationLib.h>
36 #include <Guid/MemoryTypeInformation.h>
37 #include <Ppi/MasterBootMode.h>
38 #include <IndustryStandard/Pci22.h>
39 #include <OvmfPlatforms.h>
44 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation
[] = {
45 { EfiACPIMemoryNVS
, 0x004 },
46 { EfiACPIReclaimMemory
, 0x008 },
47 { EfiReservedMemoryType
, 0x004 },
48 { EfiRuntimeServicesData
, 0x024 },
49 { EfiRuntimeServicesCode
, 0x030 },
50 { EfiBootServicesCode
, 0x180 },
51 { EfiBootServicesData
, 0xF00 },
52 { EfiMaxMemoryType
, 0x000 }
56 EFI_PEI_PPI_DESCRIPTOR mPpiBootMode
[] = {
58 EFI_PEI_PPI_DESCRIPTOR_PPI
| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST
,
59 &gEfiPeiMasterBootModePpiGuid
,
65 UINT16 mHostBridgeDevId
;
67 EFI_BOOT_MODE mBootMode
= BOOT_WITH_FULL_CONFIGURATION
;
69 BOOLEAN mS3Supported
= FALSE
;
73 AddIoMemoryBaseSizeHob (
74 EFI_PHYSICAL_ADDRESS MemoryBase
,
78 BuildResourceDescriptorHob (
79 EFI_RESOURCE_MEMORY_MAPPED_IO
,
80 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
81 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
82 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
83 EFI_RESOURCE_ATTRIBUTE_TESTED
,
90 AddReservedMemoryBaseSizeHob (
91 EFI_PHYSICAL_ADDRESS MemoryBase
,
96 BuildResourceDescriptorHob (
97 EFI_RESOURCE_MEMORY_RESERVED
,
98 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
99 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
100 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
102 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE
|
103 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE
|
104 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
:
107 EFI_RESOURCE_ATTRIBUTE_TESTED
,
114 AddIoMemoryRangeHob (
115 EFI_PHYSICAL_ADDRESS MemoryBase
,
116 EFI_PHYSICAL_ADDRESS MemoryLimit
119 AddIoMemoryBaseSizeHob (MemoryBase
, (UINT64
)(MemoryLimit
- MemoryBase
));
124 AddMemoryBaseSizeHob (
125 EFI_PHYSICAL_ADDRESS MemoryBase
,
129 BuildResourceDescriptorHob (
130 EFI_RESOURCE_SYSTEM_MEMORY
,
131 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
132 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
133 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
134 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE
|
135 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE
|
136 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
|
137 EFI_RESOURCE_ATTRIBUTE_TESTED
,
146 EFI_PHYSICAL_ADDRESS MemoryBase
,
147 EFI_PHYSICAL_ADDRESS MemoryLimit
150 AddMemoryBaseSizeHob (MemoryBase
, (UINT64
)(MemoryLimit
- MemoryBase
));
155 MemMapInitialization (
160 // Create Memory Type Information HOB
163 &gEfiMemoryTypeInformationGuid
,
164 mDefaultMemoryTypeInformation
,
165 sizeof(mDefaultMemoryTypeInformation
)
169 // Add PCI IO Port space available for PCI resource allocations.
171 BuildResourceDescriptorHob (
173 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
174 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
,
175 PcdGet64 (PcdPciIoBase
),
176 PcdGet64 (PcdPciIoSize
)
180 // Video memory + Legacy BIOS region
182 AddIoMemoryRangeHob (0x0A0000, BASE_1MB
);
190 TopOfLowRam
= GetSystemMemorySizeBelow4gb ();
192 if (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
194 // The MMCONFIG area is expected to fall between the top of low RAM and
195 // the base of the 32-bit PCI host aperture.
197 PciExBarBase
= FixedPcdGet64 (PcdPciExpressBaseAddress
);
198 ASSERT (TopOfLowRam
<= PciExBarBase
);
199 ASSERT (PciExBarBase
<= MAX_UINT32
- SIZE_256MB
);
200 PciBase
= (UINT32
)(PciExBarBase
+ SIZE_256MB
);
202 PciBase
= (TopOfLowRam
< BASE_2GB
) ? BASE_2GB
: TopOfLowRam
;
206 // address purpose size
207 // ------------ -------- -------------------------
208 // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)
209 // 0xFC000000 gap 44 MB
210 // 0xFEC00000 IO-APIC 4 KB
211 // 0xFEC01000 gap 1020 KB
212 // 0xFED00000 HPET 1 KB
213 // 0xFED00400 gap 111 KB
214 // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB
215 // 0xFED20000 gap 896 KB
216 // 0xFEE00000 LAPIC 1 MB
218 PciSize
= 0xFC000000 - PciBase
;
219 AddIoMemoryBaseSizeHob (PciBase
, PciSize
);
220 PcdSet64 (PcdPciMmio32Base
, PciBase
);
221 PcdSet64 (PcdPciMmio32Size
, PciSize
);
222 AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB
);
223 AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB
);
224 if (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
225 AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE
, SIZE_16KB
);
227 // Note: there should be an
229 // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
231 // call below, just like the one above for RCBA. However, Linux insists
232 // that the MMCONFIG area be marked in the E820 or UEFI memory map as
233 // "reserved memory" -- Linux does not content itself with a simple gap
234 // in the memory map wherever the MCFG ACPI table points to.
236 // This appears to be a safety measure. The PCI Firmware Specification
237 // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
238 // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
239 // [...]". (Emphasis added here.)
241 // Normally we add memory resource descriptor HOBs in
242 // QemuInitializeRam(), and pre-allocate from those with memory
243 // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
244 // is most definitely not RAM; so, as an exception, cover it with
245 // uncacheable reserved memory right here.
247 AddReservedMemoryBaseSizeHob (PciExBarBase
, SIZE_256MB
, FALSE
);
248 BuildMemoryAllocationHob (PciExBarBase
, SIZE_256MB
,
249 EfiReservedMemoryType
);
251 AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress
), SIZE_1MB
);
256 GetNamedFwCfgBoolean (
257 IN CHAR8
*FwCfgFileName
,
262 FIRMWARE_CONFIG_ITEM FwCfgItem
;
266 Status
= QemuFwCfgFindFile (FwCfgFileName
, &FwCfgItem
, &FwCfgSize
);
267 if (EFI_ERROR (Status
)) {
270 if (FwCfgSize
> sizeof Value
) {
271 return EFI_BAD_BUFFER_SIZE
;
273 QemuFwCfgSelectItem (FwCfgItem
);
274 QemuFwCfgReadBytes (FwCfgSize
, Value
);
276 if ((FwCfgSize
== 1) ||
277 (FwCfgSize
== 2 && Value
[1] == '\n') ||
278 (FwCfgSize
== 3 && Value
[1] == '\r' && Value
[2] == '\n')) {
296 return EFI_PROTOCOL_ERROR
;
299 #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \
303 if (!EFI_ERROR (GetNamedFwCfgBoolean ( \
304 "opt/ovmf/" #TokenName, &Setting))) { \
305 PcdSetBool (TokenName, Setting); \
310 NoexecDxeInitialization (
314 UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable
);
315 UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack
);
319 PciExBarInitialization (
329 // We only support the 256MB size for the MMCONFIG area:
330 // 256 buses * 32 devices * 8 functions * 4096 bytes config space.
332 // The masks used below enforce the Q35 requirements that the MMCONFIG area
333 // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.
335 // Note that (b) also ensures that the minimum address width we have
336 // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice
337 // for DXE's page tables to cover the MMCONFIG area.
339 PciExBarBase
.Uint64
= FixedPcdGet64 (PcdPciExpressBaseAddress
);
340 ASSERT ((PciExBarBase
.Uint32
[1] & MCH_PCIEXBAR_HIGHMASK
) == 0);
341 ASSERT ((PciExBarBase
.Uint32
[0] & MCH_PCIEXBAR_LOWMASK
) == 0);
344 // Clear the PCIEXBAREN bit first, before programming the high register.
346 PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW
), 0);
349 // Program the high register. Then program the low register, setting the
350 // MMCONFIG area size and enabling decoding at once.
352 PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH
), PciExBarBase
.Uint32
[1]);
354 DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW
),
355 PciExBarBase
.Uint32
[0] | MCH_PCIEXBAR_BUS_FF
| MCH_PCIEXBAR_EN
375 // Build the CPU HOB with guest RAM size dependent address width and 16-bits
376 // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
377 // S3 resume as well, so we build it unconditionally.)
379 BuildCpuHob (mPhysMemAddressWidth
, 16);
382 // Determine platform type and save Host Bridge DID to PCD
384 switch (mHostBridgeDevId
) {
385 case INTEL_82441_DEVICE_ID
:
386 PmCmd
= POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET
);
387 Pmba
= POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA
);
388 AcpiCtlReg
= POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC
);
389 AcpiEnBit
= PIIX4_PMREGMISC_PMIOSE
;
391 case INTEL_Q35_MCH_DEVICE_ID
:
392 PmCmd
= POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET
);
393 Pmba
= POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE
);
394 AcpiCtlReg
= POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL
);
395 AcpiEnBit
= ICH9_ACPI_CNTL_ACPI_EN
;
398 DEBUG ((EFI_D_ERROR
, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
399 __FUNCTION__
, mHostBridgeDevId
));
403 PcdSet16 (PcdOvmfHostBridgePciDevId
, mHostBridgeDevId
);
406 // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
407 // has been configured (e.g., by Xen) and skip the setup here.
408 // This matches the logic in AcpiTimerLibConstructor ().
410 if ((PciRead8 (AcpiCtlReg
) & AcpiEnBit
) == 0) {
412 // The PEI phase should be exited with fully accessibe ACPI PM IO space:
415 PciAndThenOr32 (Pmba
, ~(UINT32
)PIIX4_PMBA_MASK
, PIIX4_PMBA_VALUE
);
418 // 2. set PCICMD/IOSE
420 PciOr8 (PmCmd
, EFI_PCI_COMMAND_IO_SPACE
);
423 // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
425 PciOr8 (AcpiCtlReg
, AcpiEnBit
);
428 if (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
430 // Set Root Complex Register Block BAR
433 POWER_MGMT_REGISTER_Q35 (ICH9_RCBA
),
434 ICH9_ROOT_COMPLEX_BASE
| ICH9_RCBA_EN
438 // Set PCI Express Register Range Base Address
440 PciExBarInitialization ();
446 BootModeInitialization (
452 if (CmosRead8 (0xF) == 0xFE) {
453 mBootMode
= BOOT_ON_S3_RESUME
;
455 CmosWrite8 (0xF, 0x00);
457 Status
= PeiServicesSetBootMode (mBootMode
);
458 ASSERT_EFI_ERROR (Status
);
460 Status
= PeiServicesInstallPpi (mPpiBootMode
);
461 ASSERT_EFI_ERROR (Status
);
466 ReserveEmuVariableNvStore (
469 EFI_PHYSICAL_ADDRESS VariableStore
;
472 // Allocate storage for NV variables early on so it will be
473 // at a consistent address. Since VM memory is preserved
474 // across reboots, this allows the NV variable storage to survive
478 (EFI_PHYSICAL_ADDRESS
)(UINTN
)
479 AllocateAlignedRuntimePages (
480 EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize
)),
481 PcdGet32 (PcdFlashNvStorageFtwSpareSize
)
484 "Reserved variable store memory: 0x%lX; size: %dkb\n",
486 (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize
)) / 1024
488 PcdSet64 (PcdEmuVariableNvStoreReserved
, VariableStore
);
499 DEBUG ((EFI_D_INFO
, "CMOS:\n"));
501 for (Loop
= 0; Loop
< 0x80; Loop
++) {
502 if ((Loop
% 0x10) == 0) {
503 DEBUG ((EFI_D_INFO
, "%02x:", Loop
));
505 DEBUG ((EFI_D_INFO
, " %02x", CmosRead8 (Loop
)));
506 if ((Loop
% 0x10) == 0xf) {
507 DEBUG ((EFI_D_INFO
, "\n"));
518 #if defined (MDE_CPU_X64)
519 if (FeaturePcdGet (PcdSmmSmramRequire
) && mS3Supported
) {
521 "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__
));
523 "%a: Please disable S3 on the QEMU command line (see the README),\n",
526 "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__
));
535 Perform Platform PEI initialization.
537 @param FileHandle Handle of the file being invoked.
538 @param PeiServices Describes the list of possible PEI Services.
540 @return EFI_SUCCESS The PEIM initialized successfully.
546 IN EFI_PEI_FILE_HANDLE FileHandle
,
547 IN CONST EFI_PEI_SERVICES
**PeiServices
552 DEBUG ((EFI_D_ERROR
, "Platform PEIM Loaded\n"));
558 if (QemuFwCfgS3Enabled ()) {
559 DEBUG ((EFI_D_INFO
, "S3 support was detected on QEMU\n"));
561 Status
= PcdSetBoolS (PcdAcpiS3Enable
, TRUE
);
562 ASSERT_EFI_ERROR (Status
);
566 BootModeInitialization ();
567 AddressWidthInitialization ();
571 InitializeRamRegions ();
574 DEBUG ((EFI_D_INFO
, "Xen was detected\n"));
579 // Query Host Bridge DID
581 mHostBridgeDevId
= PciRead16 (OVMF_HOSTBRIDGE_DID
);
583 if (mBootMode
!= BOOT_ON_S3_RESUME
) {
584 ReserveEmuVariableNvStore ();
585 PeiFvInitialization ();
586 MemMapInitialization ();
587 NoexecDxeInitialization ();
590 MiscInitialization ();