OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm

   1 ;------------------------------------------------------------------------------
   2 ; @file
   3 ; First code executed by processor after resetting.
   4 ; Derived from UefiCpuPkg/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm
   5 ;
   6 ; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
   7 ; SPDX-License-Identifier: BSD-2-Clause-Patent
   8 ;
   9 ;------------------------------------------------------------------------------
  10
  11 BITS    16
  12
  13 ALIGN   16
  14
  15 ;
  16 ; Pad the image size to 4k when page tables are in VTF0
  17 ;
  18 ; If the VTF0 image has page tables built in, then we need to make
  19 ; sure the end of VTF0 is 4k above where the page tables end.
  20 ;
  21 ; This is required so the page tables will be 4k aligned when VTF0 is
  22 ; located just below 0x100000000 (4GB) in the firmware device.
  23 ;
  24 %ifdef ALIGN_TOP_TO_4K_FOR_PAGING
  25     TIMES (0x1000 - ($ - EndOfPageTables) - 0x20) DB 0
  26 %endif
  27
  28 ;
  29 ; SEV-ES Processor Reset support
  30 ;
  31 ; sevEsResetBlock:
  32 ;   For the initial boot of an AP under SEV-ES, the "reset" RIP must be
  33 ;   programmed to the RAM area defined by SEV_ES_AP_RESET_IP. A known offset
  34 ;   and GUID will be used to locate this block in the firmware and extract
  35 ;   the build time RIP value. The GUID must always be 48 bytes from the
  36 ;   end of the firmware.
  37 ;
  38 ;   0xffffffca (-0x36) - IP value
  39 ;   0xffffffcc (-0x34) - CS segment base [31:16]
  40 ;   0xffffffce (-0x32) - Size of the SEV-ES reset block
  41 ;   0xffffffd0 (-0x30) - SEV-ES reset block GUID
  42 ;                        (00f771de-1a7e-4fcb-890e-68c77e2fb44e)
  43 ;
  44 ;   A hypervisor reads the CS segement base and IP value. The CS segment base
  45 ;   value represents the high order 16-bits of the CS segment base, so the
  46 ;   hypervisor must left shift the value of the CS segement base by 16 bits to
  47 ;   form the full CS segment base for the CS segment register. It would then
  48 ;   program the EIP register with the IP value as read.
  49 ;
  50
  51 TIMES (32 - (sevEsResetBlockEnd - sevEsResetBlockStart)) DB 0
  52
  53 sevEsResetBlockStart:
  54     DD      SEV_ES_AP_RESET_IP
  55     DW      sevEsResetBlockEnd - sevEsResetBlockStart
  56     DB      0xDE, 0x71, 0xF7, 0x00, 0x7E, 0x1A, 0xCB, 0x4F
  57     DB      0x89, 0x0E, 0x68, 0xC7, 0x7E, 0x2F, 0xB4, 0x4E
  58 sevEsResetBlockEnd:
  59
  60 ALIGN   16
  61
  62 applicationProcessorEntryPoint:
  63 ;
  64 ; Application Processors entry point
  65 ;
  66 ; GenFv generates code aligned on a 4k boundary which will jump to this
  67 ; location.  (0xffffffe0)  This allows the Local APIC Startup IPI to be
  68 ; used to wake up the application processors.
  69 ;
  70     jmp     EarlyApInitReal16
  71
  72 ALIGN   8
  73
  74     DD      0
  75
  76 ;
  77 ; The VTF signature
  78 ;
  79 ; VTF-0 means that the VTF (Volume Top File) code does not require
  80 ; any fixups.
  81 ;
  82 vtfSignature:
  83     DB      'V', 'T', 'F', 0
  84
  85 ALIGN   16
  86
  87 resetVector:
  88 ;
  89 ; Reset Vector
  90 ;
  91 ; This is where the processor will begin execution
  92 ;
  93     nop
  94     nop
  95     jmp     EarlyBspInitReal16
  96
  97 ALIGN   16
  98
  99 fourGigabytes:
 100