OvmfPkg/ResetVector/Ia32/AmdSev.asm

   1 ;------------------------------------------------------------------------------
   2 ; @file
   3 ; Provide the functions to check whether SEV and SEV-ES is enabled.
   4 ;
   5 ; Copyright (c) 2017 - 2021, Advanced Micro Devices, Inc. All rights reserved.<BR>
   6 ; SPDX-License-Identifier: BSD-2-Clause-Patent
   7 ;
   8 ;------------------------------------------------------------------------------
   9
  10 BITS    32
  11
  12 ;
  13 ; SEV-ES #VC exception handler support
  14 ;
  15 ; #VC handler local variable locations
  16 ;
  17 %define VC_CPUID_RESULT_EAX         0
  18 %define VC_CPUID_RESULT_EBX         4
  19 %define VC_CPUID_RESULT_ECX         8
  20 %define VC_CPUID_RESULT_EDX        12
  21 %define VC_GHCB_MSR_EDX            16
  22 %define VC_GHCB_MSR_EAX            20
  23 %define VC_CPUID_REQUEST_REGISTER  24
  24 %define VC_CPUID_FUNCTION          28
  25
  26 ; #VC handler total local variable size
  27 ;
  28 %define VC_VARIABLE_SIZE           32
  29
  30 ; #VC handler GHCB CPUID request/response protocol values
  31 ;
  32 %define GHCB_CPUID_REQUEST          4
  33 %define GHCB_CPUID_RESPONSE         5
  34 %define GHCB_CPUID_REGISTER_SHIFT  30
  35 %define CPUID_INSN_LEN              2
  36
  37
  38 %define SEV_GHCB_MSR                0xc0010130
  39 %define SEV_STATUS_MSR              0xc0010131
  40
  41 ; The #VC was not for CPUID
  42 %define TERM_VC_NOT_CPUID           1
  43
  44 ; The unexpected response code
  45 %define TERM_UNEXPECTED_RESP_CODE   2
  46
  47 %define PAGE_PRESENT            0x01
  48 %define PAGE_READ_WRITE         0x02
  49 %define PAGE_USER_SUPERVISOR    0x04
  50 %define PAGE_WRITE_THROUGH      0x08
  51 %define PAGE_CACHE_DISABLE     0x010
  52 %define PAGE_ACCESSED          0x020
  53 %define PAGE_DIRTY             0x040
  54 %define PAGE_PAT               0x080
  55 %define PAGE_GLOBAL           0x0100
  56 %define PAGE_2M_MBO            0x080
  57 %define PAGE_2M_PAT          0x01000
  58
  59 %define PAGE_4K_PDE_ATTR (PAGE_ACCESSED + \
  60                           PAGE_DIRTY + \
  61                           PAGE_READ_WRITE + \
  62                           PAGE_PRESENT)
  63
  64 %define PAGE_PDP_ATTR (PAGE_ACCESSED + \
  65                        PAGE_READ_WRITE + \
  66                        PAGE_PRESENT)
  67
  68
  69 ; Macro is used to issue the MSR protocol based VMGEXIT. The caller is
  70 ; responsible to populate values in the EDX:EAX registers. After the vmmcall
  71 ; returns, it verifies that the response code matches with the expected
  72 ; code. If it does not match then terminate the guest. The result of request
  73 ; is returned in the EDX:EAX.
  74 ;
  75 ; args 1:Request code, 2: Response code
  76 %macro VmgExit 2
  77     ;
  78     ; Add request code:
  79     ;   GHCB_MSR[11:0]  = Request code
  80     or      eax, %1
  81
  82     mov     ecx, SEV_GHCB_MSR
  83     wrmsr
  84
  85     ; Issue VMGEXIT - NASM doesn't support the vmmcall instruction in 32-bit
  86     ; mode, so work around this by temporarily switching to 64-bit mode.
  87     ;
  88 BITS    64
  89     rep     vmmcall
  90 BITS    32
  91
  92     mov     ecx, SEV_GHCB_MSR
  93     rdmsr
  94
  95     ;
  96     ; Verify the reponse code, if it does not match then request to terminate
  97     ;   GHCB_MSR[11:0]  = Response code
  98     mov     ecx, eax
  99     and     ecx, 0xfff
 100     cmp     ecx, %2
 101     jne     SevEsUnexpectedRespTerminate
 102 %endmacro
 103
 104 ; Macro to terminate the guest using the VMGEXIT.
 105 ; arg 1: reason code
 106 %macro TerminateVmgExit 1
 107     mov     eax, %1
 108     ;
 109     ; Use VMGEXIT to request termination. At this point the reason code is
 110     ; located in EAX, so shift it left 16 bits to the proper location.
 111     ;
 112     ; EAX[11:0]  => 0x100 - request termination
 113     ; EAX[15:12] => 0x1   - OVMF
 114     ; EAX[23:16] => 0xXX  - REASON CODE
 115     ;
 116     shl     eax, 16
 117     or      eax, 0x1100
 118     xor     edx, edx
 119     mov     ecx, SEV_GHCB_MSR
 120     wrmsr
 121     ;
 122     ; Issue VMGEXIT - NASM doesn't support the vmmcall instruction in 32-bit
 123     ; mode, so work around this by temporarily switching to 64-bit mode.
 124     ;
 125 BITS    64
 126     rep     vmmcall
 127 BITS    32
 128
 129     ;
 130     ; We shouldn't come back from the VMGEXIT, but if we do, just loop.
 131     ;
 132 %%TerminateHlt:
 133     hlt
 134     jmp     %%TerminateHlt
 135 %endmacro
 136
 137 ; Terminate the guest due to unexpected response code.
 138 SevEsUnexpectedRespTerminate:
 139     TerminateVmgExit    TERM_UNEXPECTED_RESP_CODE
 140
 141 ; If SEV-ES is enabled then initialize and make the GHCB page shared
 142 SevClearPageEncMaskForGhcbPage:
 143     ; Check if SEV is enabled
 144     cmp       byte[WORK_AREA_GUEST_TYPE], 1
 145     jnz       SevClearPageEncMaskForGhcbPageExit
 146
 147     ; Check if SEV-ES is enabled
 148     cmp       byte[SEV_ES_WORK_AREA], 1
 149     jnz       SevClearPageEncMaskForGhcbPageExit
 150
 151     ;
 152     ; The initial GHCB will live at GHCB_BASE and needs to be un-encrypted.
 153     ; This requires the 2MB page for this range be broken down into 512 4KB
 154     ; pages.  All will be marked encrypted, except for the GHCB.
 155     ;
 156     mov     ecx, (GHCB_BASE >> 21)
 157     mov     eax, GHCB_PT_ADDR + PAGE_PDP_ATTR
 158     mov     [ecx * 8 + PT_ADDR (0x2000)], eax
 159
 160     ;
 161     ; Page Table Entries (512 * 4KB entries => 2MB)
 162     ;
 163     mov     ecx, 512
 164 pageTableEntries4kLoop:
 165     mov     eax, ecx
 166     dec     eax
 167     shl     eax, 12
 168     add     eax, GHCB_BASE & 0xFFE0_0000
 169     add     eax, PAGE_4K_PDE_ATTR
 170     mov     [ecx * 8 + GHCB_PT_ADDR - 8], eax
 171     mov     [(ecx * 8 + GHCB_PT_ADDR - 8) + 4], edx
 172     loop    pageTableEntries4kLoop
 173
 174     ;
 175     ; Clear the encryption bit from the GHCB entry
 176     ;
 177     mov     ecx, (GHCB_BASE & 0x1F_FFFF) >> 12
 178     mov     [ecx * 8 + GHCB_PT_ADDR + 4], strict dword 0
 179
 180 SevClearPageEncMaskForGhcbPageExit:
 181     OneTimeCallRet SevClearPageEncMaskForGhcbPage
 182
 183 ; Check if SEV is enabled, and get the C-bit mask above 31.
 184 ; Modified: EDX
 185 ;
 186 ; The value is returned in the EDX
 187 GetSevCBitMaskAbove31:
 188     xor       edx, edx
 189
 190     ; Check if SEV is enabled
 191     cmp       byte[WORK_AREA_GUEST_TYPE], 1
 192     jnz       GetSevCBitMaskAbove31Exit
 193
 194     mov       edx, dword[SEV_ES_WORK_AREA_ENC_MASK + 4]
 195
 196 GetSevCBitMaskAbove31Exit:
 197     OneTimeCallRet GetSevCBitMaskAbove31
 198
 199 ; Check if Secure Encrypted Virtualization (SEV) features are enabled.
 200 ;
 201 ; Register usage is tight in this routine, so multiple calls for the
 202 ; same CPUID and MSR data are performed to keep things simple.
 203 ;
 204 ; Modified:  EAX, EBX, ECX, EDX, ESP
 205 ;
 206 ; If SEV is enabled then EAX will be at least 32.
 207 ; If SEV is disabled then EAX will be zero.
 208 ;
 209 CheckSevFeatures:
 210     ; Set the first byte of the workarea to zero to communicate to the SEC
 211     ; phase that SEV-ES is not enabled. If SEV-ES is enabled, the CPUID
 212     ; instruction will trigger a #VC exception where the first byte of the
 213     ; workarea will be set to one or, if CPUID is not being intercepted,
 214     ; the MSR check below will set the first byte of the workarea to one.
 215     mov     byte[SEV_ES_WORK_AREA], 0
 216
 217     ;
 218     ; Set up exception handlers to check for SEV-ES
 219     ;   Load temporary RAM stack based on PCDs (see SevEsIdtVmmComm for
 220     ;   stack usage)
 221     ;   Establish exception handlers
 222     ;
 223     mov       esp, SEV_ES_VC_TOP_OF_STACK
 224     mov       eax, ADDR_OF(Idtr)
 225     lidt      [cs:eax]
 226
 227     ; Check if we have a valid (0x8000_001F) CPUID leaf
 228     ;   CPUID raises a #VC exception if running as an SEV-ES guest
 229     mov       eax, 0x80000000
 230     cpuid
 231
 232     ; This check should fail on Intel or Non SEV AMD CPUs. In future if
 233     ; Intel CPUs supports this CPUID leaf then we are guranteed to have exact
 234     ; same bit definition.
 235     cmp       eax, 0x8000001f
 236     jl        NoSev
 237
 238     ; Check for SEV memory encryption feature:
 239     ; CPUID  Fn8000_001F[EAX] - Bit 1
 240     ;   CPUID raises a #VC exception if running as an SEV-ES guest
 241     mov       eax, 0x8000001f
 242     cpuid
 243     bt        eax, 1
 244     jnc       NoSev
 245
 246     ; Check if SEV memory encryption is enabled
 247     ;  MSR_0xC0010131 - Bit 0 (SEV enabled)
 248     mov       ecx, SEV_STATUS_MSR
 249     rdmsr
 250     bt        eax, 0
 251     jnc       NoSev
 252
 253     ; Set the work area header to indicate that the SEV is enabled
 254     mov     byte[WORK_AREA_GUEST_TYPE], 1
 255
 256     ; Check for SEV-ES memory encryption feature:
 257     ; CPUID  Fn8000_001F[EAX] - Bit 3
 258     ;   CPUID raises a #VC exception if running as an SEV-ES guest
 259     mov       eax, 0x8000001f
 260     cpuid
 261     bt        eax, 3
 262     jnc       GetSevEncBit
 263
 264     ; Check if SEV-ES is enabled
 265     ;  MSR_0xC0010131 - Bit 1 (SEV-ES enabled)
 266     mov       ecx, SEV_STATUS_MSR
 267     rdmsr
 268     bt        eax, 1
 269     jnc       GetSevEncBit
 270
 271     ; Set the first byte of the workarea to one to communicate to the SEC
 272     ; phase that SEV-ES is enabled.
 273     mov       byte[SEV_ES_WORK_AREA], 1
 274
 275 GetSevEncBit:
 276     ; Get pte bit position to enable memory encryption
 277     ; CPUID Fn8000_001F[EBX] - Bits 5:0
 278     ;
 279     and       ebx, 0x3f
 280     mov       eax, ebx
 281
 282     ; The encryption bit position is always above 31
 283     sub       ebx, 32
 284     jns       SevSaveMask
 285
 286     ; Encryption bit was reported as 31 or below, enter a HLT loop
 287 SevEncBitLowHlt:
 288     cli
 289     hlt
 290     jmp       SevEncBitLowHlt
 291
 292 SevSaveMask:
 293     xor       edx, edx
 294     bts       edx, ebx
 295
 296     mov       dword[SEV_ES_WORK_AREA_ENC_MASK], 0
 297     mov       dword[SEV_ES_WORK_AREA_ENC_MASK + 4], edx
 298     jmp       SevExit
 299
 300 NoSev:
 301     ;
 302     ; Perform an SEV-ES sanity check by seeing if a #VC exception occurred.
 303     ;
 304     cmp       byte[SEV_ES_WORK_AREA], 0
 305     jz        NoSevPass
 306
 307     ;
 308     ; A #VC was received, yet CPUID indicates no SEV-ES support, something
 309     ; isn't right.
 310     ;
 311 NoSevEsVcHlt:
 312     cli
 313     hlt
 314     jmp       NoSevEsVcHlt
 315
 316 NoSevPass:
 317     xor       eax, eax
 318
 319 SevExit:
 320     ;
 321     ; Clear exception handlers and stack
 322     ;
 323     push      eax
 324     mov       eax, ADDR_OF(IdtrClear)
 325     lidt      [cs:eax]
 326     pop       eax
 327     mov       esp, 0
 328
 329     OneTimeCallRet CheckSevFeatures
 330
 331 ; Start of #VC exception handling routines
 332 ;
 333
 334 SevEsIdtNotCpuid:
 335     TerminateVmgExit TERM_VC_NOT_CPUID
 336     iret
 337
 338     ;
 339     ; Total stack usage for the #VC handler is 44 bytes:
 340     ;   - 12 bytes for the exception IRET (after popping error code)
 341     ;   - 32 bytes for the local variables.
 342     ;
 343 SevEsIdtVmmComm:
 344     ;
 345     ; If we're here, then we are an SEV-ES guest and this
 346     ; was triggered by a CPUID instruction
 347     ;
 348     ; Set the first byte of the workarea to one to communicate that
 349     ; a #VC was taken.
 350     mov     byte[SEV_ES_WORK_AREA], 1
 351
 352     pop     ecx                     ; Error code
 353     cmp     ecx, 0x72               ; Be sure it was CPUID
 354     jne     SevEsIdtNotCpuid
 355
 356     ; Set up local variable room on the stack
 357     ;   CPUID function         : + 28
 358     ;   CPUID request register : + 24
 359     ;   GHCB MSR (EAX)         : + 20
 360     ;   GHCB MSR (EDX)         : + 16
 361     ;   CPUID result (EDX)     : + 12
 362     ;   CPUID result (ECX)     : + 8
 363     ;   CPUID result (EBX)     : + 4
 364     ;   CPUID result (EAX)     : + 0
 365     sub     esp, VC_VARIABLE_SIZE
 366
 367     ; Save the CPUID function being requested
 368     mov     [esp + VC_CPUID_FUNCTION], eax
 369
 370     ; The GHCB CPUID protocol uses the following mapping to request
 371     ; a specific register:
 372     ;   0 => EAX, 1 => EBX, 2 => ECX, 3 => EDX
 373     ;
 374     ; Set EAX as the first register to request. This will also be used as a
 375     ; loop variable to request all register values (EAX to EDX).
 376     xor     eax, eax
 377     mov     [esp + VC_CPUID_REQUEST_REGISTER], eax
 378
 379     ; Save current GHCB MSR value
 380     mov     ecx, SEV_GHCB_MSR
 381     rdmsr
 382     mov     [esp + VC_GHCB_MSR_EAX], eax
 383     mov     [esp + VC_GHCB_MSR_EDX], edx
 384
 385 NextReg:
 386     ;
 387     ; Setup GHCB MSR
 388     ;   GHCB_MSR[63:32] = CPUID function
 389     ;   GHCB_MSR[31:30] = CPUID register
 390     ;   GHCB_MSR[11:0]  = CPUID request protocol
 391     ;
 392     mov     eax, [esp + VC_CPUID_REQUEST_REGISTER]
 393     cmp     eax, 4
 394     jge     VmmDone
 395
 396     shl     eax, GHCB_CPUID_REGISTER_SHIFT
 397     mov     edx, [esp + VC_CPUID_FUNCTION]
 398
 399     VmgExit GHCB_CPUID_REQUEST, GHCB_CPUID_RESPONSE
 400
 401     ;
 402     ; Response GHCB MSR
 403     ;   GHCB_MSR[63:32] = CPUID register value
 404     ;   GHCB_MSR[31:30] = CPUID register
 405     ;   GHCB_MSR[11:0]  = CPUID response protocol
 406     ;
 407
 408     ; Save returned value
 409     shr     eax, GHCB_CPUID_REGISTER_SHIFT
 410     mov     [esp + eax * 4], edx
 411
 412     ; Next register
 413     inc     word [esp + VC_CPUID_REQUEST_REGISTER]
 414
 415     jmp     NextReg
 416
 417 VmmDone:
 418     ;
 419     ; At this point we have all CPUID register values. Restore the GHCB MSR,
 420     ; set the return register values and return.
 421     ;
 422     mov     eax, [esp + VC_GHCB_MSR_EAX]
 423     mov     edx, [esp + VC_GHCB_MSR_EDX]
 424     mov     ecx, SEV_GHCB_MSR
 425     wrmsr
 426
 427     mov     eax, [esp + VC_CPUID_RESULT_EAX]
 428     mov     ebx, [esp + VC_CPUID_RESULT_EBX]
 429     mov     ecx, [esp + VC_CPUID_RESULT_ECX]
 430     mov     edx, [esp + VC_CPUID_RESULT_EDX]
 431
 432     add     esp, VC_VARIABLE_SIZE
 433
 434     ; Update the EIP value to skip over the now handled CPUID instruction
 435     ; (the CPUID instruction has a length of 2)
 436     add     word [esp], CPUID_INSN_LEN
 437     iret
 438
 439 ALIGN   2
 440
 441 Idtr:
 442     dw      IDT_END - IDT_BASE - 1  ; Limit
 443     dd      ADDR_OF(IDT_BASE)       ; Base
 444
 445 IdtrClear:
 446     dw      0                       ; Limit
 447     dd      0                       ; Base
 448
 449 ALIGN   16
 450
 451 ;
 452 ; The Interrupt Descriptor Table (IDT)
 453 ;   This will be used to determine if SEV-ES is enabled.  Upon execution
 454 ;   of the CPUID instruction, a VMM Communication Exception will occur.
 455 ;   This will tell us if SEV-ES is enabled.  We can use the current value
 456 ;   of the GHCB MSR to determine the SEV attributes.
 457 ;
 458 IDT_BASE:
 459 ;
 460 ; Vectors 0 - 28 (No handlers)
 461 ;
 462 %rep 29
 463     dw      0                                    ; Offset low bits 15..0
 464     dw      0x10                                 ; Selector
 465     db      0                                    ; Reserved
 466     db      0x8E                                 ; Gate Type (IA32_IDT_GATE_TYPE_INTERRUPT_32)
 467     dw      0                                    ; Offset high bits 31..16
 468 %endrep
 469 ;
 470 ; Vector 29 (VMM Communication Exception)
 471 ;
 472     dw      (ADDR_OF(SevEsIdtVmmComm) & 0xffff)  ; Offset low bits 15..0
 473     dw      0x10                                 ; Selector
 474     db      0                                    ; Reserved
 475     db      0x8E                                 ; Gate Type (IA32_IDT_GATE_TYPE_INTERRUPT_32)
 476     dw      (ADDR_OF(SevEsIdtVmmComm) >> 16)     ; Offset high bits 31..16
 477 ;
 478 ; Vectors 30 - 31 (No handlers)
 479 ;
 480 %rep 2
 481     dw      0                                    ; Offset low bits 15..0
 482     dw      0x10                                 ; Selector
 483     db      0                                    ; Reserved
 484     db      0x8E                                 ; Gate Type (IA32_IDT_GATE_TYPE_INTERRUPT_32)
 485     dw      0                                    ; Offset high bits 31..16
 486 %endrep
 487 IDT_END: