OvmfPkg/ResetVector/Ia32/PageTables64.asm

   1 ;------------------------------------------------------------------------------
   2 ; @file
   3 ; Sets the CR3 register for 64-bit paging
   4 ;
   5 ; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
   6 ; This program and the accompanying materials
   7 ; are licensed and made available under the terms and conditions of the BSD License
   8 ; which accompanies this distribution.  The full text of the license may be found at
   9 ; http://opensource.org/licenses/bsd-license.php
  10 ;
  11 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 ;
  14 ;------------------------------------------------------------------------------
  15
  16 BITS    32
  17
  18 %define PAGE_PRESENT            0x01
  19 %define PAGE_READ_WRITE         0x02
  20 %define PAGE_USER_SUPERVISOR    0x04
  21 %define PAGE_WRITE_THROUGH      0x08
  22 %define PAGE_CACHE_DISABLE     0x010
  23 %define PAGE_ACCESSED          0x020
  24 %define PAGE_DIRTY             0x040
  25 %define PAGE_PAT               0x080
  26 %define PAGE_GLOBAL           0x0100
  27 %define PAGE_2M_MBO            0x080
  28 %define PAGE_2M_PAT          0x01000
  29
  30 %define PAGE_2M_PDE_ATTR (PAGE_2M_MBO + \
  31                           PAGE_ACCESSED + \
  32                           PAGE_DIRTY + \
  33                           PAGE_READ_WRITE + \
  34                           PAGE_PRESENT)
  35
  36 %define PAGE_PDP_ATTR (PAGE_ACCESSED + \
  37                        PAGE_READ_WRITE + \
  38                        PAGE_PRESENT)
  39
  40 ; Check if Secure Encrypted Virtualization (SEV) feature is enabled
  41 ;
  42 ; If SEV is enabled then EAX will be at least 32
  43 ; If SEV is disabled then EAX will be zero.
  44 ;
  45 CheckSevFeature:
  46     ; Check if we have a valid (0x8000_001F) CPUID leaf
  47     mov       eax, 0x80000000
  48     cpuid
  49
  50     ; This check should fail on Intel or Non SEV AMD CPUs. In future if
  51     ; Intel CPUs supports this CPUID leaf then we are guranteed to have exact
  52     ; same bit definition.
  53     cmp       eax, 0x8000001f
  54     jl        NoSev
  55
  56     ; Check for memory encryption feature:
  57     ;  CPUID  Fn8000_001F[EAX] - Bit 1
  58     ;
  59     mov       eax,  0x8000001f
  60     cpuid
  61     bt        eax, 1
  62     jnc       NoSev
  63
  64     ; Check if memory encryption is enabled
  65     ;  MSR_0xC0010131 - Bit 0 (SEV enabled)
  66     mov       ecx, 0xc0010131
  67     rdmsr
  68     bt        eax, 0
  69     jnc       NoSev
  70
  71     ; Get pte bit position to enable memory encryption
  72     ; CPUID Fn8000_001F[EBX] - Bits 5:0
  73     ;
  74     mov       eax, ebx
  75     and       eax, 0x3f
  76     jmp       SevExit
  77
  78 NoSev:
  79     xor       eax, eax
  80
  81 SevExit:
  82     OneTimeCallRet CheckSevFeature
  83
  84 ;
  85 ; Modified:  EAX, EBX, ECX, EDX
  86 ;
  87 SetCr3ForPageTables64:
  88
  89     OneTimeCall   CheckSevFeature
  90     xor     edx, edx
  91     test    eax, eax
  92     jz      SevNotActive
  93
  94     ; If SEV is enabled, C-bit is always above 31
  95     sub     eax, 32
  96     bts     edx, eax
  97
  98 SevNotActive:
  99
 100     ;
 101     ; For OVMF, build some initial page tables at
 102     ; PcdOvmfSecPageTablesBase - (PcdOvmfSecPageTablesBase + 0x6000).
 103     ;
 104     ; This range should match with PcdOvmfSecPageTablesSize which is
 105     ; declared in the FDF files.
 106     ;
 107     ; At the end of PEI, the pages tables will be rebuilt into a
 108     ; more permanent location by DxeIpl.
 109     ;
 110
 111     mov     ecx, 6 * 0x1000 / 4
 112     xor     eax, eax
 113 clearPageTablesMemoryLoop:
 114     mov     dword[ecx * 4 + PT_ADDR (0) - 4], eax
 115     loop    clearPageTablesMemoryLoop
 116
 117     ;
 118     ; Top level Page Directory Pointers (1 * 512GB entry)
 119     ;
 120     mov     dword[PT_ADDR (0)], PT_ADDR (0x1000) + PAGE_PDP_ATTR
 121     mov     dword[PT_ADDR (4)], edx
 122
 123     ;
 124     ; Next level Page Directory Pointers (4 * 1GB entries => 4GB)
 125     ;
 126     mov     dword[PT_ADDR (0x1000)], PT_ADDR (0x2000) + PAGE_PDP_ATTR
 127     mov     dword[PT_ADDR (0x1004)], edx
 128     mov     dword[PT_ADDR (0x1008)], PT_ADDR (0x3000) + PAGE_PDP_ATTR
 129     mov     dword[PT_ADDR (0x100C)], edx
 130     mov     dword[PT_ADDR (0x1010)], PT_ADDR (0x4000) + PAGE_PDP_ATTR
 131     mov     dword[PT_ADDR (0x1014)], edx
 132     mov     dword[PT_ADDR (0x1018)], PT_ADDR (0x5000) + PAGE_PDP_ATTR
 133     mov     dword[PT_ADDR (0x101C)], edx
 134
 135     ;
 136     ; Page Table Entries (2048 * 2MB entries => 4GB)
 137     ;
 138     mov     ecx, 0x800
 139 pageTableEntriesLoop:
 140     mov     eax, ecx
 141     dec     eax
 142     shl     eax, 21
 143     add     eax, PAGE_2M_PDE_ATTR
 144     mov     [ecx * 8 + PT_ADDR (0x2000 - 8)], eax
 145     mov     [(ecx * 8 + PT_ADDR (0x2000 - 8)) + 4], edx
 146     loop    pageTableEntriesLoop
 147
 148     ;
 149     ; Set CR3 now that the paging structures are available
 150     ;
 151     mov     eax, PT_ADDR (0)
 152     mov     cr3, eax
 153
 154     OneTimeCallRet SetCr3ForPageTables64