1 ;------------------------------------------------------------------------------
3 ; This file includes all other code files to assemble the reset vector code
5 ; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
6 ; Copyright (c) 2020, Advanced Micro Devices, Inc. All rights reserved.<BR>
7 ; SPDX-License-Identifier: BSD-2-Clause-Patent
9 ;------------------------------------------------------------------------------
12 ; If neither ARCH_IA32 nor ARCH_X64 are defined, then try to include
13 ; Base.h to use the C pre-processor to determine the architecture.
18 #if defined (MDE_CPU_IA32)
20 #elif defined (MDE_CPU_X64)
28 %error "Only one of ARCH_IA32 or ARCH_X64 can be defined."
32 %error "Either ARCH_IA32 or ARCH_X64 must be defined."
35 %include "CommonMacros.inc"
37 %include "PostCodes.inc"
40 %include "Port80Debug.asm"
42 %include "SerialDebug.asm"
44 %include "DebugDisabled.asm"
47 %include "Ia32/SearchForBfvBase.asm"
48 %include "Ia32/SearchForSecEntry.asm"
50 %define WORK_AREA_GUEST_TYPE (FixedPcdGet32 (PcdOvmfWorkAreaBase))
55 %if (FixedPcdGet32 (PcdOvmfSecPageTablesSize) != 0x6000)
56 %error "This implementation inherently depends on PcdOvmfSecPageTablesSize"
59 %if (FixedPcdGet32 (PcdOvmfSecGhcbPageTableSize) != 0x1000)
60 %error "This implementation inherently depends on PcdOvmfSecGhcbPageTableSize"
63 %if (FixedPcdGet32 (PcdOvmfSecGhcbSize) != 0x2000)
64 %error "This implementation inherently depends on PcdOvmfSecGhcbSize"
67 %if ((FixedPcdGet32 (PcdOvmfSecGhcbBase) >> 21) != \
68 ((FixedPcdGet32 (PcdOvmfSecGhcbBase) + FixedPcdGet32 (PcdOvmfSecGhcbSize) - 1) >> 21))
69 %error "This implementation inherently depends on PcdOvmfSecGhcbBase not straddling a 2MB boundary"
72 %define TDX_BFV_RAW_DATA_OFFSET FixedPcdGet32 (PcdBfvRawDataOffset)
73 %define TDX_BFV_RAW_DATA_SIZE FixedPcdGet32 (PcdBfvRawDataSize)
74 %define TDX_BFV_MEMORY_BASE FixedPcdGet32 (PcdBfvBase)
75 %define TDX_BFV_MEMORY_SIZE FixedPcdGet32 (PcdBfvRawDataSize)
77 %define TDX_CFV_RAW_DATA_OFFSET FixedPcdGet32 (PcdCfvRawDataOffset)
78 %define TDX_CFV_RAW_DATA_SIZE FixedPcdGet32 (PcdCfvRawDataSize)
79 %define TDX_CFV_MEMORY_BASE FixedPcdGet32 (PcdCfvBase),
80 %define TDX_CFV_MEMORY_SIZE FixedPcdGet32 (PcdCfvRawDataSize),
82 %define TDX_HEAP_STACK_BASE FixedPcdGet32 (PcdOvmfSecPeiTempRamBase)
83 %define TDX_HEAP_STACK_SIZE FixedPcdGet32 (PcdOvmfSecPeiTempRamSize)
85 %define TDX_HOB_MEMORY_BASE FixedPcdGet32 (PcdOvmfSecGhcbBase)
86 %define TDX_HOB_MEMORY_SIZE FixedPcdGet32 (PcdOvmfSecGhcbSize)
88 %define TDX_INIT_MEMORY_BASE FixedPcdGet32 (PcdOvmfWorkAreaBase)
89 %define TDX_INIT_MEMORY_SIZE (FixedPcdGet32 (PcdOvmfWorkAreaSize) + FixedPcdGet32 (PcdOvmfSecGhcbBackupSize))
91 %define OVMF_PAGE_TABLE_BASE FixedPcdGet32 (PcdOvmfSecPageTablesBase)
92 %define OVMF_PAGE_TABLE_SIZE FixedPcdGet32 (PcdOvmfSecPageTablesSize)
94 %define TDX_WORK_AREA_PGTBL_READY (FixedPcdGet32 (PcdOvmfWorkAreaBase) + 4)
95 %define TDX_WORK_AREA_GPAW (FixedPcdGet32 (PcdOvmfWorkAreaBase) + 8)
97 %define PT_ADDR(Offset) (FixedPcdGet32 (PcdOvmfSecPageTablesBase) + (Offset))
99 %define GHCB_PT_ADDR (FixedPcdGet32 (PcdOvmfSecGhcbPageTableBase))
100 %define GHCB_BASE (FixedPcdGet32 (PcdOvmfSecGhcbBase))
101 %define GHCB_SIZE (FixedPcdGet32 (PcdOvmfSecGhcbSize))
102 %define SEV_ES_WORK_AREA (FixedPcdGet32 (PcdSevEsWorkAreaBase))
103 %define SEV_ES_WORK_AREA_SIZE 25
104 %define SEV_ES_WORK_AREA_STATUS_MSR (FixedPcdGet32 (PcdSevEsWorkAreaBase))
105 %define SEV_ES_WORK_AREA_RDRAND (FixedPcdGet32 (PcdSevEsWorkAreaBase) + 8)
106 %define SEV_ES_WORK_AREA_ENC_MASK (FixedPcdGet32 (PcdSevEsWorkAreaBase) + 16)
107 %define SEV_ES_WORK_AREA_RECEIVED_VC (FixedPcdGet32 (PcdSevEsWorkAreaBase) + 24)
108 %define SEV_ES_VC_TOP_OF_STACK (FixedPcdGet32 (PcdOvmfSecPeiTempRamBase) + FixedPcdGet32 (PcdOvmfSecPeiTempRamSize))
109 %define SEV_SNP_SECRETS_BASE (FixedPcdGet32 (PcdOvmfSnpSecretsBase))
110 %define SEV_SNP_SECRETS_SIZE (FixedPcdGet32 (PcdOvmfSnpSecretsSize))
111 %define CPUID_BASE (FixedPcdGet32 (PcdOvmfCpuidBase))
112 %define CPUID_SIZE (FixedPcdGet32 (PcdOvmfCpuidSize))
113 %define SNP_SEC_MEM_BASE_DESC_1 (FixedPcdGet32 (PcdOvmfSecPageTablesBase))
114 %define SNP_SEC_MEM_SIZE_DESC_1 (FixedPcdGet32 (PcdOvmfSecGhcbBase) - SNP_SEC_MEM_BASE_DESC_1)
116 ; The PcdOvmfSecGhcbBase reserves two GHCB pages. The first page is used
117 ; as GHCB shared page and second is used for bookkeeping to support the
118 ; nested GHCB in SEC phase. The bookkeeping page is mapped private. The VMM
119 ; does not need to validate the shared page but it need to validate the
122 %define SNP_SEC_MEM_BASE_DESC_2 (GHCB_BASE + 0x1000)
123 %define SNP_SEC_MEM_SIZE_DESC_2 (SEV_SNP_SECRETS_BASE - SNP_SEC_MEM_BASE_DESC_2)
124 %define SNP_SEC_MEM_BASE_DESC_3 (CPUID_BASE + CPUID_SIZE)
125 %define SNP_SEC_MEM_SIZE_DESC_3 (FixedPcdGet32 (PcdOvmfPeiMemFvBase) - SNP_SEC_MEM_BASE_DESC_3)
127 %include "X64/IntelTdxMetadata.asm"
128 %include "Ia32/Flat32ToFlat64.asm"
129 %include "Ia32/AmdSev.asm"
130 %include "Ia32/PageTables64.asm"
131 %include "Ia32/IntelTdx.asm"
132 %include "X64/OvmfSevMetadata.asm"
135 %include "Ia16/Real16ToFlat32.asm"
136 %include "Ia16/Init16.asm"
140 %define SEV_ES_AP_RESET_IP FixedPcdGet32 (PcdSevEsWorkAreaBase)
141 %define SEV_LAUNCH_SECRET_BASE FixedPcdGet32 (PcdSevLaunchSecretBase)
142 %define SEV_LAUNCH_SECRET_SIZE FixedPcdGet32 (PcdSevLaunchSecretSize)
143 %define SEV_FW_HASH_BLOCK_BASE FixedPcdGet32 (PcdQemuHashTableBase)
144 %define SEV_FW_HASH_BLOCK_SIZE FixedPcdGet32 (PcdQemuHashTableSize)
145 %include "Ia16/ResetVectorVtf0.asm"