2 Memory Detection for Virtual Machines.
4 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
5 Copyright (c) 2019, Citrix Systems, Inc.
7 SPDX-License-Identifier: BSD-2-Clause-Patent
16 // The package level header files this module uses
18 #include <IndustryStandard/Q35MchIch9.h>
22 // The Library classes this module consumes
24 #include <Library/BaseLib.h>
25 #include <Library/BaseMemoryLib.h>
26 #include <Library/DebugLib.h>
27 #include <Library/HobLib.h>
28 #include <Library/IoLib.h>
29 #include <Library/PcdLib.h>
30 #include <Library/PciLib.h>
31 #include <Library/PeimEntryPoint.h>
32 #include <Library/ResourcePublicationLib.h>
37 UINT8 mPhysMemAddressWidth
;
39 STATIC UINT32 mS3AcpiReservedMemoryBase
;
40 STATIC UINT32 mS3AcpiReservedMemorySize
;
42 STATIC UINT16 mQ35TsegMbytes
;
45 Q35TsegMbytesInitialization (
49 UINT16 ExtendedTsegMbytes
;
50 RETURN_STATUS PcdStatus
;
52 if (mHostBridgeDevId
!= INTEL_Q35_MCH_DEVICE_ID
) {
55 "%a: no TSEG (SMRAM) on host bridge DID=0x%04x; "
56 "only DID=0x%04x (Q35) is supported\n",
59 INTEL_Q35_MCH_DEVICE_ID
66 // Check if QEMU offers an extended TSEG.
68 // This can be seen from writing MCH_EXT_TSEG_MB_QUERY to the MCH_EXT_TSEG_MB
69 // register, and reading back the register.
71 // On a QEMU machine type that does not offer an extended TSEG, the initial
72 // write overwrites whatever value a malicious guest OS may have placed in
73 // the (unimplemented) register, before entering S3 or rebooting.
74 // Subsequently, the read returns MCH_EXT_TSEG_MB_QUERY unchanged.
76 // On a QEMU machine type that offers an extended TSEG, the initial write
77 // triggers an update to the register. Subsequently, the value read back
78 // (which is guaranteed to differ from MCH_EXT_TSEG_MB_QUERY) tells us the
79 // number of megabytes.
81 PciWrite16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB
), MCH_EXT_TSEG_MB_QUERY
);
82 ExtendedTsegMbytes
= PciRead16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB
));
83 if (ExtendedTsegMbytes
== MCH_EXT_TSEG_MB_QUERY
) {
84 mQ35TsegMbytes
= PcdGet16 (PcdQ35TsegMbytes
);
90 "%a: QEMU offers an extended TSEG (%d MB)\n",
94 PcdStatus
= PcdSet16S (PcdQ35TsegMbytes
, ExtendedTsegMbytes
);
95 ASSERT_RETURN_ERROR (PcdStatus
);
96 mQ35TsegMbytes
= ExtendedTsegMbytes
;
101 GetHighestSystemMemoryAddress (
105 EFI_E820_ENTRY64
*E820Map
;
106 UINT32 E820EntriesCount
;
107 EFI_E820_ENTRY64
*Entry
;
110 UINT64 HighestAddress
;
115 Status
= XenGetE820Map (&E820Map
, &E820EntriesCount
);
116 ASSERT_EFI_ERROR (Status
);
118 for (Loop
= 0; Loop
< E820EntriesCount
; Loop
++) {
119 Entry
= E820Map
+ Loop
;
120 EntryEnd
= Entry
->BaseAddr
+ Entry
->Length
;
122 if (Entry
->Type
== EfiAcpiAddressRangeMemory
&&
123 EntryEnd
> HighestAddress
) {
125 if (Below4gb
&& (EntryEnd
<= BASE_4GB
)) {
126 HighestAddress
= EntryEnd
;
127 } else if (!Below4gb
&& (EntryEnd
>= BASE_4GB
)) {
128 HighestAddress
= EntryEnd
;
134 // Round down the end address.
136 return HighestAddress
& ~(UINT64
)EFI_PAGE_MASK
;
140 GetSystemMemorySizeBelow4gb (
148 // In PVH case, there is no CMOS, we have to calculate the memory size
149 // from parsing the E820
151 if (XenPvhDetected ()) {
152 UINT64 HighestAddress
;
154 HighestAddress
= GetHighestSystemMemoryAddress (TRUE
);
155 ASSERT (HighestAddress
> 0 && HighestAddress
<= BASE_4GB
);
157 return HighestAddress
;
161 // CMOS 0x34/0x35 specifies the system memory above 16 MB.
162 // * CMOS(0x35) is the high byte
163 // * CMOS(0x34) is the low byte
164 // * The size is specified in 64kb chunks
165 // * Since this is memory above 16MB, the 16MB must be added
166 // into the calculation to get the total memory size.
169 Cmos0x34
= (UINT8
) CmosRead8 (0x34);
170 Cmos0x35
= (UINT8
) CmosRead8 (0x35);
172 return (UINT32
) (((UINTN
)((Cmos0x35
<< 8) + Cmos0x34
) << 16) + SIZE_16MB
);
176 Initialize the mPhysMemAddressWidth variable, based on CPUID data.
179 AddressWidthInitialization (
185 AsmCpuid (0x80000000, &RegEax
, NULL
, NULL
, NULL
);
186 if (RegEax
>= 0x80000008) {
187 AsmCpuid (0x80000008, &RegEax
, NULL
, NULL
, NULL
);
188 mPhysMemAddressWidth
= (UINT8
) RegEax
;
190 mPhysMemAddressWidth
= 36;
194 // IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses.
196 ASSERT (mPhysMemAddressWidth
<= 52);
197 if (mPhysMemAddressWidth
> 48) {
198 mPhysMemAddressWidth
= 48;
203 Calculate the cap for the permanent PEI memory.
211 BOOLEAN Page1GSupport
;
219 // If DXE is 32-bit, then just return the traditional 64 MB cap.
222 if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode
)) {
228 // Dependent on physical address width, PEI memory allocations can be
229 // dominated by the page tables built for 64-bit DXE. So we key the cap off
230 // of those. The code below is based on CreateIdentityMappingPageTables() in
231 // "MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c".
233 Page1GSupport
= FALSE
;
234 if (PcdGetBool (PcdUse1GPageTable
)) {
235 AsmCpuid (0x80000000, &RegEax
, NULL
, NULL
, NULL
);
236 if (RegEax
>= 0x80000001) {
237 AsmCpuid (0x80000001, NULL
, NULL
, NULL
, &RegEdx
);
238 if ((RegEdx
& BIT26
) != 0) {
239 Page1GSupport
= TRUE
;
244 if (mPhysMemAddressWidth
<= 39) {
246 PdpEntries
= 1 << (mPhysMemAddressWidth
- 30);
247 ASSERT (PdpEntries
<= 0x200);
249 Pml4Entries
= 1 << (mPhysMemAddressWidth
- 39);
250 ASSERT (Pml4Entries
<= 0x200);
254 TotalPages
= Page1GSupport
? Pml4Entries
+ 1 :
255 (PdpEntries
+ 1) * Pml4Entries
+ 1;
256 ASSERT (TotalPages
<= 0x40201);
259 // Add 64 MB for miscellaneous allocations. Note that for
260 // mPhysMemAddressWidth values close to 36, the cap will actually be
261 // dominated by this increment.
263 return (UINT32
)(EFI_PAGES_TO_SIZE (TotalPages
) + SIZE_64MB
);
268 Publish PEI core memory
270 @return EFI_SUCCESS The PEIM initialized successfully.
279 EFI_PHYSICAL_ADDRESS MemoryBase
;
281 UINT32 LowerMemorySize
;
284 LowerMemorySize
= GetSystemMemorySizeBelow4gb ();
286 if (mBootMode
== BOOT_ON_S3_RESUME
) {
287 MemoryBase
= mS3AcpiReservedMemoryBase
;
288 MemorySize
= mS3AcpiReservedMemorySize
;
290 PeiMemoryCap
= GetPeiMemoryCap ();
291 DEBUG ((DEBUG_INFO
, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",
292 __FUNCTION__
, mPhysMemAddressWidth
, PeiMemoryCap
>> 10));
295 // Determine the range of memory to use during PEI
298 PcdGet32 (PcdOvmfDxeMemFvBase
) + PcdGet32 (PcdOvmfDxeMemFvSize
);
299 MemorySize
= LowerMemorySize
- MemoryBase
;
300 if (MemorySize
> PeiMemoryCap
) {
301 MemoryBase
= LowerMemorySize
- PeiMemoryCap
;
302 MemorySize
= PeiMemoryCap
;
307 // Publish this memory to the PEI Core
309 Status
= PublishSystemMemory(MemoryBase
, MemorySize
);
310 ASSERT_EFI_ERROR (Status
);
317 Publish system RAM and reserve memory regions
321 InitializeRamRegions (
325 XenPublishRamRegions ();
327 if (mBootMode
!= BOOT_ON_S3_RESUME
) {
329 // Reserve the lock box storage area
331 // Since this memory range will be used on S3 resume, it must be
332 // reserved as ACPI NVS.
334 // If S3 is unsupported, then various drivers might still write to the
335 // LockBox area. We ought to prevent DXE from serving allocation requests
336 // such that they would overlap the LockBox storage.
339 (VOID
*)(UINTN
) PcdGet32 (PcdOvmfLockBoxStorageBase
),
340 (UINTN
) PcdGet32 (PcdOvmfLockBoxStorageSize
)
342 BuildMemoryAllocationHob (
343 (EFI_PHYSICAL_ADDRESS
)(UINTN
) PcdGet32 (PcdOvmfLockBoxStorageBase
),
344 (UINT64
)(UINTN
) PcdGet32 (PcdOvmfLockBoxStorageSize
),