2 PCI Root Bridge Io Protocol implementation
4 Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials are
6 licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include "PciHostBridge.h"
18 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR SpaceDesp
[TypeMax
];
19 EFI_ACPI_END_TAG_DESCRIPTOR EndDesp
;
20 } RESOURCE_CONFIGURATION
;
22 RESOURCE_CONFIGURATION Configuration
= {
23 {{0x8A, 0x2B, 1, 0, 0, 0, 0, 0, 0, 0},
24 {0x8A, 0x2B, 0, 0, 0, 32, 0, 0, 0, 0},
25 {0x8A, 0x2B, 0, 0, 6, 32, 0, 0, 0, 0},
26 {0x8A, 0x2B, 0, 0, 0, 64, 0, 0, 0, 0},
27 {0x8A, 0x2B, 0, 0, 6, 64, 0, 0, 0, 0},
28 {0x8A, 0x2B, 2, 0, 0, 0, 0, 0, 0, 0}},
33 // Protocol Member Function Prototypes
37 Polls an address in memory mapped I/O space until an exit condition is met, or
40 This function provides a standard way to poll a PCI memory location. A PCI memory read
41 operation is performed at the PCI memory address specified by Address for the width specified
42 by Width. The result of this PCI memory read operation is stored in Result. This PCI memory
43 read operation is repeated until either a timeout of Delay 100 ns units has expired, or (Result &
44 Mask) is equal to Value.
46 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
47 @param[in] Width Signifies the width of the memory operations.
48 @param[in] Address The base address of the memory operations. The caller is
49 responsible for aligning Address if required.
50 @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask
51 are ignored. The bits in the bytes below Width which are zero in
52 Mask are ignored when polling the memory address.
53 @param[in] Value The comparison value used for the polling exit criteria.
54 @param[in] Delay The number of 100 ns units to poll. Note that timer available may
55 be of poorer granularity.
56 @param[out] Result Pointer to the last value read from the memory location.
58 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
59 @retval EFI_INVALID_PARAMETER Width is invalid.
60 @retval EFI_INVALID_PARAMETER Result is NULL.
61 @retval EFI_TIMEOUT Delay expired before a match occurred.
62 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
68 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
69 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
78 Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is
79 satisfied or after a defined duration.
81 This function provides a standard way to poll a PCI I/O location. A PCI I/O read operation is
82 performed at the PCI I/O address specified by Address for the width specified by Width.
83 The result of this PCI I/O read operation is stored in Result. This PCI I/O read operation is
84 repeated until either a timeout of Delay 100 ns units has expired, or (Result & Mask) is equal
87 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
88 @param[in] Width Signifies the width of the I/O operations.
89 @param[in] Address The base address of the I/O operations. The caller is responsible
90 for aligning Address if required.
91 @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask
92 are ignored. The bits in the bytes below Width which are zero in
93 Mask are ignored when polling the I/O address.
94 @param[in] Value The comparison value used for the polling exit criteria.
95 @param[in] Delay The number of 100 ns units to poll. Note that timer available may
96 be of poorer granularity.
97 @param[out] Result Pointer to the last value read from the memory location.
99 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
100 @retval EFI_INVALID_PARAMETER Width is invalid.
101 @retval EFI_INVALID_PARAMETER Result is NULL.
102 @retval EFI_TIMEOUT Delay expired before a match occurred.
103 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
109 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
110 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
119 Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
121 The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller
122 registers in the PCI root bridge memory space.
123 The memory operations are carried out exactly as requested. The caller is responsible for satisfying
124 any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.
126 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
127 @param[in] Width Signifies the width of the memory operation.
128 @param[in] Address The base address of the memory operation. The caller is
129 responsible for aligning the Address if required.
130 @param[in] Count The number of memory operations to perform. Bytes moved is
131 Width size * Count, starting at Address.
132 @param[out] Buffer For read operations, the destination buffer to store the results. For
133 write operations, the source buffer to write data from.
135 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
136 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
137 @retval EFI_INVALID_PARAMETER Buffer is NULL.
138 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
143 RootBridgeIoMemRead (
144 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
145 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
152 Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
154 The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller
155 registers in the PCI root bridge memory space.
156 The memory operations are carried out exactly as requested. The caller is responsible for satisfying
157 any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.
159 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
160 @param[in] Width Signifies the width of the memory operation.
161 @param[in] Address The base address of the memory operation. The caller is
162 responsible for aligning the Address if required.
163 @param[in] Count The number of memory operations to perform. Bytes moved is
164 Width size * Count, starting at Address.
165 @param[in] Buffer For read operations, the destination buffer to store the results. For
166 write operations, the source buffer to write data from.
168 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
169 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
170 @retval EFI_INVALID_PARAMETER Buffer is NULL.
171 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
175 RootBridgeIoMemWrite (
176 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
177 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
184 Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
186 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
187 @param[in] Width Signifies the width of the memory operations.
188 @param[in] UserAddress The base address of the I/O operation. The caller is responsible for
189 aligning the Address if required.
190 @param[in] Count The number of I/O operations to perform. Bytes moved is Width
191 size * Count, starting at Address.
192 @param[out] UserBuffer For read operations, the destination buffer to store the results. For
193 write operations, the source buffer to write data from.
195 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
196 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
197 @retval EFI_INVALID_PARAMETER Buffer is NULL.
198 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
204 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
205 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
206 IN UINT64 UserAddress
,
212 Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
214 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
215 @param[in] Width Signifies the width of the memory operations.
216 @param[in] UserAddress The base address of the I/O operation. The caller is responsible for
217 aligning the Address if required.
218 @param[in] Count The number of I/O operations to perform. Bytes moved is Width
219 size * Count, starting at Address.
220 @param[in] UserBuffer For read operations, the destination buffer to store the results. For
221 write operations, the source buffer to write data from.
223 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
224 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
225 @retval EFI_INVALID_PARAMETER Buffer is NULL.
226 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
231 RootBridgeIoIoWrite (
232 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
233 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
234 IN UINT64 UserAddress
,
240 Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI
241 root bridge memory space.
243 The CopyMem() function enables a PCI driver to copy one region of PCI root bridge memory
244 space to another region of PCI root bridge memory space. This is especially useful for video scroll
245 operation on a memory mapped video buffer.
246 The memory operations are carried out exactly as requested. The caller is responsible for satisfying
247 any alignment and memory width restrictions that a PCI root bridge on a platform might require.
249 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.
250 @param[in] Width Signifies the width of the memory operations.
251 @param[in] DestAddress The destination address of the memory operation. The caller is
252 responsible for aligning the DestAddress if required.
253 @param[in] SrcAddress The source address of the memory operation. The caller is
254 responsible for aligning the SrcAddress if required.
255 @param[in] Count The number of memory operations to perform. Bytes moved is
256 Width size * Count, starting at DestAddress and SrcAddress.
258 @retval EFI_SUCCESS The data was copied from one memory region to another memory region.
259 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
260 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
265 RootBridgeIoCopyMem (
266 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
267 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
268 IN UINT64 DestAddress
,
269 IN UINT64 SrcAddress
,
274 Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
276 The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration
277 registers for a PCI controller.
278 The PCI Configuration operations are carried out exactly as requested. The caller is responsible for
279 any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might
282 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
283 @param[in] Width Signifies the width of the memory operations.
284 @param[in] Address The address within the PCI configuration space for the PCI controller.
285 @param[in] Count The number of PCI configuration operations to perform. Bytes
286 moved is Width size * Count, starting at Address.
287 @param[out] Buffer For read operations, the destination buffer to store the results. For
288 write operations, the source buffer to write data from.
290 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
291 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
292 @retval EFI_INVALID_PARAMETER Buffer is NULL.
293 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
298 RootBridgeIoPciRead (
299 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
300 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
307 Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
309 The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration
310 registers for a PCI controller.
311 The PCI Configuration operations are carried out exactly as requested. The caller is responsible for
312 any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might
315 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
316 @param[in] Width Signifies the width of the memory operations.
317 @param[in] Address The address within the PCI configuration space for the PCI controller.
318 @param[in] Count The number of PCI configuration operations to perform. Bytes
319 moved is Width size * Count, starting at Address.
320 @param[in] Buffer For read operations, the destination buffer to store the results. For
321 write operations, the source buffer to write data from.
323 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
324 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
325 @retval EFI_INVALID_PARAMETER Buffer is NULL.
326 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
331 RootBridgeIoPciWrite (
332 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
333 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
340 Provides the PCI controller-specific addresses required to access system memory from a
343 The Map() function provides the PCI controller specific addresses needed to access system
344 memory. This function is used to map system memory for PCI bus master DMA accesses.
346 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
347 @param[in] Operation Indicates if the bus master is going to read or write to system memory.
348 @param[in] HostAddress The system memory address to map to the PCI controller.
349 @param[in, out] NumberOfBytes On input the number of bytes to map. On output the number of bytes that were mapped.
350 @param[out] DeviceAddress The resulting map address for the bus master PCI controller to use
351 to access the system memory's HostAddress.
352 @param[out] Mapping The value to pass to Unmap() when the bus master DMA operation is complete.
354 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
355 @retval EFI_INVALID_PARAMETER Operation is invalid.
356 @retval EFI_INVALID_PARAMETER HostAddress is NULL.
357 @retval EFI_INVALID_PARAMETER NumberOfBytes is NULL.
358 @retval EFI_INVALID_PARAMETER DeviceAddress is NULL.
359 @retval EFI_INVALID_PARAMETER Mapping is NULL.
360 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
361 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
362 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
368 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
369 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation
,
370 IN VOID
*HostAddress
,
371 IN OUT UINTN
*NumberOfBytes
,
372 OUT EFI_PHYSICAL_ADDRESS
*DeviceAddress
,
377 Completes the Map() operation and releases any corresponding resources.
379 The Unmap() function completes the Map() operation and releases any corresponding resources.
380 If the operation was an EfiPciOperationBusMasterWrite or
381 EfiPciOperationBusMasterWrite64, the data is committed to the target system memory.
382 Any resources used for the mapping are freed.
384 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
385 @param[in] Mapping The mapping value returned from Map().
387 @retval EFI_SUCCESS The range was unmapped.
388 @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().
389 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
395 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
400 Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or
401 EfiPciOperationBusMasterCommonBuffer64 mapping.
403 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
404 @param Type This parameter is not used and must be ignored.
405 @param MemoryType The type of memory to allocate, EfiBootServicesData or EfiRuntimeServicesData.
406 @param Pages The number of pages to allocate.
407 @param HostAddress A pointer to store the base system memory address of the allocated range.
408 @param Attributes The requested bit mask of attributes for the allocated range. Only
409 the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, EFI_PCI_ATTRIBUTE_MEMORY_CACHED,
410 and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this function.
412 @retval EFI_SUCCESS The requested memory pages were allocated.
413 @retval EFI_INVALID_PARAMETER MemoryType is invalid.
414 @retval EFI_INVALID_PARAMETER HostAddress is NULL.
415 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
416 MEMORY_WRITE_COMBINE, MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.
417 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
422 RootBridgeIoAllocateBuffer (
423 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
424 IN EFI_ALLOCATE_TYPE Type
,
425 IN EFI_MEMORY_TYPE MemoryType
,
427 OUT VOID
**HostAddress
,
432 Frees memory that was allocated with AllocateBuffer().
434 The FreeBuffer() function frees memory that was allocated with AllocateBuffer().
436 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
437 @param Pages The number of pages to free.
438 @param HostAddress The base system memory address of the allocated range.
440 @retval EFI_SUCCESS The requested memory pages were freed.
441 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
442 was not allocated with AllocateBuffer().
447 RootBridgeIoFreeBuffer (
448 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
450 OUT VOID
*HostAddress
454 Flushes all PCI posted write transactions from a PCI host bridge to system memory.
456 The Flush() function flushes any PCI posted write transactions from a PCI host bridge to system
457 memory. Posted write transactions are generated by PCI bus masters when they perform write
458 transactions to target addresses in system memory.
459 This function does not flush posted write transactions from any PCI bridges. A PCI controller
460 specific action must be taken to guarantee that the posted write transactions have been flushed from
461 the PCI controller and from all the PCI bridges into the PCI host bridge. This is typically done with
462 a PCI read transaction from the PCI controller prior to calling Flush().
464 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
466 @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host
467 bridge to system memory.
468 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI
469 host bridge due to a hardware error.
475 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
479 Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the
480 attributes that a PCI root bridge is currently using.
482 The GetAttributes() function returns the mask of attributes that this PCI root bridge supports
483 and the mask of attributes that the PCI root bridge is currently using.
485 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
486 @param Supported A pointer to the mask of attributes that this PCI root bridge
487 supports setting with SetAttributes().
488 @param Attributes A pointer to the mask of attributes that this PCI root bridge is
491 @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI root
492 bridge supports is returned in Supports. If Attributes is
493 not NULL, then the attributes that the PCI root bridge is currently
494 using is returned in Attributes.
495 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
500 RootBridgeIoGetAttributes (
501 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
502 OUT UINT64
*Supported
,
503 OUT UINT64
*Attributes
507 Sets attributes for a resource range on a PCI root bridge.
509 The SetAttributes() function sets the attributes specified in Attributes for the PCI root
510 bridge on the resource range specified by ResourceBase and ResourceLength. Since the
511 granularity of setting these attributes may vary from resource type to resource type, and from
512 platform to platform, the actual resource range and the one passed in by the caller may differ. As a
513 result, this function may set the attributes specified by Attributes on a larger resource range
514 than the caller requested. The actual range is returned in ResourceBase and
515 ResourceLength. The caller is responsible for verifying that the actual range for which the
516 attributes were set is acceptable.
518 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
519 @param[in] Attributes The mask of attributes to set. If the attribute bit
520 MEMORY_WRITE_COMBINE, MEMORY_CACHED, or
521 MEMORY_DISABLE is set, then the resource range is specified by
522 ResourceBase and ResourceLength. If
523 MEMORY_WRITE_COMBINE, MEMORY_CACHED, and
524 MEMORY_DISABLE are not set, then ResourceBase and
525 ResourceLength are ignored, and may be NULL.
526 @param[in, out] ResourceBase A pointer to the base address of the resource range to be modified
527 by the attributes specified by Attributes.
528 @param[in, out] ResourceLength A pointer to the length of the resource range to be modified by the
529 attributes specified by Attributes.
531 @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.
532 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.
533 @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
538 RootBridgeIoSetAttributes (
539 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
540 IN UINT64 Attributes
,
541 IN OUT UINT64
*ResourceBase
,
542 IN OUT UINT64
*ResourceLength
546 Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI 2.0
547 resource descriptors.
549 There are only two resource descriptor types from the ACPI Specification that may be used to
550 describe the current resources allocated to a PCI root bridge. These are the QWORD Address
551 Space Descriptor (ACPI 2.0 Section 6.4.3.5.1), and the End Tag (ACPI 2.0 Section 6.4.2.8). The
552 QWORD Address Space Descriptor can describe memory, I/O, and bus number ranges for dynamic
553 or fixed resources. The configuration of a PCI root bridge is described with one or more QWORD
554 Address Space Descriptors followed by an End Tag.
556 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
557 @param[out] Resources A pointer to the ACPI 2.0 resource descriptors that describe the
558 current configuration of this PCI root bridge. The storage for the
559 ACPI 2.0 resource descriptors is allocated by this function. The
560 caller must treat the return buffer as read-only data, and the buffer
561 must not be freed by the caller.
563 @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.
564 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.
565 @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
570 RootBridgeIoConfiguration (
571 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
576 // Memory Controller Pci Root Bridge Io Module Variables
578 EFI_METRONOME_ARCH_PROTOCOL
*mMetronome
;
581 // Lookup table for increment values based on transfer widths
583 UINT8 mInStride
[] = {
584 1, // EfiPciWidthUint8
585 2, // EfiPciWidthUint16
586 4, // EfiPciWidthUint32
587 8, // EfiPciWidthUint64
588 0, // EfiPciWidthFifoUint8
589 0, // EfiPciWidthFifoUint16
590 0, // EfiPciWidthFifoUint32
591 0, // EfiPciWidthFifoUint64
592 1, // EfiPciWidthFillUint8
593 2, // EfiPciWidthFillUint16
594 4, // EfiPciWidthFillUint32
595 8 // EfiPciWidthFillUint64
599 // Lookup table for increment values based on transfer widths
601 UINT8 mOutStride
[] = {
602 1, // EfiPciWidthUint8
603 2, // EfiPciWidthUint16
604 4, // EfiPciWidthUint32
605 8, // EfiPciWidthUint64
606 1, // EfiPciWidthFifoUint8
607 2, // EfiPciWidthFifoUint16
608 4, // EfiPciWidthFifoUint32
609 8, // EfiPciWidthFifoUint64
610 0, // EfiPciWidthFillUint8
611 0, // EfiPciWidthFillUint16
612 0, // EfiPciWidthFillUint32
613 0 // EfiPciWidthFillUint64
618 Construct the Pci Root Bridge Io protocol
620 @param Protocol Point to protocol instance
621 @param HostBridgeHandle Handle of host bridge
622 @param Attri Attribute of host bridge
623 @param ResAppeture ResourceAppeture for host bridge
625 @retval EFI_SUCCESS Success to initialize the Pci Root Bridge.
629 RootBridgeConstructor (
630 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*Protocol
,
631 IN EFI_HANDLE HostBridgeHandle
,
633 IN PCI_ROOT_BRIDGE_RESOURCE_APPETURE
*ResAppeture
637 PCI_ROOT_BRIDGE_INSTANCE
*PrivateData
;
638 PCI_RESOURCE_TYPE Index
;
640 PrivateData
= DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (Protocol
);
643 // The host to pci bridge, the host memory and io addresses are
644 // direct mapped to pci addresses, so no need translate, set bases to 0.
646 PrivateData
->MemBase
= ResAppeture
->MemBase
;
647 PrivateData
->IoBase
= ResAppeture
->IoBase
;
650 // The host bridge only supports 32bit addressing for memory
651 // and standard IA32 16bit io
653 PrivateData
->MemLimit
= ResAppeture
->MemLimit
;
654 PrivateData
->IoLimit
= ResAppeture
->IoLimit
;
657 // Bus Appeture for this Root Bridge (Possible Range)
659 PrivateData
->BusBase
= ResAppeture
->BusBase
;
660 PrivateData
->BusLimit
= ResAppeture
->BusLimit
;
663 // Specific for this chipset
665 for (Index
= TypeIo
; Index
< TypeMax
; Index
++) {
666 PrivateData
->ResAllocNode
[Index
].Type
= Index
;
667 PrivateData
->ResAllocNode
[Index
].Base
= 0;
668 PrivateData
->ResAllocNode
[Index
].Length
= 0;
669 PrivateData
->ResAllocNode
[Index
].Status
= ResNone
;
672 PrivateData
->PciAddress
= 0xCF8;
673 PrivateData
->PciData
= 0xCFC;
675 PrivateData
->RootBridgeAttrib
= Attri
;
677 PrivateData
->Supports
= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO
| EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO
| \
678 EFI_PCI_ATTRIBUTE_ISA_IO_16
| EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO
| \
679 EFI_PCI_ATTRIBUTE_VGA_MEMORY
| \
680 EFI_PCI_ATTRIBUTE_VGA_IO_16
| EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16
;
681 PrivateData
->Attributes
= PrivateData
->Supports
;
683 Protocol
->ParentHandle
= HostBridgeHandle
;
685 Protocol
->PollMem
= RootBridgeIoPollMem
;
686 Protocol
->PollIo
= RootBridgeIoPollIo
;
688 Protocol
->Mem
.Read
= RootBridgeIoMemRead
;
689 Protocol
->Mem
.Write
= RootBridgeIoMemWrite
;
691 Protocol
->Io
.Read
= RootBridgeIoIoRead
;
692 Protocol
->Io
.Write
= RootBridgeIoIoWrite
;
694 Protocol
->CopyMem
= RootBridgeIoCopyMem
;
696 Protocol
->Pci
.Read
= RootBridgeIoPciRead
;
697 Protocol
->Pci
.Write
= RootBridgeIoPciWrite
;
699 Protocol
->Map
= RootBridgeIoMap
;
700 Protocol
->Unmap
= RootBridgeIoUnmap
;
702 Protocol
->AllocateBuffer
= RootBridgeIoAllocateBuffer
;
703 Protocol
->FreeBuffer
= RootBridgeIoFreeBuffer
;
705 Protocol
->Flush
= RootBridgeIoFlush
;
707 Protocol
->GetAttributes
= RootBridgeIoGetAttributes
;
708 Protocol
->SetAttributes
= RootBridgeIoSetAttributes
;
710 Protocol
->Configuration
= RootBridgeIoConfiguration
;
712 Protocol
->SegmentNumber
= 0;
714 Status
= gBS
->LocateProtocol (&gEfiMetronomeArchProtocolGuid
, NULL
, (VOID
**)&mMetronome
);
715 ASSERT_EFI_ERROR (Status
);
721 Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridge IO.
723 The I/O operations are carried out exactly as requested. The caller is responsible
724 for satisfying any alignment and I/O width restrictions that a PI System on a
725 platform might require. For example on some platforms, width requests of
726 EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
727 be handled by the driver.
729 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
730 @param[in] OperationType I/O operation type: IO/MMIO/PCI.
731 @param[in] Width Signifies the width of the I/O or Memory operation.
732 @param[in] Address The base address of the I/O operation.
733 @param[in] Count The number of I/O operations to perform. The number of
734 bytes moved is Width size * Count, starting at Address.
735 @param[in] Buffer For read operations, the destination buffer to store the results.
736 For write operations, the source buffer from which to write data.
738 @retval EFI_SUCCESS The parameters for this request pass the checks.
739 @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
740 @retval EFI_INVALID_PARAMETER Buffer is NULL.
741 @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
742 @retval EFI_UNSUPPORTED The address range specified by Address, Width,
743 and Count is not valid for this PI system.
747 RootBridgeIoCheckParameter (
748 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
749 IN OPERATION_TYPE OperationType
,
750 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
756 PCI_ROOT_BRIDGE_INSTANCE
*PrivateData
;
757 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS
*PciRbAddr
;
763 // Check to see if Buffer is NULL
765 if (Buffer
== NULL
) {
766 return EFI_INVALID_PARAMETER
;
770 // Check to see if Width is in the valid range
772 if (Width
< EfiPciWidthUint8
|| Width
>= EfiPciWidthMaximum
) {
773 return EFI_INVALID_PARAMETER
;
777 // For FIFO type, the target address won't increase during the access,
778 // so treat Count as 1
780 if (Width
>= EfiPciWidthFifoUint8
&& Width
<= EfiPciWidthFifoUint64
) {
785 // Check to see if Width is in the valid range for I/O Port operations
787 Width
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
) (Width
& 0x03);
788 if ((OperationType
!= MemOperation
) && (Width
== EfiPciWidthUint64
)) {
790 return EFI_INVALID_PARAMETER
;
794 // Check to see if Address is aligned
796 if ((Address
& (UINT64
)(mInStride
[Width
] - 1)) != 0) {
797 return EFI_UNSUPPORTED
;
800 PrivateData
= DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This
);
803 // Check to see if any address associated with this transfer exceeds the maximum
804 // allowed address. The maximum address implied by the parameters passed in is
805 // Address + Size * Count. If the following condition is met, then the transfer
808 // Address + Size * Count > Limit + 1
810 // Since Limit can be the maximum integer value supported by the CPU and Count
811 // can also be the maximum integer value supported by the CPU, this range
812 // check must be adjusted to avoid all oveflow conditions.
814 // The following form of the range check is equivalent but assumes that
815 // Limit is of the form (2^n - 1).
817 if (OperationType
== IoOperation
) {
818 Base
= PrivateData
->IoBase
;
819 Limit
= PrivateData
->IoLimit
;
820 } else if (OperationType
== MemOperation
) {
821 Base
= PrivateData
->MemBase
;
822 Limit
= PrivateData
->MemLimit
;
824 PciRbAddr
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS
*) &Address
;
825 if (PciRbAddr
->Bus
< PrivateData
->BusBase
|| PciRbAddr
->Bus
> PrivateData
->BusLimit
) {
826 return EFI_INVALID_PARAMETER
;
829 if (PciRbAddr
->Device
> MAX_PCI_DEVICE_NUMBER
|| PciRbAddr
->Function
> MAX_PCI_FUNCTION_NUMBER
) {
830 return EFI_INVALID_PARAMETER
;
833 if (PciRbAddr
->ExtendedRegister
!= 0) {
834 Address
= PciRbAddr
->ExtendedRegister
;
836 Address
= PciRbAddr
->Register
;
839 Limit
= MAX_PCI_REG_ADDRESS
;
842 if (Address
< Base
) {
843 return EFI_INVALID_PARAMETER
;
847 if (Address
> Limit
) {
848 return EFI_UNSUPPORTED
;
851 MaxCount
= RShiftU64 (Limit
, Width
);
852 if (MaxCount
< (Count
- 1)) {
853 return EFI_UNSUPPORTED
;
855 if (Address
> LShiftU64 (MaxCount
- Count
+ 1, Width
)) {
856 return EFI_UNSUPPORTED
;
864 Internal help function for read and write memory space.
866 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
867 @param[in] Write Switch value for Read or Write.
868 @param[in] Width Signifies the width of the memory operations.
869 @param[in] UserAddress The address within the PCI configuration space for the PCI controller.
870 @param[in] Count The number of PCI configuration operations to perform. Bytes
871 moved is Width size * Count, starting at Address.
872 @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For
873 write operations, the source buffer to write data from.
875 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
876 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
877 @retval EFI_INVALID_PARAMETER Buffer is NULL.
878 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
883 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
885 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
894 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth
;
897 Status
= RootBridgeIoCheckParameter (This
, MemOperation
, Width
, Address
, Count
, Buffer
);
898 if (EFI_ERROR (Status
)) {
902 InStride
= mInStride
[Width
];
903 OutStride
= mOutStride
[Width
];
904 OperationWidth
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
) (Width
& 0x03);
905 for (Uint8Buffer
= Buffer
; Count
> 0; Address
+= InStride
, Uint8Buffer
+= OutStride
, Count
--) {
907 switch (OperationWidth
) {
908 case EfiPciWidthUint8
:
909 MmioWrite8 ((UINTN
)Address
, *Uint8Buffer
);
911 case EfiPciWidthUint16
:
912 MmioWrite16 ((UINTN
)Address
, *((UINT16
*)Uint8Buffer
));
914 case EfiPciWidthUint32
:
915 MmioWrite32 ((UINTN
)Address
, *((UINT32
*)Uint8Buffer
));
917 case EfiPciWidthUint64
:
918 MmioWrite64 ((UINTN
)Address
, *((UINT64
*)Uint8Buffer
));
922 // The RootBridgeIoCheckParameter call above will ensure that this
923 // path is not taken.
929 switch (OperationWidth
) {
930 case EfiPciWidthUint8
:
931 *Uint8Buffer
= MmioRead8 ((UINTN
)Address
);
933 case EfiPciWidthUint16
:
934 *((UINT16
*)Uint8Buffer
) = MmioRead16 ((UINTN
)Address
);
936 case EfiPciWidthUint32
:
937 *((UINT32
*)Uint8Buffer
) = MmioRead32 ((UINTN
)Address
);
939 case EfiPciWidthUint64
:
940 *((UINT64
*)Uint8Buffer
) = MmioRead64 ((UINTN
)Address
);
944 // The RootBridgeIoCheckParameter call above will ensure that this
945 // path is not taken.
956 Internal help function for read and write IO space.
958 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
959 @param[in] Write Switch value for Read or Write.
960 @param[in] Width Signifies the width of the memory operations.
961 @param[in] UserAddress The address within the PCI configuration space for the PCI controller.
962 @param[in] Count The number of PCI configuration operations to perform. Bytes
963 moved is Width size * Count, starting at Address.
964 @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For
965 write operations, the source buffer to write data from.
967 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
968 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
969 @retval EFI_INVALID_PARAMETER Buffer is NULL.
970 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
975 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
977 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
986 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth
;
989 Status
= RootBridgeIoCheckParameter (This
, IoOperation
, Width
, Address
, Count
, Buffer
);
990 if (EFI_ERROR (Status
)) {
994 InStride
= mInStride
[Width
];
995 OutStride
= mOutStride
[Width
];
996 OperationWidth
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
) (Width
& 0x03);
997 for (Uint8Buffer
= Buffer
; Count
> 0; Address
+= InStride
, Uint8Buffer
+= OutStride
, Count
--) {
999 switch (OperationWidth
) {
1000 case EfiPciWidthUint8
:
1001 IoWrite8 ((UINTN
)Address
, *Uint8Buffer
);
1003 case EfiPciWidthUint16
:
1004 IoWrite16 ((UINTN
)Address
, *((UINT16
*)Uint8Buffer
));
1006 case EfiPciWidthUint32
:
1007 IoWrite32 ((UINTN
)Address
, *((UINT32
*)Uint8Buffer
));
1011 // The RootBridgeIoCheckParameter call above will ensure that this
1012 // path is not taken.
1018 switch (OperationWidth
) {
1019 case EfiPciWidthUint8
:
1020 *Uint8Buffer
= IoRead8 ((UINTN
)Address
);
1022 case EfiPciWidthUint16
:
1023 *((UINT16
*)Uint8Buffer
) = IoRead16 ((UINTN
)Address
);
1025 case EfiPciWidthUint32
:
1026 *((UINT32
*)Uint8Buffer
) = IoRead32 ((UINTN
)Address
);
1030 // The RootBridgeIoCheckParameter call above will ensure that this
1031 // path is not taken.
1042 Internal help function for read and write PCI configuration space.
1044 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1045 @param[in] Write Switch value for Read or Write.
1046 @param[in] Width Signifies the width of the memory operations.
1047 @param[in] UserAddress The address within the PCI configuration space for the PCI controller.
1048 @param[in] Count The number of PCI configuration operations to perform. Bytes
1049 moved is Width size * Count, starting at Address.
1050 @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For
1051 write operations, the source buffer to write data from.
1053 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
1054 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
1055 @retval EFI_INVALID_PARAMETER Buffer is NULL.
1056 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1061 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1063 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1072 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth
;
1074 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS
*PciRbAddr
;
1077 Status
= RootBridgeIoCheckParameter (This
, PciOperation
, Width
, Address
, Count
, Buffer
);
1078 if (EFI_ERROR (Status
)) {
1082 PciRbAddr
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS
*) &Address
;
1084 PcieRegAddr
= (UINTN
) PCI_LIB_ADDRESS (
1087 PciRbAddr
->Function
,
1088 (PciRbAddr
->ExtendedRegister
!= 0) ? \
1089 PciRbAddr
->ExtendedRegister
:
1093 InStride
= mInStride
[Width
];
1094 OutStride
= mOutStride
[Width
];
1095 OperationWidth
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
) (Width
& 0x03);
1096 for (Uint8Buffer
= Buffer
; Count
> 0; PcieRegAddr
+= InStride
, Uint8Buffer
+= OutStride
, Count
--) {
1098 switch (OperationWidth
) {
1099 case EfiPciWidthUint8
:
1100 PciWrite8 (PcieRegAddr
, *Uint8Buffer
);
1102 case EfiPciWidthUint16
:
1103 PciWrite16 (PcieRegAddr
, *((UINT16
*)Uint8Buffer
));
1105 case EfiPciWidthUint32
:
1106 PciWrite32 (PcieRegAddr
, *((UINT32
*)Uint8Buffer
));
1110 // The RootBridgeIoCheckParameter call above will ensure that this
1111 // path is not taken.
1117 switch (OperationWidth
) {
1118 case EfiPciWidthUint8
:
1119 *Uint8Buffer
= PciRead8 (PcieRegAddr
);
1121 case EfiPciWidthUint16
:
1122 *((UINT16
*)Uint8Buffer
) = PciRead16 (PcieRegAddr
);
1124 case EfiPciWidthUint32
:
1125 *((UINT32
*)Uint8Buffer
) = PciRead32 (PcieRegAddr
);
1129 // The RootBridgeIoCheckParameter call above will ensure that this
1130 // path is not taken.
1142 Polls an address in memory mapped I/O space until an exit condition is met, or
1145 This function provides a standard way to poll a PCI memory location. A PCI memory read
1146 operation is performed at the PCI memory address specified by Address for the width specified
1147 by Width. The result of this PCI memory read operation is stored in Result. This PCI memory
1148 read operation is repeated until either a timeout of Delay 100 ns units has expired, or (Result &
1149 Mask) is equal to Value.
1151 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1152 @param[in] Width Signifies the width of the memory operations.
1153 @param[in] Address The base address of the memory operations. The caller is
1154 responsible for aligning Address if required.
1155 @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask
1156 are ignored. The bits in the bytes below Width which are zero in
1157 Mask are ignored when polling the memory address.
1158 @param[in] Value The comparison value used for the polling exit criteria.
1159 @param[in] Delay The number of 100 ns units to poll. Note that timer available may
1160 be of poorer granularity.
1161 @param[out] Result Pointer to the last value read from the memory location.
1163 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
1164 @retval EFI_INVALID_PARAMETER Width is invalid.
1165 @retval EFI_INVALID_PARAMETER Result is NULL.
1166 @retval EFI_TIMEOUT Delay expired before a match occurred.
1167 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1172 RootBridgeIoPollMem (
1173 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1174 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1183 UINT64 NumberOfTicks
;
1186 if (Result
== NULL
) {
1187 return EFI_INVALID_PARAMETER
;
1190 if (Width
< 0 || Width
> EfiPciWidthUint64
) {
1191 return EFI_INVALID_PARAMETER
;
1195 // No matter what, always do a single poll.
1197 Status
= This
->Mem
.Read (This
, Width
, Address
, 1, Result
);
1198 if (EFI_ERROR (Status
)) {
1201 if ((*Result
& Mask
) == Value
) {
1211 // Determine the proper # of metronome ticks to wait for polling the
1212 // location. The nuber of ticks is Roundup (Delay / mMetronome->TickPeriod)+1
1213 // The "+1" to account for the possibility of the first tick being short
1214 // because we started in the middle of a tick.
1216 // BugBug: overriding mMetronome->TickPeriod with UINT32 until Metronome
1217 // protocol definition is updated.
1219 NumberOfTicks
= DivU64x32Remainder (Delay
, (UINT32
) mMetronome
->TickPeriod
, &Remainder
);
1220 if (Remainder
!= 0) {
1225 while (NumberOfTicks
!= 0) {
1227 mMetronome
->WaitForTick (mMetronome
, 1);
1229 Status
= This
->Mem
.Read (This
, Width
, Address
, 1, Result
);
1230 if (EFI_ERROR (Status
)) {
1234 if ((*Result
& Mask
) == Value
) {
1245 Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is
1246 satisfied or after a defined duration.
1248 This function provides a standard way to poll a PCI I/O location. A PCI I/O read operation is
1249 performed at the PCI I/O address specified by Address for the width specified by Width.
1250 The result of this PCI I/O read operation is stored in Result. This PCI I/O read operation is
1251 repeated until either a timeout of Delay 100 ns units has expired, or (Result & Mask) is equal
1254 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1255 @param[in] Width Signifies the width of the I/O operations.
1256 @param[in] Address The base address of the I/O operations. The caller is responsible
1257 for aligning Address if required.
1258 @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask
1259 are ignored. The bits in the bytes below Width which are zero in
1260 Mask are ignored when polling the I/O address.
1261 @param[in] Value The comparison value used for the polling exit criteria.
1262 @param[in] Delay The number of 100 ns units to poll. Note that timer available may
1263 be of poorer granularity.
1264 @param[out] Result Pointer to the last value read from the memory location.
1266 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
1267 @retval EFI_INVALID_PARAMETER Width is invalid.
1268 @retval EFI_INVALID_PARAMETER Result is NULL.
1269 @retval EFI_TIMEOUT Delay expired before a match occurred.
1270 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1275 RootBridgeIoPollIo (
1276 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1277 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1286 UINT64 NumberOfTicks
;
1290 // No matter what, always do a single poll.
1293 if (Result
== NULL
) {
1294 return EFI_INVALID_PARAMETER
;
1297 if (Width
< 0 || Width
> EfiPciWidthUint64
) {
1298 return EFI_INVALID_PARAMETER
;
1301 Status
= This
->Io
.Read (This
, Width
, Address
, 1, Result
);
1302 if (EFI_ERROR (Status
)) {
1305 if ((*Result
& Mask
) == Value
) {
1315 // Determine the proper # of metronome ticks to wait for polling the
1316 // location. The number of ticks is Roundup (Delay / mMetronome->TickPeriod)+1
1317 // The "+1" to account for the possibility of the first tick being short
1318 // because we started in the middle of a tick.
1320 NumberOfTicks
= DivU64x32Remainder (Delay
, (UINT32
)mMetronome
->TickPeriod
, &Remainder
);
1321 if (Remainder
!= 0) {
1326 while (NumberOfTicks
!= 0) {
1328 mMetronome
->WaitForTick (mMetronome
, 1);
1330 Status
= This
->Io
.Read (This
, Width
, Address
, 1, Result
);
1331 if (EFI_ERROR (Status
)) {
1335 if ((*Result
& Mask
) == Value
) {
1346 Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
1348 The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller
1349 registers in the PCI root bridge memory space.
1350 The memory operations are carried out exactly as requested. The caller is responsible for satisfying
1351 any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.
1353 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1354 @param[in] Width Signifies the width of the memory operation.
1355 @param[in] Address The base address of the memory operation. The caller is
1356 responsible for aligning the Address if required.
1357 @param[in] Count The number of memory operations to perform. Bytes moved is
1358 Width size * Count, starting at Address.
1359 @param[out] Buffer For read operations, the destination buffer to store the results. For
1360 write operations, the source buffer to write data from.
1362 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
1363 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
1364 @retval EFI_INVALID_PARAMETER Buffer is NULL.
1365 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1370 RootBridgeIoMemRead (
1371 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1372 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1378 return RootBridgeIoMemRW (This
, FALSE
, Width
, Address
, Count
, Buffer
);
1382 Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
1384 The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller
1385 registers in the PCI root bridge memory space.
1386 The memory operations are carried out exactly as requested. The caller is responsible for satisfying
1387 any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.
1389 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1390 @param[in] Width Signifies the width of the memory operation.
1391 @param[in] Address The base address of the memory operation. The caller is
1392 responsible for aligning the Address if required.
1393 @param[in] Count The number of memory operations to perform. Bytes moved is
1394 Width size * Count, starting at Address.
1395 @param[in] Buffer For read operations, the destination buffer to store the results. For
1396 write operations, the source buffer to write data from.
1398 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
1399 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
1400 @retval EFI_INVALID_PARAMETER Buffer is NULL.
1401 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1405 RootBridgeIoMemWrite (
1406 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1407 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1413 return RootBridgeIoMemRW (This
, TRUE
, Width
, Address
, Count
, Buffer
);
1417 Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
1419 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1420 @param[in] Width Signifies the width of the memory operations.
1421 @param[in] Address The base address of the I/O operation. The caller is responsible for
1422 aligning the Address if required.
1423 @param[in] Count The number of I/O operations to perform. Bytes moved is Width
1424 size * Count, starting at Address.
1425 @param[out] Buffer For read operations, the destination buffer to store the results. For
1426 write operations, the source buffer to write data from.
1428 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
1429 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
1430 @retval EFI_INVALID_PARAMETER Buffer is NULL.
1431 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1436 RootBridgeIoIoRead (
1437 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1438 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1444 return RootBridgeIoIoRW (This
, FALSE
, Width
, Address
, Count
, Buffer
);
1448 Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
1450 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1451 @param[in] Width Signifies the width of the memory operations.
1452 @param[in] Address The base address of the I/O operation. The caller is responsible for
1453 aligning the Address if required.
1454 @param[in] Count The number of I/O operations to perform. Bytes moved is Width
1455 size * Count, starting at Address.
1456 @param[in] Buffer For read operations, the destination buffer to store the results. For
1457 write operations, the source buffer to write data from.
1459 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
1460 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
1461 @retval EFI_INVALID_PARAMETER Buffer is NULL.
1462 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1467 RootBridgeIoIoWrite (
1468 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1469 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1475 return RootBridgeIoIoRW (This
, TRUE
, Width
, Address
, Count
, Buffer
);
1479 Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI
1480 root bridge memory space.
1482 The CopyMem() function enables a PCI driver to copy one region of PCI root bridge memory
1483 space to another region of PCI root bridge memory space. This is especially useful for video scroll
1484 operation on a memory mapped video buffer.
1485 The memory operations are carried out exactly as requested. The caller is responsible for satisfying
1486 any alignment and memory width restrictions that a PCI root bridge on a platform might require.
1488 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.
1489 @param[in] Width Signifies the width of the memory operations.
1490 @param[in] DestAddress The destination address of the memory operation. The caller is
1491 responsible for aligning the DestAddress if required.
1492 @param[in] SrcAddress The source address of the memory operation. The caller is
1493 responsible for aligning the SrcAddress if required.
1494 @param[in] Count The number of memory operations to perform. Bytes moved is
1495 Width size * Count, starting at DestAddress and SrcAddress.
1497 @retval EFI_SUCCESS The data was copied from one memory region to another memory region.
1498 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
1499 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1504 RootBridgeIoCopyMem (
1505 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1506 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1507 IN UINT64 DestAddress
,
1508 IN UINT64 SrcAddress
,
1518 if (Width
< 0 || Width
> EfiPciWidthUint64
) {
1519 return EFI_INVALID_PARAMETER
;
1522 if (DestAddress
== SrcAddress
) {
1526 Stride
= (UINTN
)(1 << Width
);
1529 if ((DestAddress
> SrcAddress
) && (DestAddress
< (SrcAddress
+ Count
* Stride
))) {
1531 SrcAddress
= SrcAddress
+ (Count
-1) * Stride
;
1532 DestAddress
= DestAddress
+ (Count
-1) * Stride
;
1535 for (Index
= 0;Index
< Count
;Index
++) {
1536 Status
= RootBridgeIoMemRead (
1543 if (EFI_ERROR (Status
)) {
1546 Status
= RootBridgeIoMemWrite (
1553 if (EFI_ERROR (Status
)) {
1557 SrcAddress
+= Stride
;
1558 DestAddress
+= Stride
;
1560 SrcAddress
-= Stride
;
1561 DestAddress
-= Stride
;
1568 Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
1570 The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration
1571 registers for a PCI controller.
1572 The PCI Configuration operations are carried out exactly as requested. The caller is responsible for
1573 any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might
1576 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1577 @param[in] Width Signifies the width of the memory operations.
1578 @param[in] Address The address within the PCI configuration space for the PCI controller.
1579 @param[in] Count The number of PCI configuration operations to perform. Bytes
1580 moved is Width size * Count, starting at Address.
1581 @param[out] Buffer For read operations, the destination buffer to store the results. For
1582 write operations, the source buffer to write data from.
1584 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
1585 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
1586 @retval EFI_INVALID_PARAMETER Buffer is NULL.
1587 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1592 RootBridgeIoPciRead (
1593 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1594 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1600 return RootBridgeIoPciRW (This
, FALSE
, Width
, Address
, Count
, Buffer
);
1604 Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
1606 The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration
1607 registers for a PCI controller.
1608 The PCI Configuration operations are carried out exactly as requested. The caller is responsible for
1609 any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might
1612 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1613 @param[in] Width Signifies the width of the memory operations.
1614 @param[in] Address The address within the PCI configuration space for the PCI controller.
1615 @param[in] Count The number of PCI configuration operations to perform. Bytes
1616 moved is Width size * Count, starting at Address.
1617 @param[in] Buffer For read operations, the destination buffer to store the results. For
1618 write operations, the source buffer to write data from.
1620 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
1621 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
1622 @retval EFI_INVALID_PARAMETER Buffer is NULL.
1623 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1628 RootBridgeIoPciWrite (
1629 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1630 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1636 return RootBridgeIoPciRW (This
, TRUE
, Width
, Address
, Count
, Buffer
);
1640 Provides the PCI controller-specific addresses required to access system memory from a
1643 The Map() function provides the PCI controller specific addresses needed to access system
1644 memory. This function is used to map system memory for PCI bus master DMA accesses.
1646 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1647 @param[in] Operation Indicates if the bus master is going to read or write to system memory.
1648 @param[in] HostAddress The system memory address to map to the PCI controller.
1649 @param[in, out] NumberOfBytes On input the number of bytes to map. On output the number of bytes that were mapped.
1650 @param[out] DeviceAddress The resulting map address for the bus master PCI controller to use
1651 to access the system memory's HostAddress.
1652 @param[out] Mapping The value to pass to Unmap() when the bus master DMA operation is complete.
1654 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
1655 @retval EFI_INVALID_PARAMETER Operation is invalid.
1656 @retval EFI_INVALID_PARAMETER HostAddress is NULL.
1657 @retval EFI_INVALID_PARAMETER NumberOfBytes is NULL.
1658 @retval EFI_INVALID_PARAMETER DeviceAddress is NULL.
1659 @retval EFI_INVALID_PARAMETER Mapping is NULL.
1660 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
1661 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
1662 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1668 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1669 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation
,
1670 IN VOID
*HostAddress
,
1671 IN OUT UINTN
*NumberOfBytes
,
1672 OUT EFI_PHYSICAL_ADDRESS
*DeviceAddress
,
1677 EFI_PHYSICAL_ADDRESS PhysicalAddress
;
1680 if (HostAddress
== NULL
|| NumberOfBytes
== NULL
|| DeviceAddress
== NULL
|| Mapping
== NULL
) {
1681 return EFI_INVALID_PARAMETER
;
1685 // Initialize the return values to their defaults
1690 // Make sure that Operation is valid
1692 if (Operation
< 0 || Operation
>= EfiPciOperationMaximum
) {
1693 return EFI_INVALID_PARAMETER
;
1697 // Most PCAT like chipsets can not handle performing DMA above 4GB.
1698 // If any part of the DMA transfer being mapped is above 4GB, then
1699 // map the DMA transfer to a buffer below 4GB.
1701 PhysicalAddress
= (EFI_PHYSICAL_ADDRESS
) (UINTN
) HostAddress
;
1702 if ((PhysicalAddress
+ *NumberOfBytes
) > 0x100000000ULL
) {
1705 // Common Buffer operations can not be remapped. If the common buffer
1706 // if above 4GB, then it is not possible to generate a mapping, so return
1709 if (Operation
== EfiPciOperationBusMasterCommonBuffer
|| Operation
== EfiPciOperationBusMasterCommonBuffer64
) {
1710 return EFI_UNSUPPORTED
;
1714 // Allocate a MAP_INFO structure to remember the mapping when Unmap() is
1717 Status
= gBS
->AllocatePool (
1718 EfiBootServicesData
,
1722 if (EFI_ERROR (Status
)) {
1728 // Return a pointer to the MAP_INFO structure in Mapping
1733 // Initialize the MAP_INFO structure
1735 MapInfo
->Operation
= Operation
;
1736 MapInfo
->NumberOfBytes
= *NumberOfBytes
;
1737 MapInfo
->NumberOfPages
= EFI_SIZE_TO_PAGES(*NumberOfBytes
);
1738 MapInfo
->HostAddress
= PhysicalAddress
;
1739 MapInfo
->MappedHostAddress
= 0x00000000ffffffff;
1742 // Allocate a buffer below 4GB to map the transfer to.
1744 Status
= gBS
->AllocatePages (
1746 EfiBootServicesData
,
1747 MapInfo
->NumberOfPages
,
1748 &MapInfo
->MappedHostAddress
1750 if (EFI_ERROR (Status
)) {
1751 gBS
->FreePool (MapInfo
);
1757 // If this is a read operation from the Bus Master's point of view,
1758 // then copy the contents of the real buffer into the mapped buffer
1759 // so the Bus Master can read the contents of the real buffer.
1761 if (Operation
== EfiPciOperationBusMasterRead
|| Operation
== EfiPciOperationBusMasterRead64
) {
1763 (VOID
*)(UINTN
)MapInfo
->MappedHostAddress
,
1764 (VOID
*)(UINTN
)MapInfo
->HostAddress
,
1765 MapInfo
->NumberOfBytes
1770 // The DeviceAddress is the address of the maped buffer below 4GB
1772 *DeviceAddress
= MapInfo
->MappedHostAddress
;
1775 // The transfer is below 4GB, so the DeviceAddress is simply the HostAddress
1777 *DeviceAddress
= PhysicalAddress
;
1784 Completes the Map() operation and releases any corresponding resources.
1786 The Unmap() function completes the Map() operation and releases any corresponding resources.
1787 If the operation was an EfiPciOperationBusMasterWrite or
1788 EfiPciOperationBusMasterWrite64, the data is committed to the target system memory.
1789 Any resources used for the mapping are freed.
1791 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1792 @param[in] Mapping The mapping value returned from Map().
1794 @retval EFI_SUCCESS The range was unmapped.
1795 @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().
1796 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
1802 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1809 // See if the Map() operation associated with this Unmap() required a mapping buffer.
1810 // If a mapping buffer was not required, then this function simply returns EFI_SUCCESS.
1812 if (Mapping
!= NULL
) {
1814 // Get the MAP_INFO structure from Mapping
1816 MapInfo
= (MAP_INFO
*)Mapping
;
1819 // If this is a write operation from the Bus Master's point of view,
1820 // then copy the contents of the mapped buffer into the real buffer
1821 // so the processor can read the contents of the real buffer.
1823 if (MapInfo
->Operation
== EfiPciOperationBusMasterWrite
|| MapInfo
->Operation
== EfiPciOperationBusMasterWrite64
) {
1825 (VOID
*)(UINTN
)MapInfo
->HostAddress
,
1826 (VOID
*)(UINTN
)MapInfo
->MappedHostAddress
,
1827 MapInfo
->NumberOfBytes
1832 // Free the mapped buffer and the MAP_INFO structure.
1834 gBS
->FreePages (MapInfo
->MappedHostAddress
, MapInfo
->NumberOfPages
);
1835 gBS
->FreePool (Mapping
);
1841 Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or
1842 EfiPciOperationBusMasterCommonBuffer64 mapping.
1844 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1845 @param Type This parameter is not used and must be ignored.
1846 @param MemoryType The type of memory to allocate, EfiBootServicesData or EfiRuntimeServicesData.
1847 @param Pages The number of pages to allocate.
1848 @param HostAddress A pointer to store the base system memory address of the allocated range.
1849 @param Attributes The requested bit mask of attributes for the allocated range. Only
1850 the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, EFI_PCI_ATTRIBUTE_MEMORY_CACHED,
1851 and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this function.
1853 @retval EFI_SUCCESS The requested memory pages were allocated.
1854 @retval EFI_INVALID_PARAMETER MemoryType is invalid.
1855 @retval EFI_INVALID_PARAMETER HostAddress is NULL.
1856 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
1857 MEMORY_WRITE_COMBINE, MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.
1858 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
1863 RootBridgeIoAllocateBuffer (
1864 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1865 IN EFI_ALLOCATE_TYPE Type
,
1866 IN EFI_MEMORY_TYPE MemoryType
,
1868 OUT VOID
**HostAddress
,
1869 IN UINT64 Attributes
1873 EFI_PHYSICAL_ADDRESS PhysicalAddress
;
1876 // Validate Attributes
1878 if ((Attributes
& EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER
) != 0) {
1879 return EFI_UNSUPPORTED
;
1883 // Check for invalid inputs
1885 if (HostAddress
== NULL
) {
1886 return EFI_INVALID_PARAMETER
;
1890 // The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData
1892 if (MemoryType
!= EfiBootServicesData
&& MemoryType
!= EfiRuntimeServicesData
) {
1893 return EFI_INVALID_PARAMETER
;
1897 // Limit allocations to memory below 4GB
1899 PhysicalAddress
= (EFI_PHYSICAL_ADDRESS
)(0xffffffff);
1901 Status
= gBS
->AllocatePages (AllocateMaxAddress
, MemoryType
, Pages
, &PhysicalAddress
);
1902 if (EFI_ERROR (Status
)) {
1906 *HostAddress
= (VOID
*)(UINTN
)PhysicalAddress
;
1912 Frees memory that was allocated with AllocateBuffer().
1914 The FreeBuffer() function frees memory that was allocated with AllocateBuffer().
1916 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1917 @param Pages The number of pages to free.
1918 @param HostAddress The base system memory address of the allocated range.
1920 @retval EFI_SUCCESS The requested memory pages were freed.
1921 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
1922 was not allocated with AllocateBuffer().
1927 RootBridgeIoFreeBuffer (
1928 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1930 OUT VOID
*HostAddress
1933 return gBS
->FreePages ((EFI_PHYSICAL_ADDRESS
) (UINTN
) HostAddress
, Pages
);
1937 Flushes all PCI posted write transactions from a PCI host bridge to system memory.
1939 The Flush() function flushes any PCI posted write transactions from a PCI host bridge to system
1940 memory. Posted write transactions are generated by PCI bus masters when they perform write
1941 transactions to target addresses in system memory.
1942 This function does not flush posted write transactions from any PCI bridges. A PCI controller
1943 specific action must be taken to guarantee that the posted write transactions have been flushed from
1944 the PCI controller and from all the PCI bridges into the PCI host bridge. This is typically done with
1945 a PCI read transaction from the PCI controller prior to calling Flush().
1947 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1949 @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host
1950 bridge to system memory.
1951 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI
1952 host bridge due to a hardware error.
1958 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
1962 // not supported yet
1968 Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the
1969 attributes that a PCI root bridge is currently using.
1971 The GetAttributes() function returns the mask of attributes that this PCI root bridge supports
1972 and the mask of attributes that the PCI root bridge is currently using.
1974 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1975 @param Supported A pointer to the mask of attributes that this PCI root bridge
1976 supports setting with SetAttributes().
1977 @param Attributes A pointer to the mask of attributes that this PCI root bridge is
1980 @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI root
1981 bridge supports is returned in Supports. If Attributes is
1982 not NULL, then the attributes that the PCI root bridge is currently
1983 using is returned in Attributes.
1984 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
1989 RootBridgeIoGetAttributes (
1990 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1991 OUT UINT64
*Supported
,
1992 OUT UINT64
*Attributes
1995 PCI_ROOT_BRIDGE_INSTANCE
*PrivateData
;
1997 PrivateData
= DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This
);
1999 if (Attributes
== NULL
&& Supported
== NULL
) {
2000 return EFI_INVALID_PARAMETER
;
2004 // Set the return value for Supported and Attributes
2006 if (Supported
!= NULL
) {
2007 *Supported
= PrivateData
->Supports
;
2010 if (Attributes
!= NULL
) {
2011 *Attributes
= PrivateData
->Attributes
;
2018 Sets attributes for a resource range on a PCI root bridge.
2020 The SetAttributes() function sets the attributes specified in Attributes for the PCI root
2021 bridge on the resource range specified by ResourceBase and ResourceLength. Since the
2022 granularity of setting these attributes may vary from resource type to resource type, and from
2023 platform to platform, the actual resource range and the one passed in by the caller may differ. As a
2024 result, this function may set the attributes specified by Attributes on a larger resource range
2025 than the caller requested. The actual range is returned in ResourceBase and
2026 ResourceLength. The caller is responsible for verifying that the actual range for which the
2027 attributes were set is acceptable.
2029 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
2030 @param[in] Attributes The mask of attributes to set. If the attribute bit
2031 MEMORY_WRITE_COMBINE, MEMORY_CACHED, or
2032 MEMORY_DISABLE is set, then the resource range is specified by
2033 ResourceBase and ResourceLength. If
2034 MEMORY_WRITE_COMBINE, MEMORY_CACHED, and
2035 MEMORY_DISABLE are not set, then ResourceBase and
2036 ResourceLength are ignored, and may be NULL.
2037 @param[in, out] ResourceBase A pointer to the base address of the resource range to be modified
2038 by the attributes specified by Attributes.
2039 @param[in, out] ResourceLength A pointer to the length of the resource range to be modified by the
2040 attributes specified by Attributes.
2042 @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.
2043 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.
2044 @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
2049 RootBridgeIoSetAttributes (
2050 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
2051 IN UINT64 Attributes
,
2052 IN OUT UINT64
*ResourceBase
,
2053 IN OUT UINT64
*ResourceLength
2056 PCI_ROOT_BRIDGE_INSTANCE
*PrivateData
;
2058 PrivateData
= DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This
);
2060 if (Attributes
!= 0) {
2061 if ((Attributes
& (~(PrivateData
->Supports
))) != 0) {
2062 return EFI_UNSUPPORTED
;
2067 // This is a generic driver for a PC-AT class system. It does not have any
2068 // chipset specific knowlegde, so none of the attributes can be set or
2069 // cleared. Any attempt to set attribute that are already set will succeed,
2070 // and any attempt to set an attribute that is not supported will fail.
2072 if (Attributes
& (~PrivateData
->Attributes
)) {
2073 return EFI_UNSUPPORTED
;
2080 Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI 2.0
2081 resource descriptors.
2083 There are only two resource descriptor types from the ACPI Specification that may be used to
2084 describe the current resources allocated to a PCI root bridge. These are the QWORD Address
2085 Space Descriptor (ACPI 2.0 Section 6.4.3.5.1), and the End Tag (ACPI 2.0 Section 6.4.2.8). The
2086 QWORD Address Space Descriptor can describe memory, I/O, and bus number ranges for dynamic
2087 or fixed resources. The configuration of a PCI root bridge is described with one or more QWORD
2088 Address Space Descriptors followed by an End Tag.
2090 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
2091 @param[out] Resources A pointer to the ACPI 2.0 resource descriptors that describe the
2092 current configuration of this PCI root bridge. The storage for the
2093 ACPI 2.0 resource descriptors is allocated by this function. The
2094 caller must treat the return buffer as read-only data, and the buffer
2095 must not be freed by the caller.
2097 @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.
2098 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.
2099 @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
2104 RootBridgeIoConfiguration (
2105 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
2106 OUT VOID
**Resources
2109 PCI_ROOT_BRIDGE_INSTANCE
*PrivateData
;
2112 PrivateData
= DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This
);
2114 for (Index
= 0; Index
< TypeMax
; Index
++) {
2115 if (PrivateData
->ResAllocNode
[Index
].Status
== ResAllocated
) {
2116 Configuration
.SpaceDesp
[Index
].AddrRangeMin
= PrivateData
->ResAllocNode
[Index
].Base
;
2117 Configuration
.SpaceDesp
[Index
].AddrRangeMax
= PrivateData
->ResAllocNode
[Index
].Base
+ PrivateData
->ResAllocNode
[Index
].Length
- 1;
2118 Configuration
.SpaceDesp
[Index
].AddrLen
= PrivateData
->ResAllocNode
[Index
].Length
;
2122 *Resources
= &Configuration
;