2 CPU EIST control methods
4 Copyright (c) 2013-2015 Intel Corporation.
6 SPDX-License-Identifier: BSD-2-Clause-Patent
19 External (PDC0, IntObj)
20 External (CFGD, FieldUnitObj)
21 External(\_PR.CPU0, DeviceObj)
27 Return(ZERO) // Return All States Available.
33 // If GV3 is supported and OSPM is capable of direct access to
34 // performance state MSR, we use MSR method
37 // PDCx[0] = Indicates whether OSPM is capable of direct access to
38 // performance state MSR.
40 If(LAnd(And(CFGD,0x0001), And(PDC0,0x0001)))
42 Return(Package() // MSR Method
44 ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
45 ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
51 // Otherwise, we use smi method
53 Return(Package() // SMI Method
55 ResourceTemplate(){Register(SystemIO,16,0,0xB2)},
56 ResourceTemplate(){Register(SystemIO, 8,0,0xB3)}
63 // If OSPM is capable of direct access to performance state MSR,
64 // we report NPSS, otherwise, we report SPSS.
75 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
76 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
77 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
78 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
79 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
80 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
81 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
82 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
83 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
84 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
85 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
86 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}
91 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
92 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
93 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
94 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
95 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
96 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
97 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
98 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
99 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
100 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
101 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
102 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}
108 // If CMP is suppored, we report the dependency with two processors
110 If(And(CFGD,0x1000000))
113 // If OSPM is capable of hardware coordination of P-states, we report
114 // the dependency with hardware coordination.
116 // PDCx[11] = Indicates whether OSPM is capable of hardware coordination of P-states
125 0xFE, // Coord Type- HW_ALL.
132 // Otherwise, the dependency with OSPM coordination
139 0xFC, // Coord Type- SW_ALL.
146 // Otherwise, we report the dependency with one processor
153 0xFC, // Coord Type- SW_ALL.