2 CPU T-state control methods
4 Copyright (c) 2013-2015 Intel Corporation.
6 SPDX-License-Identifier: BSD-2-Clause-Patent
19 External (PDC0, IntObj)
20 External (CFGD, FieldUnitObj)
21 External(\_PR.CPU0, DeviceObj)
28 Return(ZERO) // Return All States Available.
31 Name(TPTC, ResourceTemplate()
33 Memory32Fixed(ReadOnly, 0, 0, FIX1) // IO APIC
37 // If OSPM is capable of direct access to on demand throttling MSR,
38 // we use MSR method;otherwise we use IO method.
41 // PDCx[2] = Indicates whether OSPM is capable of direct access to
42 // on demand throttling MSR.
48 Return(Package() // MSR Method
50 ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
51 ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
55 Return(Package() // IO Method
58 // PM IO base ("PMBALVL0" will be updated at runtime)
60 ResourceTemplate(){Register(SystemIO, 4, 1, 0x304C564C41424D50)},
61 ResourceTemplate(){Register(SystemIO, 4, 1, 0x304C564C41424D50)}
67 // _TSS returned package for IO Method
71 Package(){100, 1000, 0, 0x00, 0}
75 // _TSS returned package for MSR Method
79 Package(){100, 1000, 0, 0x00, 0}
86 // If OSPM is capable of direct access to on demand throttling MSR,
87 // we report TSSM;otherwise report TSSI.
99 // If CMP is suppored, we report the dependency with two processors
101 If(LAnd(And(CFGD, 0x1000000), LNot(And(PDC0, 4))))
110 0xFD, // Coord Type- SW_ANY
117 // Otherwise, we report the dependency with one processor
126 0xFC, // Coord Type- SW_ALL